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EDA365电子论坛网»电子社区 › EDA工具&PCB设计 › Cadence Allegro论坛 › 【求助】OrCAD Library Builder 导出封装出错
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【求助】OrCAD Library Builder 导出封装出错

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sty3362950349

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发表于 2019-9-29 16:21 | 只看该作者 |只看大图 回帖奖励 |倒序浏览 |阅读模式

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求助各位大神，library builder导出的封装出错，没有引脚和焊盘
! B* |  U2 w7 N' w3 K2 ^) a" sallegro版本为17.2，library builder为17-2 2016
* e* ]- ^- ^$ w) P命令窗口显示如下：
1 w; G  I9 B1 P7 @- `Loading axlcore.cxt
6 r, _0 b3 |. rStarting new design...
0 \3 l+ f( ^6 B7 F( dReading Footprint XML
. }% ]1 {% `2 i3 U1 ^% x8 bCreating padstacks+ n% N' e/ O$ ]; [
Starting new design...
; ^- _! R9 ]& F: n# S0 a: U* S  APeRForming DRC...
, ^( l% p: v+ p0 JMultithreaded DRC update (4 threads).
! n/ B7 e( G* e, [( K& R5 p" N  j3 {No DRC errors detected.8 H7 \% c2 M+ l0 Y- ]* M; ]
Performing a partial design check before saving.
: `0 g7 k  B- @Writing design to disk.$ m0 }1 X8 I% t: Q! b  S
'b187_30.pad' saved to disk.
' }7 _) {3 X" a4 I1 T- o$ N  f(SPMHUT-48): Scaled value has been rounded off.
+ x9 S) F7 F: a- Z) a) F' g  g4 N- HStarting new design...
2 q9 r8 ]& [. J' RPerforming a partial design check before saving.
$ `( f! y( Z; \* Z% s; V  j3 w, YWriting design to disk.0 D; N4 O8 h& X* W
'b100m200k200.pad' saved to disk.
' w) q+ i  w4 R& A( H3 N" QStarting new design...
* T8 i8 g+ E$ w( B; yCreating shape symbol 'D:/Z_PERSONAL_FILE/cadence_project_file/symbols/QFP50P1290X1290X120-65N/QFP50P1290X1290X120-65N_Allegro/s700c50_top.ssm'./ |( F& {' x# ?( p( ~9 b
Starting Create symbol...; C3 X1 ^( q& x8 ~6 e
create_sym completed successfully, use Viewlog to review the log file.
- a1 A% m" `4 C2 icreate_sym completed successfully, use Viewlog to review the log file.
: `& u$ P& H5 xSymbol 'D:/Z_PERSONAL_FILE/Cadence_project_file/symbols/QFP50P1290X1290X120-65N/QFP50P1290X1290X120-65N_Allegro/s700c50_top.ssm' created.
0 f6 S6 |% }# @*WARNING* (axlShapeMerge): Invalid database id argument - nil
, U' T1 |% S; l0 b+ B0 |$ v" R/ KPerforming a partial design check before saving.
& C' K/ ]. ]% |7 t# c$ a) cWriting design to disk.  v$ ]/ t9 s; h$ n# B+ E
's700c50_TOP.dra' saved to disk.2 v' t8 Y/ C. C1 k9 g$ n+ M  g
Starting new design...
9 J, w# p- K* C- b% ^8 tCreating shape symbol 'D:/Z_PERSONAL_FILE/Cadence_project_file/symbols/QFP50P1290X1290X120-65N/QFP50P1290X1290X120-65N_Allegro/s700c50_sm.ssm'.8 E4 q" K# t( _/ x& N
Starting Create symbol...
  |% \1 l3 L8 b2 gcreate_sym completed successfully, use Viewlog to review the log file.
; n6 L* \8 U- O9 u9 L& v% hcreate_sym completed successfully, use Viewlog to review the log file.' c/ o! T- @& w
Symbol 'D:/Z_PERSONAL_FILE/Cadence_project_file/symbols/QFP50P1290X1290X120-65N/QFP50P1290X1290X120-65N_Allegro/s700c50_sm.ssm' created.3 T1 W1 P9 h" u- |# O/ V  v
*WARNING* (axlShapeMerge): Invalid database id argument - nil
4 ^( V$ D! b3 Y# _  U- `( k4 B8 z" NPerforming a partial design check before saving.
7 ?; @+ Z6 K* ^% ]" I( iWriting design to disk.; x; \0 `* R1 e- d. I7 E3 C5 T: P
's700c50_SM.dra' saved to disk.- S4 V: I. K3 X2 ]6 @! D- H
Starting new design...
" p5 X2 a0 c# A. ?Creating shape symbol 'D:/Z_PERSONAL_FILE/Cadence_project_file/symbols/QFP50P1290X1290X120-65N/QFP50P1290X1290X120-65N_Allegro/s700c50_pm.ssm'.
$ C* i6 H& B, G4 s, n2 D" LStarting Create symbol...
' y' C+ }7 @# w2 w" mcreate_sym completed successfully, use Viewlog to review the log file.3 D9 H% @/ b: T5 F0 \) L
create_sym completed successfully, use Viewlog to review the log file.% s* S4 ~+ P( r, J  G( K
Symbol 'D:/Z_PERSONAL_FILE/Cadence_project_file/symbols/QFP50P1290X1290X120-65N/QFP50P1290X1290X120-65N_Allegro/s700c50_pm.ssm' created./ s: V  D& B; g- ?
*WARNING* (axlShapeMerge): Invalid database id argument - nil
; o: n: [) R; U% p! J* SPerforming a partial design check before saving.
2 s9 K6 X2 ~$ T  S# N* RWriting design to disk.. Q  ^- ?7 X6 Z% S+ }
's700c50_PM.dra' saved to disk.( N; \# e/ J0 G( M% ~
Starting new design...
# n; V; m# j7 Z3 X+ ~- cCreating shape symbol 'D:/Z_PERSONAL_FILE/Cadence_project_file/symbols/QFP50P1290X1290X120-65N/QFP50P1290X1290X120-65N_Allegro/dummy.ssm'.
2 L8 Q2 b# k: ?1 W* l9 e7 hStarting Create symbol...8 h; R3 c3 ]6 `+ s0 d7 H
create_sym completed successfully, use Viewlog to review the log file.
' t1 `  A. K, @: d, Ucreate_sym completed successfully, use Viewlog to review the log file.
0 o* S2 x  n( G3 {) b% pSymbol 'D:/Z_PERSONAL_FILE/Cadence_project_file/symbols/QFP50P1290X1290X120-65N/QFP50P1290X1290X120-65N_Allegro/dummy.ssm' created.: D8 x$ r' O1 R' x1 k
*WARNING* (axlShapeMerge): Invalid database id argument - nil
3 F2 ^" {- ~7 K3 Y! gPerforming a partial design check before saving.
* H; A, P" c/ G6 q5 ]Writing design to disk.5 ?* H8 B# g6 p: h
'dummy.dra' saved to disk.
8 o8 f7 K: Z; BStarting new design...1 P' j( Q( J6 M
Opening Design "QFP50P1290X1290X120-65N.dra"
; m( H, e# P) r: H$ _(SPMHDB-273): Unable to load shape symbol s700c50_TOP (Check PSMPATH setting for this symbol).3 z5 N+ c1 E$ W- H
*WARNING* (axlDBCreatePadStack): Illegal figure type or shape name "s700c50_TOP"
: I9 ?/ X  M% J; v- w# `Starting new design...6 N1 d$ L. p7 ^
Creating Shapes on Package layers
! W' s1 }  w8 R( {! wCreating Pins
; W5 {, n& W8 A  M$ F  wCreating Vias8 g, ?4 Q3 R  i# @! P# P
Symbol Created7 K. D7 E6 W( R5 W; U
Creating package symbol 'D:/Z_PERSONAL_FILE/Cadence_project_file/symbols/QFP50P1290X1290X120-65N/QFP50P1290X1290X120-65N_Allegro/qfp50p1290x1290x120-65n.psm'.
  ?; i( S& U/ T# fStarting Create symbol...
* \* P* |! D( _! _( N; mcreate_sym completed successfully, use Viewlog to review the log file.
& S8 }8 {/ S" ]* e1 ?" [create_sym completed successfully, use Viewlog to review the log file.# p- {: A+ b0 R! |; G3 e
Symbol 'D:/Z_PERSONAL_FILE/Cadence_project_file/symbols/QFP50P1290X1290X120-65N/QFP50P1290X1290X120-65N_Allegro/qfp50p1290x1290x120-65n.psm' created.+ r2 m. w' A8 ^" Y7 F7 o5 A1 i4 X3 E
Loading cmds.cxt
( A& y0 H, o9 r/ [9 [Loading skillExt.cxt
0 @( N  `# W0 P0 U3 [) m3 m(SPMHA1-161): Cannot open the design because of database problems. Run the dbdoctor command on the design and try to open again.- x/ N0 n) C2 R/ }% U# _% D2 F
Performing a partial design check before saving.0 x' G! e5 ^8 S8 y2 B7 a  r" |2 r+ z( C
Writing design to disk.
  n1 \" ?9 W/ `7 I. X, `/ Y/ m'QFP50P1290X1290X120-65N.dra' saved to disk.  k( D- a  j, I  e  W( q  \
Opening existing design...
! h& V! M; l' u) Z; C. j# TSymbol Saved' t) G6 o5 i  k
t8 {/ W& e6 k$ d2 p9 C! {

$ ^. a) O& f* y* p9 {4 i* h

lb.png (207.07 KB, 下载次数: 6)

Library Builder中的情况

Library Builder中的情况

QQ截图20190929161812.png (48.34 KB, 下载次数: 6)

导出页面

导出页面

malfunction.png (126.02 KB, 下载次数: 6)

dra文件

dra文件

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Regedit

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2#
发表于 2019-9-29 16:44 | 只看该作者
你这个界面是不是在lib工具使用的时候的界面，还是说你这个是做好封装后，然后自己打开的界面，我最近在玩这个，没有出现过这个问题

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sty3362950349
我应该是做好了封装了，用Allegro PCB Designer打开的.dra文件，发现里面没有焊盘和过孔。  详情 回复 发表于 2019-10-4 11:32

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sty3362950349

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3#
 楼主| 发表于 2019-10-4 11:32 | 只看该作者
Regedit 发表于 2019-9-29 16:44( M7 ~4 g8 O* n6 }/ J; H9 Z/ ?' }
你这个界面是不是在lib工具使用的时候的界面，还是说你这个是做好封装后，然后自己打开的界面，我最近在玩 ...
' [2 b" \, ?8 @: Z1 s0 ]; f
我应该是做好了封装了，用Allegro PCB Designer打开的.dra文件，发现里面没有焊盘和过孔。' Q. T2 W- [) T( L+ \

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sty3362950349

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4#
 楼主| 发表于 2019-10-4 16:20 | 只看该作者
解决了。是我的padpath的路径设置的不对，要设置到pad文件所在的目录。在Allegro中修改后重新用Library Builder导出就有了

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