|
|
改进如下：
$ a/ t( `* Z, M" l X# h: i. c
6 K8 K, @$ Z8 S {) ]) [HOTFIX VERSION: 015
0 N6 z# S+ B" D4 ]========================================================================================================) H* E7 ?) J& X5 |
CCRID PRODUCT PRODUCTLEVEL2 TITLE
* U5 u2 g v. S5 o& q% v========================================================================================================9 g, \! f7 ?' i) _" L. F
264893 APD EDIT_SHAPE Shape Edit Boundary toggle invokes S pattern not flip* i/ v9 N$ q9 i; a6 Z
609206 APD OTHER parallel command fails to run on mcm files
- h5 q3 [+ s, f646375 PCB_LIBRARIAN CORE Saving a design or Export Physical takes a long time) Z1 ^9 W- `$ a& P$ T" }, x% M
650721 PSPICE DEHDL Pins shorted due to update in unnamed netnames
4 w7 V5 z8 U I5 h1 A665343 APD EDIT_ETCH Diff pair is routed with gap less then primary gap for a smal
. t5 w) u$ G$ ?: O/ |666736 ALLEGRO_EDITOR ARTWORK There are some shapes not filled when RS274X garber is import3 @' \3 H4 e# Z$ O0 T# l8 x
669411 CONSTRAINT_MGR CONCEPT_HDL DEHDL Constraint Manager crashes when SigXP is opened for a n C i. {+ D% g# r2 ^
669769 PSPICE DEHDL Edit Model on page border causes crash
7 d3 S! B" z, ~671583 ALLEGRO_EDITOR SCHEM_FTB PartLogic does not work with library level ptf files.; \% p0 W. I1 H/ ?2 A
672656 CONCEPT_HDL CORE Using Select cut/paste commands crashes concepthdl
: S7 H4 `/ P% c) V2 l1 s, V# x- t l672806 F2B PACKAGERXL Export physical fails if datasheet hyperlink is defined as ke8 O$ }3 b4 L3 R
672995 CONSTRAINT_MGR CONCEPT_HDL Changing target on net in RPD groups does not clear the pinpa! C% X, u1 N8 L1 T
676268 ALLEGRO_EDITOR EDIT_ETCH MIN/MAX heads up meter not working for some nets, D' y4 u( H6 z' Y1 M
677049 ALLEGRO_EDITOR SHAPE Wrong DRCs created on sliding Nets
0 U1 |4 l2 `+ q677123 ALLEGRO_EDITOR SHAPE Shape does not void cline in slide mode.0 P) n7 X# b4 Y3 ?6 [# Z" o
678030 SPECCTRA LICENSING Cannot start Allegro PCB Router with SIP525 license- u$ y& x2 M0 a* S7 P4 L5 {
678075 CONSTRAINT_MGR ANALYSIS Wrong buffer delays are used in switch/settle times in CM
. l4 s- F R* O* p678794 SCM PACKAGER Unable to package subdesign6 n2 B2 i4 Z1 N# J
678851 SIG_INTEGRITY OTHER Difference in lengths in 16.01 and 16.2
~4 I% n- h0 j; r I678884 ALLEGRO_EDITOR DATABASE dbdoctor fixes corruption and then it's reintroduced, s, Q# G# |/ f5 U) u* u
679224 ALLEGRO_EDITOR DATABASE dbdoctor states it fixes an error but the error returns
2 g/ ?; ?7 l2 V m6 M* y H3 @* Z& h679228 CONSTRAINT_MGR DATABASE Wire Length over Parent Die ADRC is not updated dynamically i- W4 t0 [" e$ C7 K, p
679288 CONSTRAINT_MGR SCHEM_FTB ECSets on some of the nets are missing after importing the lo& c" z1 I( d; o' o9 Z! _6 l
679954 ALLEGRO_EDITOR DATABASE Unable to keep changes to the VIA list in constraint manager.+ w4 |5 u+ J! x) ]
679990 APD VIA_STRUCTURE In Via Structure > Replace after selecting the Old and New st/ e$ U3 q3 r- |6 z
681074 ALLEGRO_EDITOR SHAPE void is not correct with pin having multidri
1 v k1 s8 m) S4 ]' }2 C681140 SIG_INTEGRITY TRANSLATOR Spc2spc crashes on attached testcase4 G4 f v# Q$ o- _! `
681975 APD SKILL axlExtentDB and axlExtentLayout functions will return nil if
5 a# N+ I2 p8 v682587 ALLEGRO_EDITOR OTHER Allegro moves all text when any text on symbol is out of exte; v0 f# a# Y. c; z% B
683479 ALLEGRO_EDITOR DRC_CONSTR Modifying design pad to multiple drill creates unexpacted P-L0 ^# A, V$ C+ p- `+ K
683515 APD DRC_CONSTRAINTS DRC is possibly bogus as it seems to be confusing layers |
|
/1 
发表于 2009-7-27 21:04
收藏
淘帖
支持！
反对！
没有人告诉啊，