Capture-Allegro最好的设计习惯

John-L

0 K, Y* Q& T$ I" N; Z. A
5 T) ~6 J8 ?2 v做到下面的要求,allegro NET-IN就轻松多了:

Best practices for Capture-Allegro
( d! v' ~/ i$ CBest practices for preparing a library for Capture-Allegro PCB Editor
flow
􀂃 Limit part and pin names to 31 characters
􀂃 Use upper case characters for part/symbol names, part references
designators, and pin names
􀂃 Do not use special characters to assign part names, references
designators, and pin names
! o4 H+ E# ]/ u% ~, M􀂃 Do not use duplicate pin names for pins other than power pins
" @1 U! t6 J8 z7 p& G& X  j- J4 @􀂃 For multiple power pins with the same pin names, do not make some
pins visible and other invisible
: W: X1 w$ |0 x" V􀂃 Do not use "0" as a pin number
/ q$ o; R7 j( `1 a2 {* R& [8 \, eBest practices for Capture design for Allegro PCB Editor
- m/ K/ |$ d9 m4 v􀂃 While defining a net list alias or a net name
• Keep the maximum length of a net name or alias up to 31
9 G7 k# Q- o5 Jcharacters
2 i$ q+ S+ ]1 }& j7 W" S• Do not use lower case or special characters in a net name
􀂃 Avoid using "Power Pins Visible" property at design level
􀂃 Use net to connect pins
• Leave room for assigning a net name. Pin-to-pin connection
# I& J! q' y8 r: v' \. O/ ]: f4 xchanges the net name when a user moves a component
* x& Z- a- v& F9 h􀂃 Run the Capture DRC command before generating Allegro PCB Editor
netlist
, S; l4 L7 }8 o4 |9 X4 J􀂃 Set path for Allegro PCB Editor footprint before running Netrev
Best practices for smooth back annotation
1 B" {) a# N- f5 p$ [$ r8 w- k􀂃 Do not change design name, hierarchical block names, or reference
5 y# l+ H3 z+ d# V/ }designators in Capture after board files creation
) n1 L( B* a- ?$ b, H􀂃 Do not edit a part from schematic in Capture after board file
2 h! F, _& c# W1 p% A/ B5 ycreation
􀂃 Do not replace cache as it changes the Source library name and part
name, in capture
" B# v7 v/ U, p( G3 U" d& }6 q􀂃 Do not change the values of component definition properties in
capture after board files creation
􀂃 Do not change Design file/root schematic/hierarchical block names
in Capture after board file creation
􀂃 Do not add or delete components to or from the schematic design
( k+ t+ W" `9 i9 A/ qimmediately after the board file creation. Add or delete components
after finishing the back annotation process
' ?) h$ r' Y* K  L6 G' \* U0 L- 2 -
􀂃 Do not add any additional components in Allegro PCB Editor. Instead,
3 J% \8 a6 i/ n! V2 H! Y% nadd components in Capture and take them to Allegro PCB Editor
􀂃 Do not add, rename, or delete a net in Allegro PCB Editor
# m2 \/ ^3 L  [/ ~$ ~: Q; U􀂃 Do not change the format for reference designators for parts in
Allegro PCB Editor as <Alphabet(s)><Numeric><Alphabet(s)> or
. \, K* V+ Y2 _><Alphabet(s)>-<Alphabet(s)>
&#1048707; Run Allegro PCB Editor Dbdoctor before running Back annotation by
, b: F& C5 P. E4 Tselecting the Database Check command from the Tools menu in Allegro
  V/ g6 b' \: @2 e! wPCB Editor
. l: h+ t  n; |* Q5 @&#1048707; Make backups of the original design before updating the design with
+ m( D- L# \* k. P0 w, k& |+ g- tthe swap information in Capture
&#1048707; Back annotate the design immediately after making the board file.
3 P" e( D  i- z! |  s9 tThough it does not a mandatory step, back annotating the design
before placing components helps avoid problems in back-annotation
& q, V9 H' s0 ]- |at a later stage.
2 t1 y, S4 U& U' l6 d. y; }0 oIf back annotation at this stage generates an empty swap file, you
% q3 Z( D; w" k) B1 u" W2 lcan proceed with placing and routing the board file. In case any
. L8 h) ]+ {8 [problems are detected, you must correct them in the design file and
. u4 n. O, P2 e& M, agenerate the board file again until an empty swap file is generated.

longzhiming99

一直不明白电源脚默认都是隐藏，有什么好处？1048707; Avoid using "Power Pins Visible" property at design level&

Sisic

英文版的  看不懂 請問有中文版的嗎？

jiangliang

做工程需要规范，学习下，谢谢！

John-L

不知道为什麽COPY出来会有"&#1048707"之类的东东

yizhe1015

很好哦

03155001

谢谢分享

yzxujiang

努力争取

happywzb

不错
好东西

dabing715

好东西 大家分享

osinfo

7# dabing715
打开学习一下，谢啦1

hehehe

谢谢分享！

n042208

谢谢楼主

xhymsg

TKS~~~

John-L

自己顶一顶。
$ ?( Q  K1 V6 _看见好多人调网表有问题。
9 j+ z% ~- X, u5 h6 P) M" A养成良好习惯很重要。

杜晓

很好

vincent_xiao

学习了

sls_swz

学习了！顶起来！