再给大家分享一下全志R11芯片处理器相关

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R11代表了Allwinner在智能硬件处理器上的最新成就，它集成了一个以1.2GHz的速度工作的单ARM CortexTM-A7 CPU，并支持多个外围设备。
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* x/ i+ q: J, ?/ v; ACPU


5 c* W: H. }7 s  OARM CortexTM-A7 MP1 Processor
Thumb-2 Technology
5 C7 b6 F; L) x( DSupports NEON Advanced SIMD(Single Instruction Multiple Data) instruction for acceleration of media and signal processing functions
; E8 ^- k* c& dSupports Large Physical Address Extensions(LPAE)
1 n4 ?& S: V/ v7 RVFPv4 Floating Point Unit
# K; D! l7 s, y, O* u( q32KB L1 Instruction cache and 32KB L1 Data cache
128KB L2 cache
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% k+ \3 u4 Q0 a: X3 {/ `& c, KMemory Subsystem
Boot ROM
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Internal on-chip memory
# E; J, q! }, BSupports system boot from the following devices:
- SPI Nor flash
' h6 z$ c3 ^4 A1 \7 M- SPI Nand flash
- SD/TF card
- eMMC
Supports system code download through USB OTG


SDRAM


Internal on-chip memory
Built-in DDR2 in the R11
Clock frequency up to 400MHz
4 F) [! n' O1 Y. u( X1 c, USupports Memory Dynamic Frequency Scale(MDFS)

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8 L4 Z) f9 q  {$ n5 J4 FSD/MMC

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External off-chip memory and storage device
Two SD/MMC controllers
; n( u% u0 R9 }  Q# {3 Z. D6 x2 {( g1/4-bit data bus
Complies with eMMC standard specification V4.41, SD physical layer specification V2.0, SDIO card specification


Supports hardware CRC generation and error detection
  U: \% s9 Q9 W/ |  y+ ?7 IBlock size from 1 to 65535 bytes

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System Peripheral
Timer
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  S# T, C; u4 {) v1 ]' gThree on-chip timers with interrupt-based operation
One watchdog to generate reset signal or interrupt
  j0 P/ c7 s' f4 ?7 V5 k- |33 bits Audio/Video Sync(AVS) Counter
24MHz or internal OSC clock input

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High Speed Timer
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Up to two high speed timers
2 t* ~+ V! d4 V1 XCounters up to 56 bits
Clock source is synchronized with AHB1 clock, much more accurate than other timers

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GIC
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Supports 16 Software Generated Interrupts(SGIs), 16 Private Peripheral Interrupts(PPIs) and 125 Shared Peripheral
Interrupts(SPIs)
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) {2 [6 O4 q9 _DMA

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0 R7 p8 ?, T- _3 a* {9 @Up to 8-channel DMA
) P$ p5 q6 C% x% yFlexible data width of 8/16/32 bits
9 N" U3 J; G9 h; A8 QSupports linear and IO address modes
2 A$ v, m2 p5 u8 G/ ?1 pSupports data transfer types with memory-to-memory, memory-to-peripheral, peripheral-to-memory
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9 PLLs
One on-chip RC oscillator
One 24MHz external oscillator
2 g8 \9 A. L: A8 ]; VOne 32.768kHz external oscillator
" G. ?6 [- c; v/ p1 }! s4 \0 iClock management: clock gating ,clock enabling to the device modules, clock reset, clock generation, clock division

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, A1 F* J9 z: P! o# l; V3 KPWM


Two PWM channels
Supports outputting two kinds of waveform: continuous waveform and pulse waveform
' q8 I1 b4 M" |- _' D0% to 100% adjustable duty cycle
Up to 24MHz output frequency
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RTC

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; q  t& ~# u( {7 T6 LTime,calendar
Counters second,minutes,hours,day,week,month and year with leap year generator
Alarm:general alarm and weekly alarm

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/ a) z7 J; t' O* @4 QLRADC
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( u1 l) p- ^: f6-bit resolution
# z5 |; }. R; B# B' Z* M2 l- JSupports hold key and continuous key
Supports single key, normal key and continuous key


) G, h8 n1 v# k$ |Crypto Engine
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( h# H# `$ g  B# GSupports AES 128/192/256-bit with ECB,CBC,CTS,CTR mode
) u7 _0 M: L4 X. E; ySupports DES/TDES with ECB,CBC,CTR mode
; v  K6 t, M1 V; ISupports SHA1 and MD5
- x# N, H- V7 Y( C# D& F2 l160-bit hardware PRNG with 175-bit seed


* J0 F" m$ s3 ^Display Subsystem
DE2.0
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Output size up to 1024x1024
Supports three alpha blending channel for main display
/ y+ W1 F, y" r- b( q6 vSupports four overlay layers in each channel, and has a independent scale
Supports potter-duff compatible blending operation
Supports input format YUV422/YUV420/YUV411/ARGB8888/XRGB8888/RGB888/ARGB4444/ARGB1555/RGB565

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Display Output

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Supports LVDS inteRFace with single link, up to 1024x768@60fps
Supports RGB interface with DE/SYNC mode, up to 1024x768@60fps
* N  @- N. m3 }Supports serial RGB/dummy RGB/CCIR656 interface, up to 800x480@60fps
% N) H- \1 Y% ^Supports i80 interface with 18/16/9/8 bit, support TE, up to 800x480@60fps
Supports pixel format: RGB888, RGB666 and RGB565
) Z0 }0 ?! I2 d$ n" ?' KDither function from RGB666/RGB565 to RGB888
  Q# p6 s5 Y* r# RGamma correction with R/G/B channel independence

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Video Engine
Video Decoding

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& G% {: I, _- Y+ D% uSupports video decoder for H.264 and JPEG/MJPEG
6 q5 J+ }3 z" C" T9 TSupports H.264 BP/MP/HP up to 1080p@30fps
! L! _2 y) k2 P3 U" i, @$ F) ^Supports H.264 output formats :NV21,NV12,YU12,YV12
Supports JPEG/MJPEG up to 1080p@30fps
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Video Encoding

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9 W* |; V9 c% @2 wSupports H.264 video encoding up to 720p@60fps
7 U6 T4 b5 ~6 e% L$ d8 c7 X% ^3 vJPEG baseline: picture size up to 8192x8192
Supports input picture size up to 4800x4800
  X/ l9 T* _) e& Y5 vSupports input format: YU12/YV12/NV12/NV21/YUYV/YVYU/UYVY/VYUY
Supports Alpha blending
1 c; @, J  M! L0 Q2 xSupports thumb generation
) Q) \5 E& Y4 y* n! d3 \Supports 4x2 scaling ratio: from 1/16 to 64 arbitrary non-integer ratio
Supports rotated input
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  l6 H4 z7 O1 U( I$ tImage Subsystem
Image Input


/ z& j8 `- T  f/ l& DSupports 8/10-bit CMOS sensor parallel interface
Supports 8-bit CCIR656 protocol for NTSC and PAL
  b+ W, z7 U/ ~1 L& c3 t% m: ]Supports ITU-R BT 1120 protocol for HD-CIF system
Supports 16-bit interface with separate syncs
- _& l1 f: k- b1 ZMIPI-CSI2 interface compliant with MIPI-DPHY v1.0 and MIPI-CSI2 v1.0
8 c6 u5 i" z5 L7 U8 u& USupports MIPI-CSI2 1/2 data lanes configuration
( U! b5 x! z% B. `5 ?Supports Format:


- YUV422-8/10 bits
& |2 V# |: t4 S6 q* f- YUV420-8/10 bits(for MIPI-CSI2 only)
# n9 v' ^( \2 v) P' |0 x- RAW-8/10 bits
4 k6 d5 H- v, H2 m- RGB888/RGB565(for MIPI-CSI2 only)
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  X5 Q$ x" Q/ i5 L& RPerformance:
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( B. C6 R5 N9 ?. r; s- ^% W- Still capture resolution up to 5M with parallel interface
+ B- M5 _& t) V& B5 G5 S- Video capture resolution up to 1080p@30fps with parallel interface
- Still capture resolution up to 5M with MIPI-CSI2 interface
4 _1 `' M. X: @5 n/ v; H5 j- Video capture resolution up to 1080p@30fps with MIPI-CSI2 interface
8 ?, T- k# l" a7 h' z- MIPI-DPHY maximum data rate up to 1Gbps per lane
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ISP
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1 W  g; _0 [8 z$ G& y1 N) B4 |9 vSupports input formats:8/10-bit RAW RGB,8-bit YCbCr
! ]0 M+ w( T2 ySupports output formats: YCbCr420 semi-planar,YCrCb420 semi-planar, YCbCr422 semi-planar,YCrCb422 semi-planar,YUV420 planar,YUV422 planar
Supports image mirror flip and rotation
- j# Q2 f5 r1 |* w! H  @: gSupports two output channels
Speed up to 8MPixels@24fps
' ^3 @8 {( j5 uDefect pixel correction
4 w9 k" v* Y/ F% g9 K- }Super lens shading correction
5 J0 E% N" ~- ?% R6 GAnisotropic non-linear Bayer interpolation with false color suppression
Programmable color correction
1 s; [1 b# U: K, cAdvanced contrast enhance and sharping
7 _* G7 m1 |0 |Advanced saturation adjust
6 l+ I" C" K( _( I; m- SAdvanced spatial(2D) de-noise filter
, P5 v2 }9 _& @  bAdvanced chrominance noise reduction
. C9 |; ~7 ]8 u' M6 ]Zone-based AE/AF/AWB statistics
Anti-flick detection statistics
/ {6 X4 ^6 w5 g. C1 ?* I9 w, s* PHistogram statistics


, _6 ]; Q- M9 mAudio Subsystem
+ A) z( I/ P6 g% g9 I: i6 ]Audio Codec


Two audio digital-to-analog(DAC) channels
/ Z/ `1 h9 g# _  @. VSupports analog/digital volume control
$ w) R, g, P; z/ y9 \. X0 bOne low-noise analog microphone bias output
6 ~( |$ L/ @# }; o0 T* L2 w' |6 H7 WAnalog low-power loop from microphone to headphone outputs
/ N2 c  N2 @' J' s. j% }5 VSupports Dynamic Range Controller adjusting the DAC playback output
; H! Z6 U1 n) ?2 A( K; _0 Z$ tOne Microphone input
One Stereo Lineout output
( n8 P1 L& l' h" [# JTwo audio analog-to-digital(ADC) channels

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& K3 k% P% ]) Y% M0 \5 K- 92dB SNR@A-weight
- Supports ADC Sample Rates from 8kHz to 48kHz
2 P# u9 I4 p: N# ^Supports Automatic Gain Control(AGC) and Dynamic Range Control(DRC) adjusting the ADC recording input
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! K% P0 r" q) pExternal Peripherals
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. i6 Z. o0 I9 R USB

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One USB 2.0 OTG controller with integrated PHY
Complies with USB2.0 Specification
3 K9 X3 t' N% U' P7 [2 ^, e1 MSupports High-Speed(HS,480 Mbit/s),Full-Speed(FS,12 Mbit/s),and Low-Speed(LS,1.5 Mbit/s) in host mode
$ e( x' c2 P( C8 h  L8 CComplies with Enhanced Host Controller Interface (EHCI) Specification, Version 1.0,and the Open Host Controller
, ?' l8 C8 \/ K( V5 e" R+ n5 WInterface(OHCI) Specification,Version 1.0a for host mode
$ p. @4 n8 m  PUp to 8 User-Configurable Endpoints in device mode
Supports point-to-point and point-to-multipoint transfer in both host and peripheral mode


I2S/PCM
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0 K* r9 X3 X3 I# z; gCompliant with standard Inter-IC sound(I2S) bus specification
. ?2 j6 T! {$ |& m3 S  |Compliant with left-justified, right-justified, PCM mode, and TDM(Time Division Multiplexing) format
Full-duplex synchronous work mode
Master and slave mode configured
' T5 k; Z5 z. q  RAdjustable audio sample resolution from 8-bit to 32-bit
Sample rate from 8 kHz to 192 kHz
% _; y; ^) I" O2 k: ESupports 8-bit u-law and 8-bit A-law companded sample


EMAC
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Supports 10/100/1000 Mbit/s data transfer rate
9 D) A( g% G8 b* r8 D# `- z2 k  t- M0 zSupports RGMII/MII/RMII interface
Full-duplex and half-duplex operation
Linked-list descriptor list structure
Programmable frame length to support Standard or Jumbo Ethernet frames with sizes up to 16 KB
Supports a variety of flexible address filtering modes
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UART
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2 R4 G' L! i/ K# h7 |% n5 j# KUp to three UART controllers
64-Bytes Transmit and receive data FIFOs for all UART
6 C1 I* O' i# G  h$ A7 k) RCompliant with industry-standard 16550 UARTs


不直接翻译了，且资料内容太多了，想要看完整的，可参考全志R11 datasheet

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ExxNEN

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