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DAEMON cdslmd c:\cdslmd.exe: _& N; ], _# r" U- Y+ C7 A6 P. ~
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% u# \" G) u5 I4 X# Generated especially for0 x5 w( b8 i6 D' g) O0 R$ B( s& V
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& @* P% L' a1 u: j# Mendling with Feature lines will only invalidate them!: R+ @: E8 d3 h/ ^9 C
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1 b6 X- C! F g; ~! G. k( S- YPACKAGE EFA-CDS-01 cdslmd 2019.12 50D0C0F14EEEF46F0FE0 \0 `/ O4 q6 O' r: ]1 f6 t: _
COMPONENTS="A2dxf ABIT actomd adv_package_designer_expert \5 X" C, U2 T# b1 d; y) Y% m7 S( k
adv_package_engineer_expert ADV_USUPUC_ALL \# L* @8 K5 D$ A# M' Q
Advanced_Package_Designer Affirma_NC_Simulator \0 f. h" @3 T4 f* m" Q- x
Affirma_sim_analysis_env Affirma_transaction_analysis \
0 M+ h( P! w# S0 ^0 ~4 I% Z& c0 f1 S0 J Affirma_verification_cpit_rtim Allegro_CAD_Interface \
' { m$ B% u) E( T Allegro_design_expert Allegro_Designer Allegro_designer_suite \% l0 U8 A ]0 N) m1 h
allegro_dfa allegro_dfa_att Allegro_Expert Allegro_Librarian \2 U" n2 u% t/ g9 e
allegro_non_partner Allegro_PCB Allegro_PCB_Interface \
1 [9 H8 b/ d% {! O5 U Allegro_performance Allegro_studio Allegro_Symbol \) a" ~) |& \% q1 T9 x8 g
Allegro_Viewer_Plus allegroprance ANALOG_WORKBENCH APD \# u0 y; B) e9 \% v$ r* y
archiver arouter AWB_Batch AWB_BEHAVIOR AWB_DIST_SIM \
4 J- b) c3 n) P AWB_MAGAZINE AWB_MAGNETICS AWB_MIX AWB_PPLOT AWB_RESOLV_OPT \ k! M0 y( Y; K( o8 C0 ?8 ~
AWB_RESOLVE_OPT"
; e# I# H: b! b4 m& t, ?PACKAGE EFA-CDS-02 cdslmd 2019.12 006030C10306920F9721 \' s$ U' ~6 a$ h+ b1 `5 A& ]5 V3 |; c7 f
COMPONENTS="AWB_SIMULATOR AWB_SMOKE AWB_SPICEPLUS AWB_STATS \ |+ b7 e+ |! F+ d- ^* T
AWBAA AWBSimulator Base_Digital_Body_Lib Base_Verilog_Lib \
, \5 o- r9 K4 J& m$ ~# B- N BOARDQUEST BoardQuest_Designer BoardQuest_Team BOGUS \
. u7 x9 x8 b9 A Cadence_chip_assembly_rtr_ALL Cadence_chip_assembly_rtrEngr \. d1 c: Z6 q8 a
caeviews cals_out Capture Capture_CIS_Studio CaptureCIS \* P9 F+ g, t3 z4 [' y
cbds_in cdxe_in CHDL_DesignAccess CheckADV_ALL CheckFST_ALL \
+ q8 f' [: w4 x Checkplus_Expert CISoption comp Concept_HDL_expert \6 C+ l+ u. |) X$ p# T, G1 F1 l- @
Concept_HDL_rules_checker Concept_HDL_studio ConceptHDL \
0 N& o& ~. j2 p- {8 t CP_Ele_Checks cpe crefer cvtomd CWAVES debug DFM_USUPUC_ALL \ [, z p( @/ {1 s
DISCRETE_LIB dracula_in"( P$ q# K! g* J/ Y# a
PACKAGE EFA-CDS-03 cdslmd 2019.12 40A0708139C03D1415F7 \7 _3 \ ]/ w' Q
COMPONENTS="dxf2a EB_4SUPUC_ALL EB_USUPUC_ALL eCapture \7 Q+ c. d" O j6 C7 z E6 p/ B
EDIF_Netlist_Interface EDIF_Schematic_Interface EditBase_ALL \
e) |8 ?& `9 j$ b4 Q' ] EditFST_ALL EditPlace_ALL EditRoute_ALL EMCdisplay EMControl \
/ I% ~6 }/ B m" f9 f5 E1 X4 O EMControl_Float EMI_ALL expert expgen explorer Express \
" v3 K( q3 {- h/ K ExpressPlus Extended_Digital_Body_Lib Extended_Verilog_Lib \
* C( |7 U& k% h; ?( o: U# z' r fethman fetsetup FloatPC_ALL floorplan Framework \
* `3 C4 P! L" V: \; _: h' ? fst_Usupuc_all FUNCTION_LIB gbom glib gloss gphysdly gscald \# z! z4 w0 K; A( `0 ~
gspares HDL-DESKTOP hp3070 HYB_USUPUC_ALL IC_autoroute_ALL \% E3 B& t7 ]* m& ~4 r% J5 F8 I
IC_device_place_ALL IC_devicegen_ALL"
A% P! [, i# v* [9 G$ J: TPACKAGE EFA-CDS-04 cdslmd 2019.12 30801091DAE1B711FC58 \$ G) |' U4 [# \) M( ^; a
COMPONENTS="IC_deviceplace_ALL IC_edit_ALL IC_editfast_ALL \
) ]1 Q3 I+ x/ \2 O, e, `7 M& C IC_gcell_route_ALL IC_hsrules_ALL IC_Inspector_ALL \
+ f# S! V k# `( Y IC_InspectorEngr IC_InspectorEngr_ALL IC_mp_route_ALL \
6 {, J+ L, m* O8 V4 a IC_power_route_ALL IDF_Bi_Directional_Interface \
8 v5 p D4 e, h: R# Z) H+ E iges_electrical intrgloss Intrica_powerplane_builder intrroute \
7 M- f& Q$ h. V2 C2 \+ R7 m. k/ Q intrsignoise IPB_4SUPUC_ALL IPB_USUPUC_ALL ipc_in ipc_out \0 }* y- u9 E! O( g; P9 x
IPlaceBase_ALL Layout LayoutEE LayoutEngEd LayoutPlus \4 A' g' _" O9 I+ C+ {- V2 [
LEAPFROG-BV LEAPFROG-CV LEAPFROG-SLAVE LEAPFROG-SV \
1 n$ n4 x4 e9 B: z$ q) d LEAPFROG-SYS LID11 LINEAR_LIB LSE lwb MAG_LIB MASTERTAG mdin \2 _3 ~2 S! f7 J5 `! s
mdout mdtoac mdtocv"
: s! ]- {. w, vPACKAGE EFA-CDS-05 cdslmd 2019.12 709080B1B225997E86A8 \
7 k$ [& F- e& ~6 r. Q COMPONENTS="MIXAD_LIB modelIntegrity multiwire \
$ B: C& z2 @- l5 G( c( \: n NC_VHDL_Simulator NC_SystemC_Simulator Nihongoconcept \
/ ], Z$ [& M. a OpenModeler OpenModeler_SFI OpenModeler_SWIFT OpenSim \
6 `6 ] g( w* { ?8 M OpenWaves Optimizer OptimizerAA OrCAD OrCAD_Capture_CIS_option \) G* l B C6 {/ |& U7 M F
5 M/ P: |6 d7 b, T$ Y4 q; I- c PB_USUPUC_ALL PCB_design_expert PCB_design_studio PCB_designer \
9 r3 X4 r/ J: n$ I }, _$ X6 t+ T pcb_editor pcb_interactive PCB_librarian_expert pcb_prep \$ O1 c: j1 K% Y
PCB_studio_variants pcomp PE_Librarian PlaceBase_ALL placement \: M3 \% R3 b T" U& @
PlaceOrIPlace_ALL plotVersa PO1100 PO1110 PO1300 PO1310 PO1320 \6 _/ B8 e! w6 Z0 I. T! [
PO1330"- |: `- g: V" S! H. @
PACKAGE EFA-CDS-06 cdslmd 2019.12 4030F0D1DDB23CB51B53 \3 a, s4 R [6 p B( r5 z" i
COMPONENTS="PO1340 PO1400 PO1410 PO1420 PowerIntegrity \0 n; M/ g' R1 H* Y$ E
PPRoute_ALL Prevail_Board_Designer Prevail_Designer PS2010 \, A2 @6 g, ]. L& F
PS2200 PS3010 PSpice PSpiceAA PSpiceAAOptimizer PSpiceAAStudio \4 x2 v3 O0 f M# W
PSpiceAD PSpiceADAA PSpiceADStudio PSpiceBasics PSpiceStudio \4 T2 |5 H) C0 a @: {8 p
ptc_in ptc_out PWM_LIB PX3500 PX3710 PX3910 quanticout \: q% z, N7 {( d7 R. [9 |) D
RapidPART rapidsim RB_4SUPUC_ALL RB_6SUPUC RB_6SUPUC_ALL \8 R9 u9 a1 M, p6 O K& b; j4 w( s
RB_USUPUC RB_USUPUC_ALL realchiplm RouteADV RouteADV_ALL \
4 W3 {" \3 @, Y6 S$ @( n" S RouteBase RouteBase_ALL RouteDF"( @0 ~* f3 u% d
PACKAGE EFA-CDS-07 cdslmd 2019.12 40F0106176E4BBB2D3D1 \
) n3 K0 f3 p7 q( n [- z# }4 b5 W COMPONENTS="RouteDFM_ALL RouteFST RouteFST_ALL RouteHYB_ALL \$ a# |, t5 O |6 l
RouteMin_ALL RouteMVIA_ALL RouteOrEdit_ALL rt sdrc_in sdrc_out \* \3 {$ i4 O7 c
shapefill signal_explorer signoise SigNoise_Float SigNoiseCS \
% ~3 i$ I7 j5 x# V SigNoiseEngineer SigNoiseStdDigLib Sigxp sigxp_explorer \
2 i8 t! k& [4 D9 f8 ] ^) v Sigxp_tier Sigxp_tier_EXPERT SimVision skillDev SPECCTRA_256U \# p; B8 _* A: A2 Y
SPECCTRA_6U SPECCTRA_ADV SPECCTRA_APD SPECCTRA_autoroute \
N7 d0 o3 [" P SPECCTRA_autoroute_ALL SPECCTRA_autorouteEngr \' s- y* m) f: p
SPECCTRA_designer SPECCTRA_designer_ALL SPECCTRA_designerEngr \
+ y0 m( C; v9 P6 u+ H, o' x+ H SPECCTRA_DFM SPECCTRA_expert SPECCTRA_expert_ALL \
' L& h2 `+ T1 y' z5 M7 X SPECCTRA_expert_system SPECCTRA_expert_system_ALL \2 o' _$ J3 H4 A; ]* r; x
SPECCTRA_expert_systemEngr SPECCTRA_expertEngr"
M6 `9 S- X( _( ?0 \9 n2 QPACKAGE EFA-CDS-08 cdslmd 2019.12 4010E001C03C574EA29E \7 e8 z1 E5 @3 i* M7 u
COMPONENTS="SPECCTRA_HP SPECCTRA_PCB SPECCTRA_PCB_ALL \
) W% m: o8 a# L/ P/ A7 ?* a7 J/ m SPECCTRA_PCBEngr SPECCTRA_performance SPECCTRA_performance_ALL \
/ }5 ~: F- |1 I$ x1 W3 O SPECCTRA_QE SPECCTRA_VT SPECCTRAQuest SPECCTRAQuest_expert \
) o3 O3 `+ o/ Z' w7 H SPECCTRAQuest_Planner SPECCTRAQuest_SI_expert \
, |4 \, I+ c: z, m2 t- ` SPECCTRAQuest_signal_expert SPECCTRAQuest_signal_explorer \3 Y+ \' c9 V3 t' o
SQ_Digital_Logic_SI_Lib SQ_FPGA_SI_Lib SQ_Memory_SI_Lib \
2 i6 ?, [/ V: G) M; T SQ_Microprocessor_SI_Lib stream_in stream_out StudioPSpiceAD \7 Y+ Z* B8 r0 T
swap SWIFT sx Synlink_Interface Team_EFA tscr tune tw01 tw02 \- x7 d8 s# E) \1 w# }1 r
UET ULMdelta ULMecho ULMhotel ULMindia ULMjuliette ULMmike \
+ n* W8 |1 _ }3 G9 Q/ y/ g5 l$ Y Unison_SPECCTRA_4U VB_4SUPUC_ALL VB_6SUPUC"
/ v& y0 I* x, q; O2 ePACKAGE EFA-CDS-09 cdslmd 2019.12 B0800091DEDE2463C4D0 \
5 I" \% {; h4 ]: O COMPONENTS="VB_6SUPUC_ALL VB_USUPUC VB_USUPUC_ALL \( B: Y4 f- i! O/ _
VERILOG-SLAVE VERILOG-XL vgen VHDLLink viable ViewBase \
! o: T, J! `2 P' y$ z& [1 b) I ViewBase_ALL ViewBaseEngr ViewBaseEngr_ALL \
( ?/ n7 ^% B5 G, E0 o. I" W% e7 u Virtuoso_custom_router_ALL Virtuoso_custom_routerEngr \: X* u/ S' N6 o2 `1 y0 v; N$ m5 M
visula_in vloglink VXL-LMC-HW-IF VXL-TURBO VXL-VCW VXL-VET \. t7 P3 c4 G( a. P# S( u* e, w7 f" l
VXL-VLS VXL-VRA WinActel WinAltera WinAMDMACH WinAtmel \
( g+ D9 h' f6 W4 g WinAutoRouteU WinCapture WinCaptureCIS WinDesignLab WinDevEqu \
6 t( c/ J" Y) I9 f" F WinEditRouteU WinExpress WinExpressPlus WinLayout WinLayoutEE \3 m# y( o. |) M1 }: i/ x6 O
WinLayoutPlus WinMACHfiveVP WinMicroSim WinMinc"
% S3 V1 e6 X9 V: S9 L: iPACKAGE EFA-CDS-10 cdslmd 2019.12 D0303001C3A577CFA14E \
9 l3 X) F6 r- J& G! N COMPONENTS="WinOptimizer WinOrCAD WinParts WinPCBoards WinPLD \* f4 N/ y" a) j
WinPLSyn WinPLSynPart WinProbe WinPSpice WinPSpiceAD WinStmEd \
7 {# t# S! a+ C9 U9 ~ WinXilinx"8 f& V4 a$ c, ]8 f& H8 ^: ]+ G% x
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INCREMENT EFA-CDS-04 cdslmd 2019.12 23-dec-2019 uncounted BDB107572A17EEA52094 "" ANY
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INCREMENT EFA-CDS-06 cdslmd 2019.12 23-dec-2019 uncounted BDD107572017EEA5229E "" ANY: \4 O! O4 [, U) g( @; |4 ]
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INCREMENT EFA-CDS-10 cdslmd 2019.12 23-dec-2019 uncounted AD810787261AEEA50D98 "" ANY% p& U3 C, R1 z" d. a# B6 H9 P
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