讨论下CPCI问题

yuzengshu

9 b/ v* R# m1 ^& {4 S2 [% {
1 P0 H/ q3 v  [1 v" w: aCPCI 分为系统板，背板，外围板，对于外围板有死规范，但是对于，系统板，和背板的规范
8 ~1 E1 a. v) a# z/ {6 Y，见的不多，就是对于系统板，时钟线和数据线的长度有没有限定，还有背板，时钟和数据长度的限定怎么
计算，希望做过的朋友，给点经验，我的是PCI TO PCI桥出来，在到CPCI接口的，谢谢
( j6 Y& D+ I, I% w; s大家看看这段怎么理解
1 The System Slot clock distribution circuitry shall be designed to accommodate
up to 200 ps of backplane and peripheral board skew. The following design rules
( s, x: j) Q) V2 q% Dapply to clock distribution to backplane peripherals and local (onboard) PCI
peripherals
2 Any onboard PCI peripherals connected to the CompactPCI bus, including
PCI to PCI bridges, shall be provided a clock that is delayed to
accommodate the maximum propagation delay of the backplane clocks and
+ T+ z  G$ p8 T$ }- u& g9 ystill meet the 1 ns overall skew requirement. Up to 800 ps of skew is
5 M$ n, m( Z6 o3 |allowed for onboard clock distribution (including the clock buffer internal
9 T' ^8 @7 `/ n! P$ t9 j! }skew). The onboard clock signals shall be delayed beyond the clocks routed
to the backplane (Section 3.5.5.1) to accommodate best and worst case
backplane delays and the 63.5mm wire delay on the peripheral board.