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*pads-ECO-V9.1-METRIC*
6 K- |, J4 V- b7 l: d# x: x*REMARK* old file: d:\PADS Projects\padsnet.asc' E }$ r" J% A; z- M
*REMARK* new file: d:\PADS Projects\ppcbnet.asc9 s' a( U8 J4 G2 r1 r
*REMARK* created by ECOGEN (Version 6.4v) on 2010-2-11 18:08:34
4 J) A( q! W6 @PART DIFFERENCES. ^# j0 t t* V- R0 a8 ]# d
----------------
1 L0 A3 s. m( Z/ q3 PSchematic PCB
" L4 ~: q+ \+ f7 {) \Ref-des Part-type ecal Ref-des Part-type ecal
+ i4 R; `" p9 x$ Z0 j/ QNET DIFFERENCES
. _2 X* U8 w* K2 [& U$ X/ }----------------/ d0 ]4 T, S- q4 q t. o
Schematic PCB# Z7 _6 H" C6 U5 G1 P* ]* |; Z
SWAPPED GATE DIFFERENCES6 i* N7 p8 Z# E1 k
------------------------3 C1 G' M/ D3 M3 i# u. M1 c* _
Schematic PCB
( o( s% H) U2 h" v, f7 r- F/ FSWAPPED PIN DIFFERENCES
/ [5 D' _8 B) m! T+ h0 R# }# X5 s+ o------------------------
! i: u/ _' r. |% D/ k7 p9 G9 wSchematic PCB9 N: ~6 T/ h- Y" K* J
( s4 u# a: P9 u
UNMATCHED NET PINS IN Schematic! `9 G' K9 }; z( R
-------------------------------( |" c" F2 j" a N
UNMATCHED NET PINS IN PCB
! F+ L, \2 j) \8 W4 z+ ]& e-------------------------9 g8 ]# u" A1 d
ATTRIBUTE DIFFERENCES" |3 W, K7 o. g1 H' c6 t3 o2 j
---------------------! G* ?( Q# j$ \4 f& k& q5 [
Attribute Level [ Schematic Parent -> PCB Parent ]; f, A; [& \/ M
Attribute Name Schematic Value PCB Value. Y! T# ?: p; B/ }8 x) @* g* {
RULES DIFFERENCES (Values in mm)5 V3 I& Z0 ]! S/ q, b1 B1 s" a
-----------------
/ X4 K! c. p& FObject Type Object Name [ Schematic -> PCB ] Rule Type7 d. X9 w J/ z# b) K$ s
Rule Name Schematic Value PCB Value
' y# d8 Y$ y7 ]# k- FNET BATT CLEARANCE
8 d0 Y& A) Y4 t( q% H9 V TRACK_TO_TRACK <no rule> 0.1524003 K1 Z3 T7 Q1 @( K4 n
VIA_TO_TRACK <no rule> 0.152400
$ c* G2 @6 v& x; S) i: g; C VIA_TO_VIA <no rule> 0.152400
4 ~- }* ?+ S6 c/ z PAD_TO_TRACK <no rule> 0.152400
* v1 B! z: O! s$ w4 M7 D PAD_TO_VIA <no rule> 0.152400" O; l" g. w5 W4 l
PAD_TO_PAD <no rule> 0.152400
+ c0 c2 ~. ]! O; l+ Y; Q3 d2 C9 ? SMD_TO_TRACK <no rule> 0.152400
4 N: E; _1 t* l! p ?8 x SMD_TO_VIA <no rule> 0.152400* A) l/ f' R/ _, }7 ~* X6 |
SMD_TO_PAD <no rule> 0.152400
+ n% {6 C6 e0 y/ M5 e V7 K SMD_TO_SMD <no rule> 0.152400
) r1 D' ?- P+ e6 X" U) D, s1 K COPPER_TO_TRACK <no rule> 0.2540006 A, N n; ]* p+ c3 i( n; h+ y
COPPER_TO_VIA <no rule> 0.254000
- j2 O g) e0 ~4 l$ D: I5 X6 Q COPPER_TO_PAD <no rule> 0.254000
" ]0 Y' [+ ]9 t. N4 X COPPER_TO_SMD <no rule> 0.254000+ Q# H, V( F3 d
COPPER_TO_COPPER <no rule> 0.254000
1 {% H v, Z% G TEXT_TO_TRACK <no rule> 0.152400: t( L& |) D( \+ |
TEXT_TO_VIA <no rule> 0.152400
4 x( t0 {, {9 ]* U( t, Z1 a TEXT_TO_PAD <no rule> 0.152400: i: O# o' |0 W3 z ?# }8 c
TEXT_TO_SMD <no rule> 0.152400( ^5 B& N2 w, A, y6 ]- b- _
OUTLINE_TO_TRACK <no rule> 0.254000
. c, M$ _$ I5 }- k6 I OUTLINE_TO_VIA <no rule> 0.254000 |
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