|
EDA365欢迎您登录!
您需要 登录 才可以下载或查看,没有帐号?注册
x
LIBRARY IEEE;
7 M1 q* D$ Z/ d6 W0 VUSE IEEE.STD_LOGIC_1164.ALL;
, N% ?1 Y! V7 G/ Z: v' JENTITY tri_s IS
, d4 X; l. _; t9 G PORT( enable : IN STD_LOGIC;
0 A @' J! W0 O2 c; v1 |. x; d datain : IN STD_LOGIC_VECTOR(7 DOWNTO 0);* j M' e2 N [% ~
dataout: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
5 u0 D/ o6 {# k c ^ @+ w0 C; L UEND tri_s;! M/ c( H! @ `; S, u3 p
ARCHITECTURE bhv OF tri_s IS
; J2 z' e0 j& u' c* L% ~. BBEGIN
# r+ e/ p1 D/ B: E) H pPROCESS(enable,datain); y/ |4 f" f5 a9 g4 ?+ G) I
BEGIN - H5 a0 I- e$ {: h8 e" D
IF enable ='1' THEN dataout <= datain;
- S/ m5 u! a; q% \3 o else dataout <= "ZZZZZZZ"; END IF;3 ^4 [4 X/ `0 f1 A2 D4 h
END PROCESS;
! ~9 }. h+ R: G, Z0 O9 d1 F6 ` ~+ AEND bhv;. r# {0 m" j' ~- G- _; k" V( Y
! S5 ]" s6 W5 T4 x3 N7 Q/ S编译提示:
5 H) K {3 v. WError: Top-level design entity "div" is undefined! j0 D: w; Z( m1 U$ I! Z; I
3 n2 ?' L# C& n是什么原因,求救!!!!!! |
|