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DATE: 04-23-2010 HOTFIX VERSION: 007
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0 U; D3 Q1 c3 a$ r; H+ K2 s# ?6 k- }CCRID PRODUCT PRODUCTLEVEL2 TITLE
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721859 ALLEGRO_EDITOR OTHER update shape to smooth creates tmp file on remote file server working dir why?
7 U. L q3 u2 w$ }740201 SPECCTRA_MENT_ IMPORT Wrong stackup order after translating from mbs2sp
1 X/ K# _5 @5 |. t2 s- j* n/ a744797 SIP_LAYOUT OTHER Cannot Copy a connector (IO) symbol in APD and SiP tools v) d# S. f8 a0 S- h
747831 CIS CONFIGURATION There is a delay of 5 to 10 mins in opening SQL database in V16.2 and V16.3. It is fine in V16.0.
. G, y3 w/ x. z: g. d* S747848 CIS CONFIGURATION Unable to configure CIS with Oracle database due to Capture crash.; n3 v4 \7 f3 S1 m1 m
751372 CAPTURE OTHER Copy / Paste Issue in capture 16.3
, z5 ^2 e+ w& A n8 m o9 L757434 ALLEGRO_EDITOR MODULES Allegro hangs the board file after creating Placement Replicate circuit.
k% a2 w# ~ T& }% D759906 CIS PART_MANAGER Property copy from one to several parts doesn't work
; p0 {4 x+ i! I9 D9 z, ~. E( C, {760154 PSPICE NETLISTER Model parameter (Tj) is not affecting Smoke Analysis result
; W* r0 d0 b$ f/ O6 }4 n761177 CIS OTHER Error Message - Memory exhausted9 Y! t! @+ w" P2 ~
762602 CIS EXPLORE_DATABASE CIS doesn't open datasheet for parts if it is not stored at default Capture location.3 E' R' f/ h6 \1 P j
763677 APD EDIT_ETCH The "Via to Via Line Fattening" tool is inconsistent in which clines are changed.- l& }" z9 G+ Y7 ?/ W! F
763715 CAPTURE NETLIST_OTHER A long pin name gets truncated upto 31 characters when the wirelist is created." e, o ~/ E, o( m e: C1 R. `
763878 CONSTRAINT_MGR DATABASE Why Pinpairs disappear after closing Constraint Manager?7 h3 z3 q) c* t' l- m
764020 CAPTURE NETLISTS Usernetl.dll has changed between 16.2 and 16.3. O0 U# _$ p1 L2 c1 R8 C0 T# U( D
764101 APD EDIT_ETCH Perpendicular routing through a Region does not work when the region segment is drawn at an angle.
8 }# b* t7 N% l- r5 s: \764200 ALLEGRO_EDITOR DRC_CONSTR Via at smd fit drc on a via that is placed fully inside the padstack having custom pad( R6 i1 }) P7 k, c
764903 PSPICE ENVIRONMENT 'Run in Resume Mode' does not work in SPB 16.3
0 O* b0 q% a% Z7 w1 q8 F765206 F2B PACKAGERXL Unable to feedback subsequent pin swaps from Allegro
0 i# c! u9 T9 [5 d765319 APD DRC_CONSTRAINTS Identical Constraints in Performance Advisor question/ s0 H$ g, C f/ p' k8 _
765541 SIP_LAYOUT SHAPE Set via oversize value to 3 in dynamic shape instance parameters will make overlap shape.% [# \. g) B( a" _' P
766147 APD EDIT_ETCH Resize/Respace Diff Pairs does not work on 45 and off angle; t3 {- o8 d1 _6 h
766337 SIG_INTEGRITY GEOMETRY_EXTRACT Geometry of Via model Extracted from board file is not identical to Original Via geometry design5 w j; t. S+ P0 O! {* _
766443 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd in 16.3
* Z+ J- m# w; {, x* {" r+ C) e766581 CIS CONFIGURATION In 16.3 capture.exe remains memory-resident after exit
& f1 N- Q# J+ Z# h2 x# p2 G6 W' b/ x767161 ALLEGRO_EDITOR SHAPE The behavior of Add Fillet command is different by Hotfix version.+ Y F0 b6 q% t
767217 SIP_LAYOUT IMPORT_DATA The Die-Text In wizard and it is crashing on the "Finish" step.
7 m$ x% e& y% R3 \# O767598 SIP_LAYOUT WIREBOND Can't wirebond SIP designs as it just hangs.
( t8 ]. K% K6 `, N/ p2 s767832 ALLEGRO_EDITOR DRC_CONSTR Reducing Design Accuracy updates Physical Diffpair constraints wrongly
( Q, s1 v8 R" u8 r/ v7 j, c768822 ALLEGRO_EDITOR SKILL axlSetParam return value is divided by 10 to the power of the design accuracy./ I* c i5 I9 {% f1 r
769150 CIS PART_MANAGER Update All part Status on a group changes 揇o Not Stuff?status to 揝tuffed?in V61.3_ISR_5.5 [ \# l/ a1 y
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发表于 2010-4-20 19:50
