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本来一直好好的,元器件都布局好了。然后去orcad里更改了一下原理图里几个电容的封装,再更新到PCB就出错了。有人有解决办法吗?不然白忙活了。* s4 Y+ R A) I4 p
( g2 A* F' E! nallegro里的出错报告如下:- u4 ]) X7 L4 s
cadence Design Systems, Inc. netrev 15.7 Wed May 12 21:32:04 2010
) w$ J9 R- z# n8 @" h5 E(C) Copyright 2002 Cadence Design Systems, Inc.
& B$ W2 Y/ d) ]' i" i8 x5 p: u0 f------ Directives ------
. D9 F3 H" {9 w9 ~) z2 \& LRIPUP_ETCH TRUE;6 V$ j2 o) p i: o% ^0 G
RIPUP_SYMBOLS ALWAYS;8 j) W0 L. B' a8 g+ R
MISSING SYMBOL AS ERROR FALSE;
6 a8 g" m) k+ q% G7 ^/ ?/ XSCHEMATIC_DIRECTORY 'D:/CadenceWork/HongelDM642/PCB/allegro';
1 r: O. W/ V) Q+ I) y# L! BBOARD_DIRECTORY '';
" h8 l+ Q. B: V6 }OLD_BOARD_NAME 'D:/CadenceWork/HongelDM642/PCB/DM642_Core_Board.brd';
) q1 p6 ]1 x9 tNEW_BOARD_NAME 'D:/CadenceWork/HongelDM642/PCB/DM642_Core_Board.brd'; M) l4 W8 A4 t; E# O
CmdLine: netrev -$ -5 -i D:/CadenceWork/HongelDM642/PCB/allegro -x -y 1 -z D:/CadenceWork/HongelDM642/PCB/#Taaaaaa00436.tmp
6 \1 Q& X ]+ a0 `8 ], C/ x% {- }------ Preparing to read pst files ------
i# f4 a \' e8 HStarting to read D:/CadenceWork/HongelDM642/PCB/allegro/pstchip.dat
4 [& S8 Y8 m5 _! [9 | Finished reading D:/CadenceWork/HongelDM642/PCB/allegro/pstchip.dat (00:00:00.04)( r* Z7 f: T% Z; q) k5 T- Q
Starting to read D:/CadenceWork/HongelDM642/PCB/allegro/pstxprt.dat $ l* t- @. A0 }, S: i4 e G
Finished reading D:/CadenceWork/HongelDM642/PCB/allegro/pstxprt.dat (00:00:00.01)6 n) P' j3 k8 P
Starting to read D:/CadenceWork/HongelDM642/PCB/allegro/pstxnet.dat
. }, b0 @ A+ K- U Finished reading D:/CadenceWork/HongelDM642/PCB/allegro/pstxnet.dat (00:00:00.03)! B* d# p" b3 l L; v
------ Oversights/Warnings/Errors ------) I E$ B$ L7 M. t. I5 ^: j
) h7 K; S$ Y& d7 W8 B#1 ERROR(102) Run stopped because errors were detected
" `, B' K# |5 Mnetrev run on May 12 21:32:04 2010
3 H3 y$ ^' U. x! L DESIGN NAME : 'DM642_PRJ'
b0 r) m5 ^8 W0 t" y9 e& N PACKAGING ON May 28 2006 22:05:31) t) D' p3 r% V, W9 b
COMPILE 'logic'
, I9 u: c; K8 H% M2 i1 M+ F CHECK_PIN_NAMES OFF' X; s" ?, k( |. l
CROSS_REFERENCE OFF
; E, I9 V4 e2 R) q FEEDBACK OFF
; ?$ m. F. Z- h" D% S% J3 E INCREMENTAL OFF ?) C/ [/ O4 _# j: R
INTERFACE_TYPE PHYSICAL
: @) \+ g. B" l# g* E MAX_ERRORS 500
4 O8 F" W: J j& D MERGE_MINIMUM 56 ~$ W8 M. _, Y7 ^1 r% S
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
@# y0 p- k8 p" J5 W0 \ NET_NAME_LENGTH 24
+ p$ E' _0 i+ H/ Y/ [+ M- A OVERSIGHTS ON+ `( a* U7 ?/ M
REPLACE_CHECK OFF
% e. r( V! Y+ ^ u SINGLE_NODE_NETS ON
+ U7 f; r0 G) f n* J. @ SPLIT_MINIMUM 0
3 _" R& h; w8 P: c0 p SUPPRESS 20
, R6 n& g: o3 ^* c+ L WARNINGS ON
$ n* h1 g }, e8 ] 1 errors detected5 }+ S/ |" B+ w* y. w9 `% ]6 P
No oversight detected6 X7 U5 H. F; b* p
No warning detected! I- R2 q# v: @% b# e' o* }4 |
cpu time 0:02:360 i1 C# a, q6 B1 B, D/ a
elapsed time 0:00:01 |
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