|
|
EDA365欢迎您登录!
您需要 登录 才可以下载或查看,没有帐号?注册
x
本帖最后由 zxli36 于 2010-6-10 11:22 编辑 5 k: E4 G2 J7 R
5 X0 h: d& O5 h/ y5 |) z" X' a0 M6 V
有一个项目文件,已经画好,出过网表,画好PCB。现在要交给其他人稍微修改一下,发现同样的文件(没有修改过),orcad在DRC的时候出现了DRC0039的错误。
; `. `: O1 E' y5 R! ]具体情况是:项目采用层次原理图设计的方法,所有的错误都出现在顶层原理图上,是总线有关的错误。% O6 Y6 ^8 H" L" j, r* {
具体错误信息:
9 l! Z9 C2 G3 ?Checking Schematic: 00_SYSTEM
# x0 z6 Y7 m; \--------------------------------------------------
/ _+ E# q: Y' I: h, b4 @Checking Electrical Rules
6 h! F+ A5 }5 a" d; \$ y; ~7 E! N6 D+ i: G+ C2 v
Checking for Unconnected Nets( U5 i9 p I, B
" P& ]$ S) ~2 W. F
Checking Off-Page Connections s8 T" ~; H1 b0 Z
7 ]& G9 L. T/ _
Checking Pin to Port Connections
1 X; |; ?8 M* x" i" Q
9 D0 s* _7 @9 a$ s8 g2 M. Q2 `Checking for Invalid References8 q& D/ \9 }" h/ @ h
: p1 k" N5 d" D6 GChecking for Duplicate References0 N; P0 ^& H% P# m
+ s7 z7 S- k$ B3 U6 [/ R# p2 _
Reporting Off-Grid Objects* F( c% i4 a# N/ F
G6 a$ n: k) c0 O; j
Checking Visible Unconnected Power Pins
6 ^$ Z6 Y6 [8 t# p
7 H2 m: y6 f. zChecking Misleading Tap connection. V- k6 m: `) i9 f# G
ERROR: [DRC0039] Tap may not be connected with the bus Check Entire net. CPU_XM1_ADDR15
) B" P1 E$ l8 m# g* r 00_SYSTEM, 2_BLOCK (276.86, 25.40)
, b0 l9 u; B9 q4 |4 Q4 Q, Q& bERROR: [DRC0039] Tap may not be connected with the bus Check Entire net. CPU_XM1_ADDR145 y6 t8 I9 T/ k V
00_SYSTEM, 2_BLOCK (276.86, 25.40)
1 Y8 s5 K3 l2 mERROR: [DRC0039] Tap may not be connected with the bus Check Entire net. CPU_XM1_ADDR13& W, o" a4 g2 D8 ^+ g
00_SYSTEM, 2_BLOCK (276.86, 25.40) * r' p* ?0 a T+ i
ERROR: [DRC0039] Tap may not be connected with the bus Check Entire net. CPU_XM1_ADDR127 S) X, a. m7 B! g* y( V6 ^
00_SYSTEM, 2_BLOCK (276.86, 25.40)
3 n* E0 |5 u, G x6 F9 R。。。
) A) i* N* G b+ [7 u============================================================================================
7 A) J; I' v! G) e/ A8 [官方文档的解释:
- i' y/ J8 C. B" @[DRC0039] Tap may not be connected with the bus Check Entire net. ) N; l+ Y' H/ r. l: z
Design Rule Check detected a net physically connected to a bus with a different base name than the net itself. To solve this problem, make sure that the Tap is property connected to the bus. 1 d: i( G0 e3 {- k" h
==============================================================================================
% Y/ t/ z8 U1 a- n, q9 _- x错误处截图:) f2 l! z) M9 b' O& c: [
2 ~6 e; i4 @4 A$ A* L
* Q1 I2 }7 H- f/ e/ x/ @2 I2 _==============================================================================================
7 s! V l3 J) ]3 _& F8 v# L( l# B注:
2 A$ N" g7 l* ]' v顶层原理图上的大部分总线均出现这样的错误,仅有一条总线没有问题。5 ^! p% T4 ?7 Y' k x
* t1 M$ n( u5 K# x==============================================================================================
# Q z) c- f2 {8 y! G希望遇到过或者知道这种问题的大侠们多多指教。- y( a0 b/ [" G+ _% P7 a
. M) }; i3 ^! ^. l U. u4 t==========================================- a! d2 K) o$ H$ k1 A
新发现:DRC,发现和这个选项有关:Report misleading tap connections8 d4 q3 H' X" P0 r$ Y
如下图:
& q0 C/ i7 F: H4 \原来是勾选的,就有以上错误,现在不它取消后就没有这样的错误了,请知道内幕的高手指教下。3 ?, D" t* y9 M* e+ Z/ m
|
|