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本帖最后由 auto1860 于 2020-11-4 13:30 编辑
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链接：https://pan.baidu.com/s/1f4DTDBhhjcKz4On13yCxSg
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$ I* P9 J( F" `" R9 J6 lFixed CCRs: SPB 17.4 HF012
W( i t$ B& D9 R+ f10-30-2020
' @: _! _9 o$ W' a1 A) e8 [0 X========================================================================================================================================================
8 @1 e4 f' X6 v+ Y; }CCRID Product ProductLevel2 Title
& A$ B; L( W/ n# X* a: ]0 P. l========================================================================================================================================================
[: I; f9 s- ^' R, D. e# Z, _2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias.
& d, \8 e5 d7 \* |2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation ]4 J; H1 k6 G8 D
2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly
, h5 k6 |2 {$ }2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening'
: G) E( i% B+ \# c7 [& b2 Y8 ]2 Q2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking, B* p- ~% c0 W4 b" y X4 j
2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234)
- A1 q# F4 P' D' n% ?7 c2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC
* |# J# {1 G9 p2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter
2 ]0 f, g- K7 X% I4 K( [2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format.
, M' a( i. n1 f2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape'
/ e. ^# V0 t0 O$ p2 K9 U- \7 l- b9 m2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait( ?% O8 n% B, N5 n9 [/ F
2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst
9 y7 J! Z! R5 _, A+ n; ?8 N- y2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process+ { O/ G6 l a; v- o. w* {
2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error* S. H7 u& N9 e: h. Y
2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.
9 s5 t1 t5 H& C: a5 u9 K0 l- `2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area
% B8 |8 S) w! @& d# @+ q2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding
8 b9 r; r: s! N9 \. j2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC5 y6 e/ u0 L" s# Q2 m, Y9 @
2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified# ]; ~7 v0 {0 x# K$ Z8 s: E; G3 w
2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text9 o8 D( v) x5 x+ Z
2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes...' pop-up menu option changes only the Min BB Via Gap value
1 l, w5 M) V4 f+ q. e' K* v& X2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group
! }4 e$ |* P' \2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager
; s9 F U) w' K/ ? W2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions3 e/ s8 X2 y) Q% X
2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect
& e+ a1 D4 F8 E8 O' @: f R2280766 Pspice MODELEDITOR Error while converting Verilog-A model
; G1 w! }7 S" {3 V) {2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name
, \! h5 _# k- a+ D; Q+ y4 n" B2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work
8 |& S) N5 M+ X4 c ~% J2346643 PULSE ADHOC System Capture crashes when adding a part/ v( y1 s5 d. I( Q+ p9 X+ c
2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings
' H8 B9 Z' A6 U2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database0 f# _$ l* b8 E
2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1)
1 R. d/ p4 T( |8 x' X! {" l2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants
5 c' F. _, Z& o# V" [$ P4 d2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete8 C7 K V8 Y" q( ^$ X
2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design% _0 ?8 ~2 Z% C+ X/ N8 S" t S
2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field
7 W: c: \4 [& c2 c( Y2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt7 }, q; C& f* A4 s8 S) l; n6 G
2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR9 X/ V. }+ R, z
2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol
# K) D0 H2 H0 ~9 u5 i/ h# q2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance/ K2 H- }) U% H U6 a
2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires
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发表于 2020-11-4 12:16
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发表于 2020-11-4 14:16
