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本帖最后由 auto1860 于 2020-11-4 13:30 编辑 * s+ `" Y1 |4 x# K
" C' y* I; h3 N2 w! A) \) x" ?链接：https://pan.baidu.com/s/1f4DTDBhhjcKz4On13yCxSg
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Fixed CCRs: SPB 17.4 HF012
O: r" O1 [* t2 w6 K10-30-2020
) L1 R( X& l9 u; k========================================================================================================================================================/ C/ E- ]# j3 E2 s4 p6 K% O! O5 Q
CCRID Product ProductLevel2 Title" i# Q7 {6 x" k, m5 W0 Y
========================================================================================================================================================+ d4 C5 W" q" |1 e
2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias.
( E' P3 x2 q2 u! ]2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation
c, H; ^5 x& j" _2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly, `; F1 j- m! b( F, V+ v
2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening'" o( Z5 a5 ]$ y
2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking6 i: \ e+ u) V1 o" E1 Q
2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234)
! v/ @0 n8 B8 h% ]; a) n7 l: B2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC
: G3 K, ?/ s) O2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter; w' U% W0 q2 B! u: A: c
2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format.! k; \" ?) O$ _0 J2 W. I
2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape'
; U; a3 \& r$ |, q# @3 ?2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait% _4 Q0 k$ |; u3 y& M m
2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst" q0 |5 J/ `) i" E
2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process, {8 E% [/ H. m" p- k# ?; g
2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error
9 X" [) D# Y) U. C8 x2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.
6 Q9 Y" z' c" {/ r. c4 q% C. B2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area
, ^& K1 u5 z. g: ]* m8 l5 [2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding
9 x2 p4 _& U# V! _5 m2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC
) Z% B( J( p o) {- O2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified
% J/ A* o5 ?; b( D g2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text4 H. T. K2 a1 ^% M
2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes...' pop-up menu option changes only the Min BB Via Gap value0 W$ m8 z4 d8 |
2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group
! d) f b7 Y+ ?/ K; z2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager1 P5 J9 u5 x3 B1 J9 V& u7 l
2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions- z- z8 N* t" d1 d P
2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect4 a8 u1 X0 k7 o# @$ Z; I8 d( p
2280766 Pspice MODELEDITOR Error while converting Verilog-A model
9 O4 Z* v, x& g3 n) w. N3 d* ^2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name$ g8 x) d9 q, Q! t
2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work
2 g9 t& l& P' M- P, I- e$ F2346643 PULSE ADHOC System Capture crashes when adding a part+ t" j0 u) P4 k; r+ f
2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings2 h# t: ^4 Q6 ?, e0 k) ~0 H. t+ l
2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database
- W( k) S- m+ b2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1)
1 E( A$ F" S! O4 j. q2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants
& H* [" J/ U8 e3 m. q7 I( l2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete
1 B( R F' S4 x1 U# d3 e2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design
4 \7 G) x& ]; [. V S+ W2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field3 E6 P1 }+ N7 g
2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt
$ q: A+ O' w# J2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR
! h5 i$ v' Z, j" a5 P9 j2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol
! X6 C0 }8 R4 K1 g# s7 d% V3 }2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance u# F" X3 ]6 |
2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires
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发表于 2020-11-4 12:16
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发表于 2020-11-4 14:16
