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本帖最后由 auto1860 于 2020-11-4 13:30 编辑 / t$ n9 G. U8 ~5 I0 J P: f
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链接：https://pan.baidu.com/s/1f4DTDBhhjcKz4On13yCxSg 8 h! n0 X$ f1 ?% a! R( ?5 n3 O
& S) d5 X2 D, ZFixed CCRs: SPB 17.4 HF012$ g: u1 }3 O7 ?8 o: w
10-30-2020
$ F4 a% Z ^$ P4 u' F3 F: R2 E========================================================================================================================================================
, H+ H3 |: T2 i- X% o" PCCRID Product ProductLevel2 Title
+ R9 U2 p: S4 U& B) O========================================================================================================================================================: A8 o+ d4 t' @' ?% F
2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias.1 v# K! V* `# u9 R o1 \/ k c) h
2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation, h/ i. B$ R0 {' V
2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly: ^- i: G, `+ j& {
2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening', }; ]# K' I# k ?! i- |2 N
2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking
: h! p O$ @' h: K" K5 h k2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234) m/ V! {) |& C. J9 U3 G0 l
2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC) J: d' ]+ @) F x. u8 s2 k0 j
2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter& T3 x6 @* x% k9 l+ q& i, |4 v- y; i& F
2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format.
1 p6 s5 T! J6 s4 Z0 G& s1 R2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape'
. {1 z& q: z7 @& g" T a2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait/ n1 e6 L$ R2 G) y
2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst
' r1 T/ r: F2 @ v3 `: W' |$ w- R4 C2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process
( @1 S1 j, A+ b, [7 H: V) j* F2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error
3 N! w2 @1 f7 z+ o7 }; F7 ~2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.( ] p8 O- }' c& Q+ o% ~
2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area3 b0 V' _# ~/ j3 j* L* J; p& o$ r( `
2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding
_9 R4 O& L+ k2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC
( O* [# |5 S* S4 r$ ?2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified7 \4 ^; I6 t' i! F. B6 l. C
2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text
4 q& D( T3 W% x2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes...' pop-up menu option changes only the Min BB Via Gap value1 L$ r3 t2 d; M0 T5 R! Z
2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group
2 I- T$ o4 E' x3 }( |2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager
7 J7 U. ], H" [* K0 A; T2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions. U" B% J! J) Y
2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect9 T; B9 s* B, i1 z$ C
2280766 Pspice MODELEDITOR Error while converting Verilog-A model4 S) X& G: X, R4 y9 e( _& T
2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name9 Q* M( c7 M7 B0 Y8 C
2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work
4 ]" ?0 V+ Z& X, B2346643 PULSE ADHOC System Capture crashes when adding a part
7 X+ ~6 p5 L# H; y2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings
( T) v. k+ }' l4 K* X$ w2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database
# I/ K6 b( O( P! q. J2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1)
& o) a: @) y9 B, S* {3 Q3 ?2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants( L6 R; ~- }9 G* k
2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete9 e) [% E) |$ n
2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design
" X, e& `, X' N$ M L- t6 |) T2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field/ `5 G+ ~ |' }/ A: @3 d# \
2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt
! _* T& H+ b6 N: `. R, d4 \2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR* l: V* V& A$ S ]' F7 o
2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol
( v, _- S1 ]3 c; b2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance
% @ ?: o9 j0 u* h' H4 Q% G2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires
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发表于 2020-11-4 12:16
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发表于 2020-11-4 14:16
