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本帖最后由 auto1860 于 2020-11-4 13:30 编辑
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链接：https://pan.baidu.com/s/1f4DTDBhhjcKz4On13yCxSg
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* E( a# s& h1 Y1 s' r* q }- W+ {Fixed CCRs: SPB 17.4 HF012+ X2 o# P6 `! K6 H/ b
10-30-2020
8 X' u! J+ K9 D" b* ^# U========================================================================================================================================================% s* Q) e& g Q; Y5 W
CCRID Product ProductLevel2 Title; f- t* @2 V3 }9 n% u
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2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias.1 r% l+ o/ p% X/ }( R. Z9 y
2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation
0 A/ D/ j& R k- ?2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly
6 z, ^9 v6 S @' w. l8 Y2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening'! ?/ ]) x4 [5 U/ t
2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking
_+ ]" j5 U1 ^3 p' B9 P2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234)# f, g. N) x# t+ [
2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC
, g x: O6 d& b/ }; t/ R2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter
' i/ R9 T( [8 M% l2 h2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format.0 J' s0 B0 Z2 I9 k2 t, F7 Q
2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape'
# g; F) T3 U/ `$ d% R. g5 b2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait
# M& s8 D+ \& W! N1 U6 D/ o, I2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst7 Y. y' i9 G% l# I
2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process- X; }! A2 E$ w
2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error5 x' [* v9 @% r+ R
2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.
) n" } |; V2 t, {2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area! P* [4 `$ Z5 y6 ]6 T ^ ~
2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding0 K& M$ N+ U; G3 m4 ]! p
2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC2 Y* } h% X' P7 S( [% k2 V
2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified
. F' `8 _9 |# c4 C" P1 C) P9 u2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text: ]! K. B5 u* T- f9 i
2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes...' pop-up menu option changes only the Min BB Via Gap value
1 Y: ?' K1 z0 W! m* U% f# X8 {2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group
$ I/ t1 b- Y4 ^$ W" t4 {2 ~; m% i0 h2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager
6 P# |6 s0 J" s; t9 D$ B! N2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions5 E' |1 P& y# e! g3 Q. }1 T# A; k j7 e
2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect
3 [1 p8 |5 y" H: W9 h* N$ l2280766 Pspice MODELEDITOR Error while converting Verilog-A model! N2 k1 \' f3 F& l3 L R' M, V- L
2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name
% V, E4 K2 H! q& s1 U2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work: G ^% ~! Q3 n! q
2346643 PULSE ADHOC System Capture crashes when adding a part
! K. V# V7 v' C! w2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings7 n" r$ [- J4 Y8 n' E# D, y4 z
2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database
6 k: P# M4 T( T1 Y2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1)
% i4 ^/ X1 v6 G2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants
: {8 d4 x& m) L4 |2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete( b# t7 L& u- j) E9 b, _4 z* ]+ o
2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design
Z7 \8 m1 L$ X! |2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field: n/ ^; k/ @: w) T$ p: C; q
2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt$ Q! z; w- Z" e
2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR& d4 k6 n; [3 n: }5 S2 R( h
2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol$ j0 j" e4 n0 S! K$ `# {
2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance
+ y& z; G- b% }' n# C! q1 H- P2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires9 Z8 P- w' N( t9 C
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发表于 2020-11-4 12:16
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发表于 2020-11-4 14:16
