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本帖最后由 金志峰 于 2020-11-5 01:02 编辑 1 w' z' z: |/ Q) r
N" s0 y4 Y9 w! ^6 J% ?Hotfix_SPB17.40.012
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$ V' o0 M6 h" h5 q8 {# I百度云链接: https://pan.baidu.com/s/1udP4SQr7pERhzD2tHlMuCA 提取码: a6q4 6 {6 `/ ]1 u$ s3 N9 J
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Fixed CCRs: SPB 17.4 HF012 - Date: 10-30-20209 d2 E/ S8 _. H& h
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CCRID Product ProductLevel2 Title
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( V7 u/ F2 A6 h* S2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias.* d \$ z8 F" P, Q$ [7 T
2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation$ {7 ~9 |3 ~8 J- B
2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly
6 E* W" g2 _7 H4 Y* F! F2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening', `/ ?, J. v+ j
2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking8 Z, u& Z; K0 E. J
2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234)0 @- Y, R8 u5 W- \
2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC! N+ t4 @8 p( ^! r! l% \
2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter7 U6 m% V5 E! u7 P# ^( n9 m
2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format.5 o0 Q+ {' s; a9 c1 X
2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape' e# w, D: ^. g& G- `$ {& |
2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait/ y9 i5 V! b% S+ V7 k. F
2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst
' {; b( y+ [6 f' b" Q2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process/ F# |+ E" s! t4 h9 K
2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error1 l% N* ^$ S" N7 i9 I# F
2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.
$ B5 p+ k b' B! g2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area
8 R2 A, I4 `8 O$ L7 T3 z( G7 h7 J2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding
- H; l) ]) X: Z# q/ p. E2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC, G4 \+ Y# ?/ w: i3 A
2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified
- _$ \. K( y' ^$ K7 ~# L2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text5 O3 c: ?: U/ I+ D' @/ Q
2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes…' pop-up menu option changes only the Min BB Via Gap value
/ ]$ k3 y* m: G- |# n2 j. J2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group
9 w6 I& t* f8 I9 \" i$ V4 y3 N" l2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager
5 T6 c1 M7 G% Y- w) ?/ W2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions
% u6 p: g1 k# z5 {4 i2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect0 a6 U9 \4 A& S7 M# b* F2 o
2280766 Pspice MODELEDITOR Error while converting Verilog-A model, V* O4 T j' e) _/ D& v0 E* F
2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name. d; _, d5 K8 M/ F7 i0 N
2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work1 K* a! U5 ^/ e# q+ _# }. _1 t
2346643 PULSE ADHOC System Capture crashes when adding a part
$ ?8 \" B* O7 J2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings
( X0 E* A, [7 F' q9 k& ?2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database; u2 W# w! |4 d. m% ]7 v
2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1): n. J, t+ ]0 t8 R) X
2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants
9 k0 G$ K7 _8 v5 l2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete
/ z; @4 @( z% n3 ]9 M2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design& R/ n$ n& P2 q6 U4 d7 D- R
2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field
3 D8 W% o2 V! Y4 l2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt
8 v1 j4 I R- n$ I7 i' e2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR
/ L" i8 d: S) b8 a8 q2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol
4 X. P0 w% ?% ~/ ^* [% j2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance( S; r# ^& O) y3 |9 x2 s# t \* V- L4 Q
2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires
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发表于 2020-11-5 00:58
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