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本帖最后由 金志峰 于 2020-11-5 01:02 编辑
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Hotfix_SPB17.40.0125 ]4 O$ v1 _6 A+ ^6 p6 I3 d
5 J% \( G E% N百度云链接: https://pan.baidu.com/s/1udP4SQr7pERhzD2tHlMuCA 提取码: a6q4 % G: C9 R4 i r2 U
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, i; k" H9 h2 A O) K' R0 zFixed CCRs: SPB 17.4 HF012 - Date: 10-30-2020 o3 o- K! Z( c( \+ k- c
1 p7 A3 t& ]( Z S' v, r+ ]! G: h=============================================================
* n7 W2 ]4 Y" {$ RCCRID Product ProductLevel2 Title1 v, \: o! c- I& H; S; w
========================================================================
8 T6 s# z5 |4 C) Z2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias.9 I- N! X1 s: c. |: {
2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation
( N8 A. P8 j3 k( @2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly8 q* P/ x: Y; J
2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening'
) u& e/ m; o. W8 B( f2 y" _2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking3 A* x. Q8 ]6 {# R
2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234)2 K, L& ^/ F( [5 [! k7 s
2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC' c; E8 q0 l6 [: e' A. w
2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter; ?. b8 ]' u; d" f& ^
2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format.
: b. k% x: J" P2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape'! G4 k' `# p- z: e
2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait
# x# d B" H% D0 k N2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst
$ i, |1 i. m' @& ]. ~9 \2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process
" A1 b8 A( U6 ?5 C) w2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error+ ]" C F# r1 Z
2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.
% }9 `: }; Q5 i7 T0 A$ o2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area5 u# {* Q3 p/ m. e ?* }+ l8 s
2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding2 ^' }0 m" W9 [# v2 ? h$ z
2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC
# f. V, f: l0 t0 X9 l0 d1 A2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified
4 S+ w9 A- p1 U) {2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text
8 b/ p& c5 ]! e& B v2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes…' pop-up menu option changes only the Min BB Via Gap value$ E$ E; l1 b8 K, Y+ _
2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group
( T: h I1 Z4 K1 T2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager3 M+ f. p2 r& v4 T; h
2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions
2 q$ [- a. ~' O, l4 ?; X2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect& n' a) r) @1 N, j
2280766 Pspice MODELEDITOR Error while converting Verilog-A model9 {$ I& v+ O5 m+ P4 h' N
2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name; o* U- x4 u& j) ?
2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work& X. i' T( b3 m `8 Z+ U) f
2346643 PULSE ADHOC System Capture crashes when adding a part
7 R0 \4 w3 K. {9 p2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings
% ?" |0 k+ s4 |4 C6 b D5 u2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database2 s9 k2 @7 f6 s
2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1)
$ v$ ]4 t. p L+ |4 k2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants) e7 f2 e+ }* o" T0 S
2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete8 y0 I, Y( r% j
2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design( l! j; c' ]/ ^; O1 ~7 l; h
2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field
2 u+ d9 Q" b0 N1 x4 I- B v2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt
9 w3 \# p6 R- p$ ]# v2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR; q* k: x3 f3 o, I2 y
2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol4 ^# @! U! ~! C" ^# Z V
2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance* |3 v3 I, g; k
2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires
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发表于 2020-11-5 00:58
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