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Fixed CCRs: SPB 17.4 HF013 - Date: 12-10-2020
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3 W0 h R# M) p: {+ j========================================================================/ S3 _. ?8 l0 z
CCRID Product ProductLevel2 Title; z1 O& m6 k3 J. C3 J& c! P4 ~( f
===================================================================================8 X1 j7 F. a9 D4 o/ W9 y
2317991 ADW DBEDITOR Two symbols named Conn1x28_AB and EPC2 disappear from the DB editor., a/ i$ D: y J
2337802 ADW DBEDITOR Saving Schematic Model Classification created several copies of the classifications and removed the original
! t+ s9 a& L8 s/ s, \% e2344239 ADW DBEDITOR Symbol mt41k128m8da disappeared after checking in to EDM# @! d! E. |) ]
2331095 ADW LIBDISTRIBUTI Schematic symbol missing after undo-checkout in EDM. j0 b5 H, f" O# l3 j1 \$ F. p
2347550 ADW PART_MANAGER Part Manager does not see VALUE property changes/ Y9 I( ]2 |- o0 z+ D {
2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned' ]* ?& ]) d( | T4 u1 j
2247481 ALLEGRO_EDITOR 3D_CANVAS Error message for bend operations being disabled in release 17.2 for rigid-flex: Cannot offset planar face to valid body
9 [- y$ u5 j4 \/ Q$ f8 l2299554 ALLEGRO_EDITOR 3D_CANVAS Error message on starting 3D Canvas and after bending all objects regarding object outside design. n0 w. c5 w( D t$ h3 W% D2 R
2303282 ALLEGRO_EDITOR 3D_CANVAS Unable to bend design+ z# J, f4 S5 D# z* p/ N
2345138 ALLEGRO_EDITOR 3D_CANVAS Bend operations are disabled: Cannot make wires with duplicate vertices7 A0 d) w# P* }% m. @" O, u
2346811 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas bender engine error due to duplicate vertices
5 B" x5 o) G( k. ?1 T2067211 ALLEGRO_EDITOR CROSS_SECTION The Cross-section Chart view in the Cross-section Editor does not remember its settings.
' v" U7 N ^4 d" l- ~7 v2228181 ALLEGRO_EDITOR CROSS_SECTION Allegro PCB Editor cross-section, release 17.4-2019: Pressing 'Enter' does not move to next field
7 r3 M7 M, ? A0 i/ p# V' M8 L( X2210674 ALLEGRO_EDITOR DATABASE BGA component is split on moving between zones; `+ ~- q- P7 v! {
2260964 ALLEGRO_EDITOR DATABASE Backdrill via replacing fails in release 17.2-2016, HotFix 062 and HotFix 066 but ok in HotFix 050 and Hotfix 065
+ ?$ A8 J _& r& V& a+ ^2291817 ALLEGRO_EDITOR DATABASE Corrupt .brd file causes Allegro PCB Editor to quit on running database check
% \; g; y& i, n2317130 ALLEGRO_EDITOR DATABASE Message to upgrade appears on opening DRA files created in release 17.2-2016 even if saved in release 17.4-20194 r" \' [: C! c& Y6 p. b; ]7 k, A
2357413 ALLEGRO_EDITOR DATABASE Import Sub-Drawing (clipboard) stops responding with Venture license: Completes with warning using PCB Designer license3 R6 }3 y4 j2 f; Y$ J
2037361 ALLEGRO_EDITOR DFM DRC not flagged for soldermask features drawn with a line to pin, via, or shape soldermask features6 b- y" W0 w) F( b/ J. `4 Y
2079204 ALLEGRO_EDITOR DFM Enabling option to update analysis mode and run DesignTrue DFM wizard causes PCB Editor to exit
) z) Q$ |/ o N2087181 ALLEGRO_EDITOR DFM DFM reporting false positive hole to hole with stacked microvias
: S0 h/ \7 R+ @0 [2272112 ALLEGRO_EDITOR DFM Mask: Exposed etch area does not work for cline
. f1 w5 |2 _4 n2341080 ALLEGRO_EDITOR DRAFTING Allegro PCB Editor crashes on moving module
# |- }6 A5 K' W' b& v2348334 ALLEGRO_EDITOR DRAFTING Allegro PCB Editor crashes on Component Move! r) {7 I. p/ Z1 _+ V/ a
2271904 ALLEGRO_EDITOR DRC_CONSTR DRC missing for static shape which has an overlap with Route Keepout/ E" {0 \ W# d- Q5 S# j
2341989 ALLEGRO_EDITOR DRC_CONSTR Allegro PCB Editor crashes while performing Update DRC.# T) Y7 {' T! m+ P
2180397 ALLEGRO_EDITOR EDIT_ETCH OrCAD/Allegro PCB Editor stops responding during add route. k5 k m" p4 ^+ |( q" ^
2185709 ALLEGRO_EDITOR EDIT_ETCH Film Area Report stops responding0 R! Z# \* X& a
2341753 ALLEGRO_EDITOR EDIT_ETCH Random crash of Allegro PCB Editor3 Y8 i8 K8 Z0 {. Q3 x
2267702 ALLEGRO_EDITOR EDIT_SHAPE 'Edit - Split Plane - Create' crashing Allegro PCB Editor
+ Q8 m+ l( n% X' b! ~2175472 ALLEGRO_EDITOR GRAPHICS Infinite cursor disappears when dragging a component to a new location.: }7 \. G$ X+ A" W% R( X
2184194 ALLEGRO_EDITOR INTERACTIV New Via Array command usage model issues: Clicking to place vias leads to selection of shapes( J `3 r) x0 M8 [
2242133 ALLEGRO_EDITOR INTERACTIV Line arc with line font and width not displaying correctly9 l) ~# _% r: c1 Z5 B
2244420 ALLEGRO_EDITOR INTERACTIV Highlight SOV is not flagging clines that are within sov_spacing }2 m$ k+ }, m$ R" H0 A! f& b- I
2293704 ALLEGRO_EDITOR INTERACTIV "Oops" command during 'add rarc' command does not revert back to snap grid of cursor3 _' \4 W l$ D' M
2304773 ALLEGRO_EDITOR INTERACTIV Cross-probe with Capture prevents subsequent part selection in Placement Edit Mode
' {: I' {! k3 o7 M; A& H5 T3 p2309994 ALLEGRO_EDITOR INTERACTIV Place -> Via array cannot be placed after preview by clicking on shape in release 17.4-20191 F$ v Y& E) w# g( L
2312593 ALLEGRO_EDITOR INTERACTIV Cannot commit Via Array placement within a shape using Single Side option
% U3 x+ }/ X; {2315052 ALLEGRO_EDITOR INTERACTIV Cross-probing issue when multiple parts are highlighted in Capture, sometimes not highlighted in PCB Editor.
" L$ z* h* f9 P7 M# I; Q- ^5 H2321401 ALLEGRO_EDITOR INTERACTIV Cross-probing issue when selecting multiple parts in OrCAD Capture: Does not highlight those in PCB Editor
- w4 c' P( [8 h$ ]8 K2324879 ALLEGRO_EDITOR INTERACTIV Rotate with function key followed by 'ix' moves component to unexpected location
3 o' {- I8 G V( Q7 O9 w2334085 ALLEGRO_EDITOR INTERACTIV Data tips not appearing if cursor moved quickly to next element.
' F9 z0 S& n+ q& i/ {2346770 ALLEGRO_EDITOR INTERACTIV Unable to place Via array on shape with Array Parameters "Type" as "Single Side"6 S0 b. q @9 y6 s6 S
2347531 ALLEGRO_EDITOR INTERACTIV Copy command results in wrong location while using 'oops' followed by new position in release 17.4
5 H4 w. z* s& M; x2360755 ALLEGRO_EDITOR INTERACTIV Rotate with funckey moves Symbol9 Y) L. a0 w+ k+ C& P1 Y& P! p E
2366514 ALLEGRO_EDITOR INTERACTIV Cross-probe issue in PCB Editor and Capture CIS in release 17.4-2019, HotFix 012: No element found
6 \% g$ d( ~( }: {: q3 ~2132582 ALLEGRO_EDITOR IN_DESIGN_ANA Messaging in command window does not appear in the journal file.# b; z% O8 S6 S- z2 m3 K# o9 {
2306827 ALLEGRO_EDITOR IN_DESIGN_ANA Rise Time and GeoWindow max value limitation to 1000mil and 1000ps
4 {0 T+ w& ]4 ~+ C" c2121233 ALLEGRO_EDITOR IPC Exporting IPC2581 from board is not including tolPlus and tolMinus for thickness of TOP and BOTTOM
* A- E8 _- _0 F" c2295545 ALLEGRO_EDITOR PAD_EDITOR Import of XML for pad stacks not working as expected: Pad files not generated
, ]! o; R) t7 S8 I% l5 F7 C/ m2286761 ALLEGRO_EDITOR PLACEMENT Not able to place via array around void in release 17.4-2019 while it is working fine in release 17.2-2016.+ x1 H; P' ~4 G$ f3 O+ y
2309866 ALLEGRO_EDITOR PORTING Allegro PCB Editor performance issue - slowness with Xorg high CPU occupancy rate1 f6 C0 i7 I% z1 P: D
2350452 ALLEGRO_EDITOR SCRIPTS Incorrect table (vertical) header popup in release 17.4-2019
8 G8 g& L6 H7 G1 I9 [4 a2125268 ALLEGRO_EDITOR SHAPE When shape outline is located at specific area, shape is not working correctly.
0 ~, }4 r& T* t( o2342307 ALLEGRO_EDITOR SHAPE Performing operations such as voiding on shape gives error (SPMHA1-507) stating PolyBool has hit an assert# P/ t$ S: H1 E. h% A: R4 x7 w
2308042 ALLEGRO_EDITOR UI_FORMS Color dialog text hidden by checkbox in Allegro PCB Editor light theme$ c9 |7 k! l) c* T
2318019 ALLEGRO_EDITOR UI_FORMS Allegro displays garbled text
) n* G: e6 U* G9 r2338953 ALLEGRO_EDITOR UI_FORMS Scroll zoom and arrows pan do not work when certain commands are active
; D2 G6 d. m/ d2345208 ALLEGRO_EDITOR UI_FORMS Change event does not work well in String field of Grid in form8 r4 X) A1 p0 j
2351653 ALLEGRO_EDITOR UI_FORMS Cannot switch to other alias or funckey unless command is canceled after setting Alias or funckey for zcopy shape8 b' A- ~6 ^' i# D6 i b! d
2353126 ALLEGRO_EDITOR UI_FORMS The POPUP fields in Test Form have a triangle sign' O5 m- H1 p+ g
2363394 ALLEGRO_EDITOR UI_FORMS Padpath text hidden in Allegro PCB Editor in light theme: k% S* y7 H6 U, _" B+ h/ ^, e: [
2257512 ALLEGRO_EDITOR UI_GENERAL Split view Horizontal and Vertical are mixed up% a& b* v3 _2 R2 p* g# V( ?: ?
2262412 ALLEGRO_EDITOR UI_GENERAL Allegro PCB Editor crashes on using SKILL GRPDrwUpdate() API because GRPDRWDATA->hwnd is not initialized
$ @1 ^. @* F6 S2265250 ALLEGRO_EDITOR UI_GENERAL Checkbox not center justified in Grid form in release 17.4-20196 G" c; u; {6 {' l- }2 ^" ?0 r
2271500 ALLEGRO_EDITOR UI_GENERAL Very slow switching between views with infinite cursor
) q f E3 k, s" `2293753 ALLEGRO_EDITOR UI_GENERAL Issue with using SKILL in Design Workflow: PCB Editor command does not run if added after SKILL command in a task7 U$ j0 V2 k4 q2 P1 a3 U' s
2301681 ALLEGRO_EDITOR UI_GENERAL The Edit>Text command in the layout is creating cursor overlap while editing the text.
0 Z# i y, ^4 C# i# i2302399 ALLEGRO_EDITOR UI_GENERAL Edit Text display issues with insert mode: Not redrawn after text edit done, showing old removed characters! ~; S8 I9 r6 L6 R# M& z
2315467 ALLEGRO_EDITOR UI_GENERAL The border option does not work for text fields depending on other fields around it+ J$ S( Q( ~) R' y7 {7 L
2322601 ALLEGRO_EDITOR UI_GENERAL The cursor disappears when editing a shape area and drag edge if infinite cursor type is being used.3 C, ]; {' N) X P$ m0 X) B
2324334 ALLEGRO_EDITOR UI_GENERAL Menu entry missing using OrCAD Professional or OrCAD Standard license for Tools - Padstack - Refresh, O) j& u( q1 m7 G1 K) E7 Z
2337176 ALLEGRO_EDITOR UI_GENERAL Visibility pane cannot be correctly resized
1 x$ t, n5 [% b' F2338704 ALLEGRO_EDITOR UI_GENERAL Cyrillic text not shown correctly.
( N. L. [1 k$ N" J: T2341742 ALLEGRO_EDITOR UI_GENERAL allgro_lock_toolbar resets on restarting Allegro PCB Editor
% s" e! ~4 C/ V, o2341757 ALLEGRO_EDITOR UI_GENERAL Textbox size is small: Cannot enter value for spacing to align components." j2 B) }" H6 j
2345084 ALLEGRO_EDITOR UI_GENERAL World view not working correctly and does not display cutout with latest hotfix of release 17.4-2019. ]& i$ l) h+ K k" Q6 i$ d1 k L
2347282 ALLEGRO_EDITOR UI_GENERAL Very slow view loading and redraw in release 17.4-2019 hotfix.4 _/ m9 I" X$ V
2354524 ALLEGRO_EDITOR UI_GENERAL Large space in command line between command prompt and typed text$ M! V, F' V3 n! f! s
2356220 ALLEGRO_EDITOR UI_GENERAL Window size is bigger in release 17.4-2019 compared to release 17.2-2016 because of white space
! E( J* w( A( s2356985 ALLEGRO_EDITOR UI_GENERAL Cannot shrink menus to min size
( `( K3 R; d6 r" Q2357540 ALLEGRO_EDITOR UI_GENERAL axlUIWTimerAdd() function not generating elapsed time correctly in release 17.4-2019
' N( I1 C' }0 }6 r1 Q2359766 ALLEGRO_EDITOR UI_GENERAL When using Edit > Text in release 17.4-2019, the cursor under the text turns into a gray/white bar3 T, u; A0 ^; j# e
2168386 ALLEGRO_EDITOR ZONES Bend Area also bends the rigid part
& v) v& S, J+ y/ j4 w2078434 ALLEGRO_PROD_TOOLB CORE Shield Router - cline end caps treated differently than cline-segment end caps
$ s0 j/ ~ a5 i3 g7 C2101020 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC with multiple net classes: script selects only the last two classes in a group0 r' c3 f7 D4 a3 C+ w4 i9 O
2150291 ALLEGRO_PROD_TOOLB CORE PCB design compare cannot compare Cross-section layer name with space( U6 ~# u. p" @$ I$ ?8 j
2075523 ALTM_TRANSLATOR CAPTURE Translation issues with third-party PCB and Schematic( H/ T8 l) f' ]3 L5 j
2336558 APD DATABASE AREF degassing for Gerber export2 F; T2 Z5 _: ?
2222216 APD LOGIC Part is not highlighting in Logic -> Edit Part List
3 I7 j* H! m7 o; r2 Z! }* t3 M2354236 APD UI_GENERAL Manufacture - Artwork: Wire bonds visible when Film view selected2 |: ~. m+ |! B2 F/ d6 E6 a0 f0 ~
2249404 CAPTURE GENERAL Place Part > Add Library > Browse dialog stop taking key board input after Create PCB Netlist) _5 R# q' O' M6 L" Z B
2199790 CAPTURE NETLISTS Netlisting from command prompt gives different results in release 17.4-2019 and 17.2-2016
+ \, u; f8 c( ~7 `* |2340813 CAPTURE OPTIONS OrCAD Capture changes canvas theme after PDF export/ ]$ n: f3 B, Y$ v4 G
2343788 CAPTURE OPTIONS Export PDF changes color scheme of schematic+ m0 d: }+ y) ?' X
2213702 CAPTURE SCHEMATIC_EDI Wire signal, which is part of NetGroup, on top level of a hierarchical design is not shown in signals command results.: [& y' J# g* G0 H
2264254 CAPTURE SCHEMATIC_EDI Crystal Report from Capture in release 17.2-2016 does not display Japanese characters correctly0 U/ v$ A8 x* @* Y- C b2 l
2278930 CLOUD_INFRA COMPONENT_EXT Unable to get parts from third-party Search Provider
( C3 |. K2 `7 _2313388 CLOUD_INFRA STARTPAGE Capture starts slowly when Start page is enabled
8 r% o) b/ K8 e- u1 }) N2332357 CONCEPT_HDL CORE Unable to backannotate or perform 'design sync' from PCB Editor to Capture
+ b" q8 y9 W( y4 k0 s" V, }2333126 CONCEPT_HDL CORE Design sync fails when the temp folder is missing in root directory& O' B1 n: n, s
2306359 CONSTRAINT_MGR ANALYSIS RPD Match Group DRC errors occur after refreshing symbol for silkscreen corrections. N+ u; N1 S* U! K4 }
2239908 CONSTRAINT_MGR CONCEPT_HDL Cross-probe is not enabled in pre-select and post-select mode in Allegro Design Entry HDL.
8 H/ q5 K: N: i5 Q, ?+ g2307873 CONSTRAINT_MGR CONCEPT_HDL Cross probing disabled in PCB Editor when adding net to a Class in Constraint Manager.7 j/ ?5 F I$ z& B0 \ |8 `: N
2238753 CONSTRAINT_MGR DATABASE Pin delays in Constraint Manager showing 3 digits resolution even if pin delay is defined with 4 digits
4 _- g2 N3 ?7 y" h' q# |2351214 CONSTRAINT_MGR ECS_APPLY Importing constraint file in OVERWRITE mode does not delete some ECSETS permanently
: t! l6 b2 m6 H2226652 CONSTRAINT_MGR UI_FORMS Release 17.4-2019, Constraint Manager: Height of column headers is too large" s4 E9 a. U }+ ?
2226663 CONSTRAINT_MGR UI_FORMS Release 17.4-2019, Constraint Manager: Cannot auto set column width by double-click
8 @! v4 B1 N" J& a! Q4 M" B2341522 CONSTRAINT_MGR UI_FORMS Release 17.4-2019: Filtering in CM for Prefix or Suffix does not work9 Y+ @9 M! w! ^; @" I. b
2251671 PCB_LIBRARIAN SYMBOL_EDITOR Drawing or custom shape shows small overlap after reset origin
+ j! ]0 w; z" z' t/ N& ^" l* `2306865 PSPICE LIBRARIES QVBICN model issue: Model and implementation pin mismatch and part moved to different library4 O2 w0 O- ?5 R' M: _) R& x; I. R( Y
2345948 PSPICE LIBRARIES Default PSpice component cannot be placed from PSpice Search
+ c; r- E0 m- j+ u4 S2346793 PSPICE LIBRARIES PSpice install has issues finding "XFRM_NONLIN…" parts.' T6 Q, v$ E1 P
2320996 PSPICE TI_CONTRACT Library update causes simulation errors (ORPSIM-15115 and ORPSIM-15107)$ D. P8 ^; M h9 e5 p+ t
2358318 PULSE ADHOC Allegro System Capture crashing when copying or pasting part or adding new part to design9 d( k% ~: _# z! {, z8 m
2359260 PULSE ADHOC Commits are denied and incorrect status/versions displayed in Project pane
0 b1 C% N& d4 P; D) e2341542 PULSE CORE Versions from Pulse Server using FQDN & Intermediate Cert. Authority (Atom): Control & ad hoc collaboration not working# E' k% [' y! p
2262023 PULSE UNIFIED_SEARC Some object types being ignored during release 17.2 to 17.4 EDM database uprev
0 ?" O6 p8 d. Q. \2356310 PULSE UNIFIED_SEARC Unified Search text color should be much darker in the results section
2 G6 T3 Y4 p* d) t2329757 PULSE VERSION_ON_SA Pulse tray not launching4 A9 m6 ~# p. `$ D% X& i% b
2311689 SCM OTHER SCM crashes during port assignment5 u) N2 Y5 p; L' l; l
2339272 SIP_LAYOUT UI_FORMS Latency observed in APD Plus in release 17.4-2019 when running SKILL code, ^7 n; F$ C6 t# s- F
2345888 SIP_LAYOUT WLP Advanced thieving patterns in .gds shifted after stream out" S3 ~$ q1 r& {- H: m! F$ i; Z
2356097 SIP_LAYOUT WLP Importing external DRCs results in error; K" |$ }4 k0 j% |! R
1972290 SYSTEMSI COMMON case-insensitive in mcp header editor
. G0 N. Y$ Y4 o2139994 SYSTEM_CAPTURE CAPTURE_IMPOR Importing OrCAD Capture designs fails for spaces in package name1 m' l/ ?! L6 F% Z$ W2 S! a
1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDS_SITE path for the current session
# O. H% N6 o3 v8 F" `! R* @2089112 SYSTEM_CAPTURE CONSTRAINT_MA Constraints are imported as read-only in System Capture from a DE-HDL design
4 D( J# d) Y' v6 K' R4 T6 m! H2242032 SYSTEM_CAPTURE CONSTRAINT_MA XNets issues in designs migrated from release 17.2-2016: Cannot add XNets across some resistors after removing
5 V. X% t6 T& `* x' m3 S: T$ A2334411 SYSTEM_CAPTURE HSS_DESIGNEDI Packaging Options for Block dialog, Reference Designators tab: Sample text for both suffix and prefix is the same
5 i- N! H- f9 V6 N% ?/ \1893897 SYSTEM_CAPTURE IMPORT_DEHDL_ Notes in Japanese from DE-HDL designs do not import correctly into System Capture
0 u `) W2 f/ l1983793 SYSTEM_CAPTURE IMPORT_DEHDL_ The ground symbol differs from the power symbol) w, g$ [+ N$ C, B0 Q4 J+ w) b, a
2025950 SYSTEM_CAPTURE IMPORT_DEHDL_ Broken connectivity on imported ground symbols6 H3 t3 I4 U B6 _9 h0 g& w% Q4 C
1969979 SYSTEM_CAPTURE MISCELLANEOUS 'Power_Group' property not working correctly with System Capture: a: r7 O& t. k+ f' F
2006600 SYSTEM_CAPTURE NAVLINKS Placement of navigation links: placed on top of port/off page symbol and inconsistent alignment
4 J" d' ?: e4 T; k- }1 ]* M' U* ~' N2018961 SYSTEM_CAPTURE PERFORMANCE Moving objects and/or groups of objects is very sluggish
* T& E; t. e' N3 {! h+ S+ g2084693 SYSTEM_CAPTURE PERFORMANCE Performance improvement required in System Capture: c. |: G3 X* \( e0 N \
2114146 SYSTEM_CAPTURE PERFORMANCE Design takes a good amount of time to open
6 p, W! \/ p" N5 X1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range4 k9 `! Q- n& u% r- \
2182607 SYSTEM_CAPTURE PRINT System Capture crashing while trying to print Y2 l \& D+ {" C6 _& G$ t/ p
2342128 SYSTEM_CAPTURE PRINT The right edge of the options area is cutoff
8 Y5 z4 F4 Q; }2106307 SYSTEM_CAPTURE PROPERTY_EDIT An orphaned VOLTAGE property gets attached to the page border
& Z! s; ^9 g$ f2080707 SYSTEM_CAPTURE SELECTION_FIL Cannot select component that has a block shape drawn around it.
9 s& k" J/ Q) ^9 @2141023 SYSTEM_CAPTURE SELECTION_FIL Place drawing objects behind the components
7 y7 |, {# U k3 @3 n. C3 t! J2041272 SYSTEM_CAPTURE SMART_PDF Smart PDF displays extra box outline if component is selected% B& b" d" j. H6 m; L$ `
2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF9 I6 I. p1 G4 X3 R, e) H
2269518 SYSTEM_CAPTURE SMART_PDF PLM system cannot process older versions of Smart PDF files
2 t2 k' f! i/ G6 ?$ O; r6 |2298673 SYSTEM_CAPTURE SMART_PDF Smart PDF crashing when Remote Desktop Connection is used/ A |& x% n8 {
2318787 SYSTEM_CAPTURE SYMBOL_GRAPHI Pin numbers overlap bubble pin stubs
5 ^& T7 ?% s4 B f* T# w$ l2082594 SYSTEM_CAPTURE UI Component Replace should seed the Component Browser with the part's existing properties; `4 z7 L! e$ K m& y
2218534 SYSTEM_CAPTURE UI 'Auto Create Differential Pairs' command missing from the Tools menu
d, d3 a, t1 S( A3 ^2221714 SYSTEM_CAPTURE UI 'Tools - Auto Create Differential Pairs' menu option is missing
5 ~6 Z+ P6 `- g% D2269532 SYSTEM_CAPTURE UI Voltage values missing and incorrect names displayed for power symbols
' p- O7 r1 f5 G2274042 SYSTEM_CAPTURE UI Bus tap bit number XY location and symbol colors changing5 ~8 H: ^; K+ A3 j% I- a
2354836 SYSTEM_CAPTURE UI Moving objects causes it to appear very far off the page4 q2 |, J" J& E' I
2361110 SYSTEM_CAPTURE UI Moving a border shape with a text box inside causes both to disappear3 ?. N+ _7 L# u# H
2193445 SYSTEM_CAPTURE VARIANT_MANAG Box object prevents selecting a part in the variant view
# `/ o8 N5 d( T2283596 SYSTEM_CAPTURE VERSION_ON_SA Misleading message displayed when a user did not have the required privileges
9 R5 F1 P' n/ u v2010029 SYSTEM_CAPTURE WIRING Zoom is too slow when zooming into a smaller area; A. o, f! @2 n! c6 b9 s
2209521 SYSTEM_CAPTURE WIRING Scalar net name 'synonym' wins and is assigned to bus
/ t% O3 _5 c2 ]2290743 SYSTEM_CAPTURE WIRING ALLOW_4WAY_JUNCTION directive not working as desired.7 K+ L4 l/ E, @# c: G
2340292 SYSTEM_CAPTURE WIRING Net names move automatically when connecting a named net with an unnamed net.+ ?9 f# Q) I- ~6 K
2253244 TOPXP AMI_BUILDER Capability to build standalone Tx or Rx AMI model in Parallel Bus Analysis workflow
! J" H( R$ o$ f8 g) [ R" X2296478 TOPXP GUI Auto-shorting causes duplicate SPICE R element
* A3 q3 ^2 q# C( Q% f2 Z7 l2305071 TOPXP GUI Difference in results at Tx power with same setup in release 17.2-2016 and release 17.4-20193 R, O7 N" h( q
2188372 TOPXP SYSTEMSI Channel Simulator results incorrect when IBIS CLK model is different for P/N buffer outputs
, e) K7 K; u' u% G. {1 k0 ?2218575 TOPXP TCL Provide Tcl support for editing AMI model parameters in Topology Explorer8 o) R" T) m1 ]( X% [: d$ e
2356260 TOPXP TCL Topology Explorer - Tcl commands to automate the entire Sweep Simulation needed |
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发表于 2021-1-6 10:46
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