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[ComponentDefinitionProps]
' M! C0 A) B9 u! dALT_SYMBOLS=YES
1 b5 A0 a+ }4 V$ ~3 ] SCLASS=YES2 W2 j3 F/ M6 M/ o% p0 y) Y
PART_NUMBER=YES) H* m1 A# L; O/ r" M, J& Q
TOL=YES
" t$ F+ G, C2 G8 D5 ?VALUE=YES7 `$ E8 h: ?# k w
POWER_GROUP=YES2 e: Y4 i/ W W& h ~. @
SWAP_INFO=YES
. F W4 f. f' a[ComponentInstanceProps]
V: L4 I$ Y5 t* k1 aGROUP=YES
) L" U! w9 q! L; wROOM=YES
+ p. w! x, ]: z+ |' |. J! x" O0 WVOLTAGE=YES0 B- q. l. L- L4 R- e
9 W S0 F! G- d# Y2 f8 r2 ^
[netprops]
) ^, u" F/ p1 Q# dASSIGN_TOPOLOGY=YES, C7 Y" }4 T- ^/ u+ t5 F' K" d
BUS_NAME=YES) f+ z% i5 H2 t) W2 q
CLOCK_NET=YES
2 ^; b& ]5 E0 f$ Z# `4 x* lDIFFERENTIAL_PAIR=YES
3 |6 F8 |/ @6 dDIFFP_2ND_LENGTH=YES+ {) l% p4 ]- `, p
DIFFP_LENGTH_TOL=YES
$ B" U ~' }8 S' @+ eECL=YES6 n1 }+ ~5 H3 q% z" h* B
ECL_TEMP=YES" f7 h! [5 @8 y# ]# O
ELECTRICAL_CONSTRAINT_SET=YES2 T) D, v8 c' I, F" {* k
EMC_CRITICAL_NET=YES
& e1 Y7 u9 x M" L1 B, l0 iIMPEDANCE_RULE=YES) k' L+ i+ g6 Z4 R- \
MATCHED_DELAY=YES
& V' P1 I% J7 \+ y5 Y2 G. KMAX_EXPOSED_LENGTH=YES R0 D' [! N& N- X6 T
MAX_FINAL_SETTLE=YES: o6 y( ?1 Q3 X6 [+ ^/ k
MAX_OVERSHOOT=YES$ N9 E+ m4 X, K) q
MAX_VIA_COUNT=YES9 J# `' f6 P3 R( T4 g, _6 p& ?
MIN_BOND_LENGTH=YES
' f; E4 }! i6 p: B# _3 K7 MMIN_HOLD=YES3 g$ s% n8 ]* k6 ?; D' P7 J
MIN_LINE_WIDTH=YES r K. t( w' a4 ?/ f# X9 d
MIN_NECK_WIDTH=YES+ d0 z) Y" G' A. o
MIN_NOISE_MARGIN=YES; a2 i( T; h* L& r4 E: d* E
MIN_SETUP=YES/ W5 m- o# H0 r
NET_PHYSICAL_TYPE=YES
5 x% o! L6 h0 `% D5 ?% o/ sNET_SPACING_TYPE=YES( n! f9 d, T1 w/ C
NO_GLOSS=YES1 h7 L) P3 d( ^8 a6 j
NO_PIN_ESCAPE=YES
! T( M& `! w' C$ A0 r/ L) z* [NO_RAT=YES
- G% a' a7 U: y# Y# mNO_RIPUP=YES! k" S# v7 N" w+ r' D d) j
NO_ROUTE=YES& I1 E# L8 x" v1 b
NO_TEST=YES$ _2 b2 q. Z9 G9 Z
PROBE_NUMBER=YES
7 D1 V# G' |. x% _/ E0 z( NPROPAGATION_DELAY=YES1 M- t S) h9 S* z, q
RELATIVE_PROPAGATION_DELAY=YES
9 b, c v: R3 |% C' U E! oRATSNEST_SCHEDULE=YES1 D9 N1 Q( M p& s7 D. `1 g: z
ROUTE_PRIORITY=YES) |4 k2 _2 l3 J+ \ V, Y: p
SHIELD_NET=YES. G3 c A- ^/ \. \; r% D& m
SHIELD_TYPE=YES4 |* ~$ L1 W3 S/ E4 S4 q6 i
STUB_LENGTH=YES2 O& j# I- W+ A& w& S
SUBNET_NAME=YES7 {/ Q5 J- c$ c- t3 a
TS_ALLOWED=YES) n5 ~6 V* }8 M: F/ ]+ E% @- V# n' k
VOLTAGE=YES( F, x5 i: k+ I1 I
VOLTAGE_LAYER=YES* _* @& e E6 {% G$ L
[functionprops]
, p' P2 `$ J* U4 K1 s/ d+ OGROUP=YES! h% j) y& H0 z) O. V7 X8 e- ^/ E
HARD_LOCATION=YES
; _- @3 [$ J0 m- `* H& YNO_SWAP_GATE=YES; d U1 u& D: h. Y( {7 W+ f
NO_SWAP_GATE_EXT=YES' T' ^) n0 T y: ?) K: [: A
NO_SWAP_PIN=YES' h4 O7 F+ P, J1 [. M! u
ROOM=YES
3 s. K) x) C5 x, U[pinprops]
( F/ C* R3 e8 E0 ~NO_DRC=YES, w9 `5 \$ p' \1 }
NO_PIN_ESCAPE=YES' E4 j- \: j& G9 C3 [# y4 K; S
NO_SHAPE_CONNECT=YES
; m& M* y3 k# k& k% V, _/ FNO_SWAP_PIN=YES8 z9 e4 _! c; W) t
PIN_ESCAPE=YES
- M0 l; k$ N" V3 \- a+ t
+ X( m1 n# f/ |+ r1 n4 ^5 x
; W) ]& T1 A0 e" ]. ?& {修改allegro.cfg文件可以屏蔽导出网络表：非法字符的报错吗
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发表于 2011-4-1 14:33
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支持！
反对！
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