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cadence 站点 上的消息。。。。
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- f& c, [0 O( fNew allegro 16.5 Technology
4 z( n6 m: ?$ ^ lOn May 23, 2011 Cadence will release the 16.5 version of its Allegro PCB and IC packaging technology, providing customers with new capabilities for a shorter, predictable, and convergent path to product creation. The latest Allegro technology will be available through flexible on-demand product configurations that offer cost-efficiency and scalability. Allegro 16.5 spans silicon, SoC, and system-level development and offers PCB designers benefits such as: - Higher functional density with a constraint-driven flow for embedded components
- Fewer physical prototype iterations with concurrent team desig
- Faster timing closure with new PCB interconnect design planning technology
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- More efficient low-power design with integrated power delivery network analysis
- A compliant and faster implementation path with package/board-aware SoC IP
- Smoother collaboration among global teams with new SiP distributed co-design
- Flexibility through “base plus options” configurations5 U z$ ?+ V2 f8 n! @
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