基于FPGA的单稳态脉冲展宽电路的设计问题！

marshal403006

请各位高手看看本人的程序，编译通过了，仿真却没有结果。我想实现的功能是单稳态脉冲展宽（通过外端口控制展宽宽度）。程序如下：
计数器（控制展宽电路的宽度）部分：
# _! f/ Z8 Y! R4 \4 h( e# P# xlibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
# o7 |% i; N, n4 U, N, \use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
1 q& Z; P& u7 Tentity counter is
* `" b" X, p) m0 n  port(reset,en,clk: in std_logic;
       N1,N2,N3,N4: in std_logic;
       feed_out: out std_logic);
3 ]9 o+ }/ V2 D; q; o  end counter;
3 S/ W: }6 d! d& Z! Parchitecture Behavioral of counter is
- q3 K- K1 j. ?3 A$ k) z% Q& Jsignal temp: integer range 0 to 15:=0;
signal k:integer:=0;
begin
& g* A( j2 o  U+ m" \$ uprocess(N1,N2,N3,N4,k,clk) is
( P; |1 \% |- _- V: C2 h8 ibegin
   if(N1='1') then temp<=temp+1;
0 P4 B8 \; i8 Y; j$ L  elsif(N2='1') then temp<=temp+2;
. \3 y' S$ n2 s4 o2 f  elsif(N3='1') then temp<=temp+4;
  elsif(N4='1') then temp<=temp+8;
% w1 S4 n5 e5 w  f% r) O, P  else null;
  end if;
5 t# v* b( }4 M  if (clk'event and clk='1') then
1 y- Z1 I# _/ f! ?' j    if (reset='1') then
       k<=0;
7 _; i- U0 [9 P  i1 e     feed_out<='0';
     elsif (en='1') then   
( {* H$ i( o' N5 Q1 w, u7 |5 h    if (k=temp-1) then
; _) J( x6 k4 h9 t- j; N         feed_out<='1';
6 Z2 d' K  P- P6 E( `         k<=temp-1;
+ s6 e( O1 L+ C4 R     else k<=k+1;
    end if;
    end if;
) Q  P) F4 u$ U5 U0 f) u: tend if;
+ k8 }: g1 h) qend process;
5 s1 `. H; u& {0 dend Behavioral;
D触发器（脉冲前沿产生电路，又是展宽脉冲宽度形成电路）：
* r- ^7 X/ }/ A9 H# zlibrary IEEE;
: q: O# S) j3 Z! Q+ ]use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
6 z. @4 G$ t, u& H1 O) Ientity D_trigger is
8 L* B+ A6 y' r! c2 Z  J  port(D,clear: in std_logic;
; i+ K' T  p' r, T; l( V5 n       clk: in std_logic;
3 j3 T, r- K# y   Q: out std_logic);
end D_trigger;
3 X$ D0 k( [- c( E; P& H8 _; Earchitecture Behavioral of D_trigger is
begin
6 ?: T$ K) n7 _7 l: l) ~$ i, ^( L" `+ bprocess(D,clear,clk) is
begin
1 \9 a  d, ^* Z- `  if (clear='1') then
    Q<='0';     
( V$ W! Q# {# Q  \8 i  elsif (clk'event and clk='1') then
    Q<=D;
  end if;
end process;  
end Behavioral;
外部综合部分：
) c) b; G) x3 m+ Z) d8 Z8 F+ Xlibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
! Y! A9 @/ |# y7 O, I) ^use IEEE.STD_LOGIC_UNSIGNED.ALL;
* d5 S/ s4 T2 W; Ventity pulse_expand is
  port(pulse_in,D_in: in std_logic;
       clk_in: in std_logic;
2 f3 u" F  v) F5 E, }; \   n1,n2,n3,n4: in std_logic;
; d' D) j7 `3 `2 P. v' ]( n8 _" M! P   pulsewidth_out: out std_logic);
end pulse_expand;
3 C- I" l" a& j( sarchitecture Behavioral of pulse_expand is
& K. c+ @# j0 R- osignal a1,a2,a3: std_logic;
component counter is
   port(reset,en,clk: in std_logic;
' n* [/ w) Z2 D# y! k* R0 \5 j      N1,N2,N3,N4: in std_logic;
        feed_out: out std_logic);
  end component counter;
  m+ G, d3 X. S' r  component  D_trigger is
     port(D,clear: in std_logic;
2 r. |8 Q' I" }) S2 L          clk: in std_logic;
' N" H  }5 \  C7 C+ |( C% D      Q: out std_logic);
8 X) ~  I4 I" ^( K  o  end component D_trigger;
& w% ^( e6 ~/ x. i/ ^begin
P1: D_trigger port map (D=>D_in,clear=>a1,clk=>pulse_in,Q=>a2);
a3<= not a2;
P2: counter port map ( reset=>a3,en=>a2,clk=>clk_in,feed_out=>a1,
    N1=>n1,N2=>n2,N3=>n3,N4=>n4);
pulsewidth_out<=a2;
end Behavioral;

[ 本帖最后由 marshal403006 于 2008-6-2 09:38 编辑 ]