基于FPGA的单稳态脉冲展宽电路的设计问题！

marshal403006

请各位高手看看本人的程序，编译通过了，仿真却没有结果。我想实现的功能是单稳态脉冲展宽（通过外端口控制展宽宽度）。程序如下：
: S  n' M: Y- f( p: s6 r8 I! B计数器（控制展宽电路的宽度）部分：
library IEEE;
3 O4 I) f# X3 s8 ^: k- duse IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
. P3 P7 {8 I7 m; U! V. [6 l  port(reset,en,clk: in std_logic;
       N1,N2,N3,N4: in std_logic;
0 @0 ^. R) y5 Y9 |' \- n$ f       feed_out: out std_logic);
; Q. H) h. z( }8 B5 Z' K) E) S: I  end counter;
architecture Behavioral of counter is
signal temp: integer range 0 to 15:=0;
signal k:integer:=0;
8 E% a0 y# z& ?2 G2 Wbegin
$ H6 b% C# }  P1 x+ ?- j! Tprocess(N1,N2,N3,N4,k,clk) is
  B9 T; U7 r. ]9 jbegin
" E' o: E  M0 G+ u, C/ {6 F   if(N1='1') then temp<=temp+1;
9 k3 |, {& a  {. c9 z8 \5 L/ X  elsif(N2='1') then temp<=temp+2;
" n# X* \) w; l3 r& r5 m$ {' }# x  elsif(N3='1') then temp<=temp+4;
$ v" Q4 E$ D! d  u' Q% ~  elsif(N4='1') then temp<=temp+8;
5 X: @. K% L, m: N6 O  else null;
) \3 }* A6 z2 b( Z; W: q& m  end if;
  if (clk'event and clk='1') then
    if (reset='1') then
       k<=0;
     feed_out<='0';
     elsif (en='1') then   
4 y: [5 l9 T& o  N    if (k=temp-1) then
# o' G' n: }2 v8 e2 i         feed_out<='1';
         k<=temp-1;
# f9 J6 r7 D/ N     else k<=k+1;
) i( ]$ b5 \" J) O+ F    end if;
; {2 \! v7 x( J, v: H6 g& G    end if;
- \1 s' g$ _& R3 kend if;
end process;
4 j' D7 `0 V9 oend Behavioral;
D触发器（脉冲前沿产生电路，又是展宽脉冲宽度形成电路）：
library IEEE;
7 {4 a  `# {5 `; _: Duse IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
* O0 L2 @9 F! G, y9 W' nentity D_trigger is
: ?# ]! @+ e- {# G: ^7 V. P) ~  port(D,clear: in std_logic;
4 u. n$ _' Y* i       clk: in std_logic;
   Q: out std_logic);
, b. m- k0 Y! a, _7 {- Uend D_trigger;
0 I) @. _# v+ J4 d1 ?3 V6 n) V9 J  @architecture Behavioral of D_trigger is
( G" [; S) i* B$ C0 Z/ H# Dbegin
% p1 E2 j  P% x$ t# T9 U2 _# C6 Wprocess(D,clear,clk) is
5 v0 d% @$ J& Y+ s1 e' ^7 Y) bbegin
, g$ s9 n+ S+ P& m& G+ L  if (clear='1') then
    Q<='0';     
  elsif (clk'event and clk='1') then
    Q<=D;
' G& ?+ z" G5 n3 e* q$ l  end if;
end process;  
$ E: E9 |# `5 g0 s6 Cend Behavioral;
外部综合部分：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
* P! k( ^* e! E8 S- @: F# M( |use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
4 h) k. @; t" F8 _% q0 |# j- ^# wentity pulse_expand is
9 b9 r7 [2 {- h5 }  port(pulse_in,D_in: in std_logic;
       clk_in: in std_logic;
   n1,n2,n3,n4: in std_logic;
/ y/ k9 Q3 \6 Q; J. N   pulsewidth_out: out std_logic);
end pulse_expand;
architecture Behavioral of pulse_expand is
2 d+ M) L6 m2 K7 Isignal a1,a2,a3: std_logic;
component counter is
! x) o8 W: B: G$ P, k   port(reset,en,clk: in std_logic;
      N1,N2,N3,N4: in std_logic;
        feed_out: out std_logic);
  end component counter;
  component  D_trigger is
     port(D,clear: in std_logic;
/ C' m6 r# n  s+ Z1 V! Q          clk: in std_logic;
3 \$ S. [# B2 q# i! i4 ^" ?2 X      Q: out std_logic);
/ q$ n: X1 J% A: G8 Z4 F  end component D_trigger;
) G/ {/ N  r( S" U' Q3 cbegin
P1: D_trigger port map (D=>D_in,clear=>a1,clk=>pulse_in,Q=>a2);
) `" j2 A3 Y1 x8 K) T' }a3<= not a2;
. r- m! x' f" VP2: counter port map ( reset=>a3,en=>a2,clk=>clk_in,feed_out=>a1,
    N1=>n1,N2=>n2,N3=>n3,N4=>n4);
pulsewidth_out<=a2;
6 {, t2 Z7 a  o+ @4 d! \: {6 f* Lend Behavioral;
9 }) ]9 K3 O- \6 w& W
7 O6 U# N% b: @1 v* s[ 本帖最后由 marshal403006 于 2008-6-2 09:38 编辑 ]