Orcad capture生成网表时出错，大家帮我看看

lyf9908

大家好，以前用AD6,pads, 与在用SPB16.2,很不习惯呀。
     在做完原理图，DRC检查没有错误后，生成网表时，出现：
$ ]+ a) {  p! Z+ M% e+ V   #248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CEJMK212BJ106KD_T'.  Each section must have at least one non-common pin.
7 P5 o8 Z# i7 T  K; Z1 N  d/ x- L3 x        Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.
      我检查了原理图SYMBOL和PCB封装，也换另外的PCB封装试了试，错误依旧。
  大家帮我看看，是什么原因呀。
" a! O) C( ~- U1 |% m+ A    我在画原理图时还碰到其它的问题：
, g8 r- k5 u* ?/ O9 s9 k$ @      1：元件编号如电阻电容之后，总自动出现一个A或是B,  如：R120A
- T% u1 j( [& y8 g$ ]3 t1 ~; T1 s& ]0 E      2: 在COPY一个元件到另外一个地方去时，本应每COPY一次编号都自动增加，可现在是每COPY两次，编号才自动增加一次。
         为方便大家检查，我把生成网有的出错贴在下面了：
      ********************************************************************************
Design Name:
E:\Hi3515FJ_cadence\hi3515fj.dsn
Netlist Directory:
E:\HI3515FJ_CADENCE\NETLIST
5 ^1 G& N# n1 V" V+ k% o5 ZConfiguration File:
D:\Candence\SPB16.2\tools\capture\allegro.cfg
Spawning... "D:\Candence\SPB16.2\tools\capture\pstswp.exe" -pst -d "E:\Hi3515FJ_CADENCE\hi3515fj.dsn" -n "E:\HI3515FJ_CADENCE\NETLIST" -c "D:\Candence\SPB16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
& {0 M. z/ O) ]6 C" C4 X( M#1 Warning [ALG0016] Part Name "PHONE JACK-4_0_PHONEJACT_4_PHONE JACK-4" is renamed to "PHONE JACK-4_0_PHONEJACT_4_PHON".
#2 Warning [ALG0016] Part Name "SN74CBT16214_0_SOP56-20-250-550_SN74CBT16214C" is renamed to "SN74CBT16214_0_SOP56-20-250-550".
Scanning netlist files ...
" [; ]  G, y' Z: e  S4 VLoading... E:\HI3515FJ_CADENCE\NETLIST/pstchip.dat
& y5 Z5 t, l; n4 F$ J#248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CEJMK212BJ106KD_T'.  Each section must have at least one non-common pin.
        Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.
$ e! x5 {: X. f1 l              ERROR(SPCODD-47): File E:/HI3515FJ_CADENCE/NETLIST/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causing this situation and package the design again.
+ Q) z9 }+ i( x1 }0 O#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the schema
tic and rerun packaging.
0 r0 |- ?" ^5 b- W: E#3 Error   [ALG0036] Unable to read logical netlist data.
Exiting... "D:\Candence\SPB16.2\tools\capture\pstswp.exe" -pst -d "E:\Hi3515FJ_CADENCE\hi3515fj.dsn" -n "E:\HI3515FJ_CADENCE\NETLIST" -c "D:\Candence\SPB16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"

*** Done ***

rockyawei

定义其中的某个电源Pin类型为power就好了。

九零年代

Part Name "PHONE JACK-4_0_PHONEJACT_4_PHONE JACK-4" is renamed to "PHONE JACK-4_0_PHONEJACT_4_PHON".
: @& h( i2 A% f5 N7 B) G
# W4 \4 f: C. g请问这个问题该怎么解决？