Orcad capture生成网表时出错，大家帮我看看

lyf9908

大家好，以前用AD6,pads, 与在用SPB16.2,很不习惯呀。 & n# n- K' H' t) H5 f: c) d8 @& b     在做完原理图，DRC检查没有错误后，生成网表时，出现：    #248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CEJMK212BJ106KD_T'.  Each section must have at least one non-common pin. 0 t! p& e) s" l4 D- C8 u        Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.       我检查了原理图SYMBOL和PCB封装，也换另外的PCB封装试了试，错误依旧。   大家帮我看看，是什么原因呀。 $ e% U% |. g  Q) c1 k8 D7 F    我在画原理图时还碰到其它的问题：       1：元件编号如电阻电容之后，总自动出现一个A或是B,  如：R120A $ [& n0 b6 @$ c4 P% P      2: 在COPY一个元件到另外一个地方去时，本应每COPY一次编号都自动增加，可现在是每COPY两次，编号才自动增加一次。 $ A# y1 h0 s* f0 m; _; l     原理图工程我加在附件里了，大家可以打开F3文件帮我看看。      为方便大家检查，我把生成网有的出错贴在下面了： - \3 f* O6 q# R# l+ H: x# t      ******************************************************************************** Design Name: E:\Hi3515FJ_cadence\hi3515fj.dsn & u* E: Y( H" S5 _2 ?Netlist Directory: : s9 p, `, F4 y. X# qE:\HI3515FJ_CADENCE\NETLIST   h+ d. K; y+ |* T& ~: XConfiguration File:   j! @0 p: @9 N! I3 G" r% lD:\Candence\SPB16.2\tools\capture\allegro.cfg ! {+ P. o; i/ r% k+ \& ?" o% USpawning... "D:\Candence\SPB16.2\tools\capture\pstswp.exe" -pst -d "E:\Hi3515FJ_CADENCE\hi3515fj.dsn" -n "E:\HI3515FJ_CADENCE\NETLIST" -c "D:\Candence\SPB16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint" #1 Warning [ALG0016] Part Name "PHONE JACK-4_0_PHONEJACT_4_PHONE JACK-4" is renamed to "PHONE JACK-4_0_PHONEJACT_4_PHON". #2 Warning [ALG0016] Part Name "SN74CBT16214_0_SOP56-20-250-550_SN74CBT16214C" is renamed to "SN74CBT16214_0_SOP56-20-250-550". Scanning netlist files ... Loading... E:\HI3515FJ_CADENCE\NETLIST/pstchip.dat #248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CEJMK212BJ106KD_T'.  Each section must have at least one non-common pin.         Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.               ERROR(SPCODD-47): File E:/HI3515FJ_CADENCE/NETLIST/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causing this situation and package the design again. % P# i/ `5 \& C#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the schema tic and rerun packaging. * E+ M- I* E! `  ~  W2 G$ N* f  S#3 Error   [ALG0036] Unable to read logical netlist data. / S- F1 m+ ?7 f  ~% pExiting... "D:\Candence\SPB16.2\tools\capture\pstswp.exe" -pst -d "E:\Hi3515FJ_CADENCE\hi3515fj.dsn" -n "E:\HI3515FJ_CADENCE\NETLIST" -c "D:\Candence\SPB16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint" , ]3 w, Q) D) R; [ & ?% A5 `; _6 F$ C3 S1 t*** Done ***