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DATE: 07-24-2011 HOTFIX VERSION: 002
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CCRID PRODUCT PRODUCTLEVEL2 TITLE2 X8 y0 o" r4 R5 {4 i6 W$ x( d
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' u) |' G5 h" |5 E5 K& q$ T527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings
9 a+ {3 k' ]: S0 T$ `; Z5 W7 D583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.
0 v' Q- M. b7 n _592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.2 E6 m* t& ^6 _) F8 p( x
745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.
: o; }& c2 P4 f7 N+ I773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.- b1 f( G" B$ D2 Z) ^# G
774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.2 I% R2 P) h$ U; u' r
799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs: r0 H$ ^4 M/ S: C
809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".' x" |% _) f$ R- \! e$ M+ a
810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally"." c+ t n; `* c8 l( K
821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format- N- z4 q5 B! R; |: }* r$ X9 a9 w
831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself; T# V, ^2 \: k- O+ L
842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.8 J( T+ C4 E% E
854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group) N& t+ h; P8 x: ]/ a0 K" o' `5 S7 c
860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser3 z \- i6 B7 @" |' |8 c
867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"
; \' b8 S9 p* n ?/ b j868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets
2 p4 G: k. n3 L9 h6 ?" X. L882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE2 V5 v7 k( ~/ Z ]! a
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
u2 K4 w, M7 c8 }& O& R! K893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.! ?+ u' m2 U' x a& E) r
893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.
- d3 h5 C2 C" h1 @. H3 D2 }894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command: u/ J0 Y/ S& E" o) O. h- B; M# d
895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs' |7 I# Q) ?5 j: k
896598 ALLEGRO_EDITOR PLACEMENT error message is misleading% P! Y+ }" v: x! F ?4 O
897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library
! ~5 y/ V( V, c# F7 V* K+ e7 K0 ^898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated./ [' S7 r# o% K. \1 Z* n! c) W
899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.
/ ?9 k- Q9 P: C7 A; ]' q( \900501 ALLEGRO_EDITOR PLACEMENT "Place Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5* Z6 q0 ^( k( `& X$ g. y
901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.
, X' C% C2 d5 o7 `5 r, |901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page1 K/ n! @; F5 T( `6 R
902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains
6 y/ {( M3 i0 F, ]902349 CAPTURE LIBRARY Capture crashes while closing library
}7 e- a, S& v+ s+ k902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3
+ `7 @1 x. Z- r3 m- N902841 CAPTURE GENERAL Capture Start page does not show
/ b9 C6 ]& [) G0 c+ W902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5
7 T9 L1 ^" D( E7 f: Y902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design
/ j: v# P/ M& D903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?
; U4 \9 `" r2 ~# D8 c2 ?* `+ s7 k0 E903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition
; f) j( s0 o6 ]/ x903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor
7 ]$ b4 T' ^3 c" G: u6 [904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable$ G; o9 [$ f- h6 k' X6 _8 w
904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE
5 T# R& C) @# v+ W904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3
# q0 O$ T! j. A" x5 p904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places/ o; H4 {3 X/ t* d
904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.9 k+ i4 s9 l2 w" Z0 }4 L
904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.3* _: `. ~1 }8 t& h0 T7 F
905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM9 N& W g: V9 u) R. U) D! P
905314 F2B PACKAGERXL Import physical causes csb corruption
9 j; l. e' ?2 ` t$ ^- [905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.6 ?- g$ E: ^0 x1 g5 N
905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible
* S. e4 d, |3 J4 }905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues
& S6 ~+ E; F7 W8 {4 \905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid3 o A2 K) |: H' P0 ]0 H) f. B1 u
906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.
W4 O4 r4 ?/ L$ y8 i906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.
6 p4 J) |) P* M! c! f* u906182 APD EXPORT_DATA Modify Board Level Component Output format* [2 z& G6 n M# f8 p% Z
906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element6 G" T9 e, ]) m% t. C
906517 PSPICE PROBE PSpice new cursor window shows incorrect result.5 e+ D( o. T2 @3 A' Z# f4 u
906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.1 A- A z5 q0 r: s
906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run( ^& l: R4 C. @/ b! Y/ f+ |
906673 F2B PACKAGERXL Ignore the signal model validity check during packaging
$ h, q! ~$ n7 n0 T906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design', l# I+ C1 }" F* {6 ]# I
906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation) I H6 C+ ?6 T
906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin: Y2 V4 P3 F; Q+ V- G
907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used, E4 j; E% R; T, P( \+ B8 j G
907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display7 T8 x) Q6 \$ c
907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.
- x- n" n* g9 s907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"
h5 ~5 h: X- y) r9 W1 n( O907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31: c! R/ r) v0 }: S- e/ c- l5 q- W
907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly. S9 ]8 C& ]* v) n
907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional
! |+ r. n- y9 ^907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5
+ M+ p* r" a. w) s- Z+ C908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.
6 Q" Q; s/ q+ N s- m8 D, G$ k908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name& ~- P8 q( t+ G$ u
908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3
* i' ?. H5 Y+ n3 ]3 `908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component1 V- x* l: i5 {
908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.5
4 B$ d; A7 ]: H/ a6 o) ]1 t908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place# U' _2 u# J% D& @
908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays
( H4 t' `' l h% z908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes9 A" S, r9 d# a$ R! d4 X5 e, Y
908595 APD 3D_VIEWER Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b# P2 T0 h2 H' q0 J
908849 CAPTURE ANNOTATE Getting crash while annotating the attached design7 J( b/ f" S' p: g2 t9 u# h
908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature/ F% k) F% h+ Z7 s& q
909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN P" E3 w w2 A, s
909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.
* B0 b7 R1 G, {, G909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux
& R, g5 Z( R, Z( E/ k& W909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout
$ @9 z9 L8 A3 A3 J909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning
, B8 \/ i- S: y, q0 d& D9 n909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack
4 q1 |7 |& H) ]; F P1 U909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.0310 w3 F: k# d: i s
910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.
1 c4 K$ v& f7 B910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector! R& P7 v* j: }# r
910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.( v; L7 \+ b5 ?# l \5 P2 } B
910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5
/ |, g3 E3 [! m2 b, I910713 F2B DESIGNVARI Variant Editor crashes when you click web link under hysical Part Filter?window.
/ |. [* t+ k9 v& `* w7 u910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent
4 R3 N% a, ^8 U7 y0 \: H+ m. m( Q911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given
0 j9 ~* ~) [' L4 r911631 CONCEPT_HDL CORE DEHDL crashes when opening a design
' f' s; E, _( \( ^+ o- r912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default8 y0 [; B$ g$ H) `2 U, A1 H" ]
912459 F2B BOM BOMHDL crashes before getting to a menu, r, z1 b6 `3 s. T$ K7 U; x
913359 APD MANUFACTURING Package Report shows incorrect data x3 @# J3 F( O' K1 b
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发表于 2011-7-27 15:44
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发表于 2011-7-28 07:44
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