|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
最近在学习quartus ii 的ddr2的ip核，编写了一个程序，在程序中实例化了DDR2的ip和，想用modelsim仿真看看波形，仅仅是功能仿真（RTL仿真），但是仿真出现了很多一样的错误，如下，请问各位大神遇到过这种情况吗？是怎么解决的？
" r( V* o6 l9 w2 n; J* P9 G. Q* f+ i( C- W% v# b
# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2256): Module parameter 'CFG_MEM_IF_CS_WIDTH' not found for override.! r9 Y& Z- r, O1 e; l/ F
#
" r N0 }- v S/ ] m0 r" R# Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst
* n! o) @% U: w4 ~# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2256): Module parameter 'CFG_RANK_tiMER_OUTPUT_REG' not found for override.+ @! x4 {: S4 j& m2 E6 i( y
#
' b2 i7 V+ R: [4 [# Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst
- w. F5 T) P; A2 C7 i+ U# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2328): Module parameter 'CFG_RANK_TIMER_OUTPUT_REG' not found for override.6 }& Y. A7 v6 h, O
# ' \" t1 U5 z |: m+ @2 [
# Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst1 Z8 e: @. z0 I" D' e* d, q; P6 T
# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2508): Module parameter 'CFG_CTL_ARBITER_TYPE' not found for override.
( e# h5 l0 m4 \! k$ [2 U& l) ?# 6 B' v7 b" ~: b
# Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst
% C# b% i; X0 J* N- P! A# Loading a0.alt_mem_ddrx_mm_st_converter
6 C: }% y6 O D( s, t8 p( [. T# [# Loading oct0.altera_mem_if_oct_cyclonev
! v4 Q. k$ i( S# a# y; S3 K# Loading dll0.altera_mem_if_dll_cyclonev9 q1 \2 h2 Y8 J
# Error loading design& B" C1 w) J( _/ c% q, ~/ P8 U S
# Error: Error loading design . J& T1 B( `7 T+ }( O% i9 j J
# Pausing macro execution ' H4 A( u" U6 Y. W+ F, q9 U
# MACRO ./ddr2_ceshi_run_msim_rtl_verilog.do PAUSED at line 214, n) y( ^( ^2 J- U: b4 i
|
|
/1 
发表于 2021-11-26 15:48
收藏
淘帖
支持！
反对！