cadence allegro17.2 从原理图向PCB导出设计时（export physical），报错

lahhse

Error: Schematic supports automatically creating XNets using DML but the Layout will not automatically create any XNets. Change setting in Layout or Schematic, re-generate files, and re-run the flow.

zefengge12138

这个错误是指原理图中支持自动创建Xnets，但是PCB中不支持自动创建Xnets，所以更改PCB或者原理图的设置，然后再生成一遍网表。

理论的

Add the following to your <normally home folder>/PCBENV/ENV file:  set CDS_XNET_STATE_UI=1

" j) C9 c  B- ~Restart the tool and open Constraint Manager
9 }6 }  {6 B* ^5 `8 Y
In Constraint Manager, select Tools > Options and enable the option "Create XNets and Differential Pairs using DML Models "
  X- q8 c, J) q: }+ M/ t" `, c. t
' T; Z" w1 S2 ]* I! X' _/ DSave the design to a new name and try running the flow again.
2 z. \4 w" ?5 R# ~8 L$ x
  `' ^5 l$ G- |" I0 D9 CI intentionally stated to save the design to a new name so you have a back-up before making any changes running the flow. :-)

NOTE: If there are any XNets that are auto-generated in the design, without DML assignments, they will be removed after running the flow. (It sounds like you don't have any XNets anyway but I figured I would mention it)

芦根苏木

下一次再导线路会不会自己更改现有的constraint设置

rergr

想知道别人是怎么说的