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偶也跟一贴！
/ R6 n. ^9 j0 n6 h以下内容来自《high speed digital system design》。
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A via is a small hole drilled through a PCB that is used to make connections between various
, X& v# s- Q8 p$ Q% V) B; jlayers of the PCB or to connect components to traces. It consists of the barrel, the pad, and
7 P/ s1 I, D- c7 ethe antipad. The barrel is a conductive material that fills the hole to allow an electrical
4 k+ m! E' R0 u* v5 \8 `connection between layers, the pad is used to connect the barrel to the component or trace,6 L& r; i+ u' q5 K% A2 l
and the antipad is a clearance hole between the pad and the metal on a layer to which no% i/ q* P8 y: |7 Z$ b3 |8 ~
connection is required. The most common type of via is called a through-hole via because it# F& E. H- |4 c4 c
is made by drilling a hole through the board, filling it with solder, and making connections on7 T$ n7 v% I6 z s& {: L
appropriate layers via the pad. Other, less common types of vias, used primarily in multichip" f1 Z" u3 ~2 E
modules (MCMs) and advanced PCBs, are blind, buried, and micro-vias. Figure 5.1 depicts
0 r$ A, y4 T6 i1 X: t+ Da typical through-hole via and its equivalent circuit. Notice that the pads used to connect the) ^4 R. L) d9 J, _% z5 S& }" k) `- ^
traces on layers 1 and 2 make contact with the barrel and that there is no connection on
4 t8 ~( I+ g) }; P& Flayer 3. Blind and buried vias have a slightly different construction. Since through-hole vias0 U N+ a1 J% `& W8 F3 [# [% Y
are by far the most common used in industry, they are the focus of this discussion.
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Notice that the via model is simply a pi network. The capacitors represent the via pad
) v; M. s7 d: o: |1 Hcapacitance on layers 1 and 2. The series inductance represents the barrel. Since the via1 ~) |0 M5 V/ J2 _+ N; n
structures are so small, they can be modeled as lumped elements. This assumption, of1 ~2 B- C- j8 ?) f& Q
course, will break down when the delay of the via is larger than one-tenth of the edge rate.
/ @" g: j2 {+ g$ d6 D0 e! T6 \6 N4 fThe main effect that via capacitance has on a signal is that it will slow down the signal edge
/ v6 j5 n! B* Orate, especially after several transitions. The amount that the signal edge rate will be slowed- O+ k$ e2 X: H
can be estimated by examining the degradation of a signal transmitted through a capacitive
4 v- u3 F \2 H$ N! m) Dload, as shown later in this chapter in equation (5.21). Furthermore, if several consecutive: B+ b9 x2 ^' o7 I4 u
vias are placed in close proximity to one another, it will lower the effective characteristic5 K# x0 E* R8 Y8 J
impedance, as explained in Section 5.3.3. The approximate value of the pad capacitance is
, \. o$ G& l! V9 }7 X& P[Johnson and Graham, 1993]
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' Y; A1 W$ t% E1 Y" t+ Z7 O[ 本帖最后由 killerljj 于 2007-11-21 20:51 编辑 ] |
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发表于 2007-9-11 14:20
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支持！
反对！
发表于 2008-1-17 21:53
发表于 2007-9-15 15:34
俺也顶一下,因为焊盘描述的太形象啦!