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偶也跟一贴！: \$ S4 [( S& s) K, ?
以下内容来自《high speed digital system design》。
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2 G9 F' ~. @+ T0 P- d" `! n8 z( sA via is a small hole drilled through a PCB that is used to make connections between various- `7 A; ^, k/ u5 d X; k; ~
layers of the PCB or to connect components to traces. It consists of the barrel, the pad, and$ R9 B8 U, t8 | g$ G& W
the antipad. The barrel is a conductive material that fills the hole to allow an electrical) p0 d3 {) n. ]$ E
connection between layers, the pad is used to connect the barrel to the component or trace,* O) B! b$ S4 Q: L* j
and the antipad is a clearance hole between the pad and the metal on a layer to which no
% A$ M% ]) A- j, W9 e x* _1 dconnection is required. The most common type of via is called a through-hole via because it
- \" k% X J" R, P! {is made by drilling a hole through the board, filling it with solder, and making connections on
2 |+ s: S3 L9 V* P, ^appropriate layers via the pad. Other, less common types of vias, used primarily in multichip
/ ]' o; I) m' f& H4 A7 Emodules (MCMs) and advanced PCBs, are blind, buried, and micro-vias. Figure 5.1 depicts0 R5 R( }. U! |
a typical through-hole via and its equivalent circuit. Notice that the pads used to connect the
0 _& u, D( u$ e% B2 Mtraces on layers 1 and 2 make contact with the barrel and that there is no connection on! P( r5 |6 i! x; A1 r6 J
layer 3. Blind and buried vias have a slightly different construction. Since through-hole vias/ B! h2 U% J- V9 j6 S* h
are by far the most common used in industry, they are the focus of this discussion.
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Notice that the via model is simply a pi network. The capacitors represent the via pad! V% n' }9 d. R
capacitance on layers 1 and 2. The series inductance represents the barrel. Since the via
+ S( i* g8 S5 A% x9 `! o" k" V' ostructures are so small, they can be modeled as lumped elements. This assumption, of8 r" c- e. B" U* ]4 f6 @
course, will break down when the delay of the via is larger than one-tenth of the edge rate.
* x$ \ I4 s6 Q/ B6 f3 z$ Y' E+ KThe main effect that via capacitance has on a signal is that it will slow down the signal edge
7 p$ a6 o6 F! A0 ]9 i' O7 T+ |rate, especially after several transitions. The amount that the signal edge rate will be slowed2 \+ A4 Z! s: U4 y
can be estimated by examining the degradation of a signal transmitted through a capacitive q9 u$ \% j) y8 ^& h3 D
load, as shown later in this chapter in equation (5.21). Furthermore, if several consecutive
. ?9 s) P0 [1 l& uvias are placed in close proximity to one another, it will lower the effective characteristic9 D. ?) r$ n, V& N. m
impedance, as explained in Section 5.3.3. The approximate value of the pad capacitance is
2 m4 }; i! s( }[Johnson and Graham, 1993]
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[ 本帖最后由 killerljj 于 2007-11-21 20:51 编辑 ] |
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发表于 2007-9-11 14:20
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支持！
反对！
发表于 2008-1-17 21:53
发表于 2007-9-15 15:34
俺也顶一下,因为焊盘描述的太形象啦!