很诡异的问题，一个DRC警告，WARNING [DRC0004]

zju

WARNING [DRC0004]   Possible pin type conflict U1,IO_VB7N0_W15 Bidirectional Connected to Output Port:  FPGA, PAGE-A1DR FPGA END  (2.50, 5.30)

请看图

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zju

--------------------------------------------------
Checking Schematic: FPGA
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Checking Electrical Rules
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WARNING [DRC0004]   Possible pin type conflict U1,IO_VB6N1_V21 Bidirectional Connected to Output Port:  FPGA, PAGE-A1DR FPGA END  (4.90, 2.20)
WARNING [DRC0004]   Possible pin type conflict U1,IO_VB7N0_AA19 Bidirectional Connected to Output Port:  FPGA, PAGE-A1DR FPGA END  (5.00, 4.80)
WARNING [DRC0004]   Possible pin type conflictWARNING [DRC0004]   Possible pin type conflict U1,IO_VB7N0_W15 Bidirectional Connected to Output Port:  FPGA, PAGE-A1DR FPGA END  (2.50, 5.30)  U1,IO_VB7N0_Y14 Bidirectional Connected to Output Port:  FPGA, PAGE-A1:DDR FPGA END  (2.50, 5.50)
! n( `/ C( F. o# H) @; X5 B. QWARNING [DRC0004]   Possible pin type conflict U1,IO_VB6N1_V20 Bidirectional Connected to Output Port:  FPGA, PAGE-A1:DDR FPGA END  (4.90, 2.10)
WARNING [DRC0004]   Possible pin type conflict U1,IO_VB6N1_V22 Bidirectional Connected to Output Port:  FPGA, PAGE-A1:DDR FPGA END  (4.90, 2.30)
- [' F. ?% g( `WARNING [DRC0004]   Possible pin type conflict U1,IO_VB6N1_W22 Bidirectional Connected to Output Port:  FPGA, PAGE-A1:DDR FPGA END  (4.90, 2.70)
0 R- H9 g+ H: K- o" j" C/ `WARNING [DRC0004]   Possible pin type conflict U1,IO_VB7N0_W16 Bidirectional Connected to Output Port:  FPGA, PAGE-A1:DDR FPGA END  (2.50, 5.40)
9 k2 |, B/ Y" }# L! h0 n: ^WARNING [DRC0004]   Possible pin type conflict U1,IO_VB7N0_AB18 Bidirectional Connected to Output Port:  FPGA, PAGE-A1:DDR FPGA END  (5.00, 5.60)
- ~8 J# k$ b1 R/ eWARNING [DRC0004]   Possible pin type conflict U1,IO_VB7N0_Y17 Bidirectional Connected to Output Port:  FPGA, PAGE-A1:DDR FPGA END  (2.50, 5.60)
WARNING [DRC0004]   Possible pin type conflict U1,IO_VB6N1_Y21 Bidirectional Connected to Output Port:  FPGA, PAGE-A1:DDR FPGA END  (4.90, 3.10)
WARNING [DRC0004]   Possible pin type conflict U1,IO_VB6N1_Y22 Bidirectional Connected to Output Port:  FPGA, PAGE-A1:DDR FPGA END  (4.90, 3.20)
WARNING [DRC0004]   Possible pin type conflict U1,IO_VB7N0_AA18 Bidirectional Connected to Output Port:  FPGA, PAGE-A1:DDR FPGA END  (5.00, 4.70)
WARNING [DRC0004]   Possible pin type conflict U1,IO_VB6N1_W21 Bidirectional Connected to Output Port:  FPGA, PAGE-A1:DDR FPGA END  (4.90, 2.60)
' Z* F3 j" K$ Q, |& X: s6 gWARNING [DRC0004]   Possible pin type conflict U1,IO_VB7N0_AB19 Bidirectional Connected to Output Port:  FPGA, PAGE-A1:DDR FPGA END  (5.00, 5.70)
WARNING [DRC0004]   Possible pin type conflict U1,IO_VB6N1_R17 Bidirectional Connected to Output Port:  FPGA, PAGE-A1:DDR FPGA END  (4.90, 1.70)

jacklee_47pn

這個很正常啊，例如有些芯片的管腳在手冊上說是 Bidirectional，可是它有很多模式可以選擇，好比說 GPIO INPUT、GPIO OUTPUT、UART TX，這時候你在ORCAD建立元件庫的時候，你可能選擇 Bidirectional ，可是實際上你可能是一個 GPIO INPUT PIN，所以會接某元件的 OUTPUT PIN，所以 ORCAD 會提醒你 Bidirectional Connected to Output Port。
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所以在件元件庫的時候，要慎選 PIN TYPE。另外一個方法是去修改， ERC Matrix 的規則，只怕 98%Bidirectional Connected to Output Port 是沒關係的，其他 2% 是真正有問題，如果沒仔細看，有時候會很淒慘的啦~~~~~~

zju

仔细看，我试着把那个PIN 没连接到任何网络，都会出现那个警告。。。
3 U+ z* n  k  M, X. j, C! ?& v7 Y百思不得其解啊

zju

解决问题，把PORT 改成off-page 就OK
虽然逻辑上说不清楚。。。

jacklee_47pn

怎會說不清楚。請看別人的帖子 https://www.eda365.com/thread-9218-1-1.html
帖子還是放在 [推薦主題] ，非常醒目呢。

zju

我的port确信属性没问题的~~所以说不清楚嘛