Hotfix_$PB16.50.013

yulizi

9 E! _; r1 j  g  y2 o% ~http://kuai.xunlei.com/d/DGOHIFKLICUP

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; [- \; F, x2 ~+ [+ K% JDATE: 12-16-2011   HOTFIX VERSION: 013
===================================================================================================================================
6 g+ Q: _# ]: @& z% c" }; d& G! f# ?CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
- I' H$ X' \. B* Z- v===================================================================================================================================
5 E4 H4 J  z3 W% m875695  SIG_EXPLORER   INTERACTIV       Enforce Causality check box doesn't work.
927148  CAPTURE        PROJECT_MANAGER  Capture crashes on creating scehmatic folder with name which already exists in design
938013  CAPTURE        NETLIST_OTHER    The netlist in RINF Format contained two identical lines for PCB FOOTPRINT
4 I  B/ t0 ~2 o, E941409  Pspice         PROBE            BUG : Search accuracy wrong in new cursor window
* w' B3 _3 \/ S7 e- R945242  SIG_INTEGRITY  SIMULATION       Unable to select "shapes" in find filter for 'show parasitic ' command
946293  concept_HDL    ARCHIVER         Archiver hangs if there is a whitespace at the end of the path of cref.dat
( u2 A  }1 Q9 i, y946770  CONCEPT_HDL    CORE             揤iew Design?function is missing in Windows Mode after reseting the menus.
950994  CAPTURE        NETGROUPS        Problem in expanding the netgroup in Auto Connect to Bus function
953530  SIG_INTEGRITY  GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
953713  CONCEPT_HDL    PAGE_MGMT        Random page replacement/duplication in block
953917  CONCEPT_HDL    ARCHIVER         archcore should handle errors correctly
953971  allegro_EDITOR MANUFACT         NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes?
$ F( u- s+ U2 G& \$ S; a954400  CAPTURE        NETGROUPS        BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.
954498  SCM            B2F              SCM crashes when importing physical
, m1 v7 p  i  ]5 Z7 F) W: k954623  ALLEGRO_EDITOR EDIT_ETCH        Unable to complete connection with Add Connect - related to soldermask to cline check?
4 k6 N- R1 T( K5 w$ J7 e954894  ALLEGRO_EDITOR MANUFACT         Dimensions disappear when opening database in v16.5 from v16.3
" k8 R4 A6 t9 |- e; P955029  CONCEPT_HDL    CORE             custom text font size not recognized in symbol view
955133  SIG_INTEGRITY  FIELD_SOLVERS    The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.
' y; A) V- |- ]! S; I9 A, c955290  CAPTURE        DRC              Description for UPD0014 missing in the Browse DRC markers window
955299  ALLEGRO_EDITOR DRC_CONSTR       drc text to smd pin does not work any more on this database in 16.3 S039
955338  CONCEPT_HDL    CHECKPLUS        Need to change PART_NAME
955447  SIG_EXPLORER   OTHER            Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL
4 x# L, ~4 r2 f+ m4 G955740  SIG_INTEGRITY  GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
% y5 ^' A, O- c) I955749  ALLEGRO_EDITOR MANUFACT         show element Info shows symbol dimensions on incorrect subclass
955912  ALLEGRO_EDITOR OTHER            Shapes with voids that are exported to PDF have gray filled area over the void
' w; z5 F5 J" P+ n- \1 @/ R) k3 f" w956129  CONCEPT_HDL    INFRA            DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.
956373  ALLEGRO_EDITOR NC               drawing name doesn't display in the log file
956393  CAPTURE        PROJECT_MANAGER  "GENERAL" and "TYPE" tabs are missing from "Properties" dialogue box.
956448  PSPICE         MODELEDITOR      Can not generate a DEHDL symbol from Model Editor, because no Capture license found
956456  CAPTURE        NETLIST_OTHER    OrTelesis netlist not transferring user properties defined under combined
956489  ALLEGRO_EDITOR MANUFACT         dimensions lost when symbol with diemnsions attached to symbol origin placed on board
2 K6 X$ y  \7 d956603  CONCEPT_HDL    OTHER            Part Manager "has stopped working" after changing a component
' C5 m% c" J8 o: j956751  ALLEGRO_EDITOR ARTWORK          Import Gerber command does not work correctly
# P) n6 R# Y4 T. f" M) l956847  PCB_LIBRARIAN  METADATA         PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
956987  CAPTURE        OTHER            Find from "Search toolbar" doesn't gives complete results
) N% p9 p  c& Y1 B  Q956996  CONCEPT_HDL    INFRA            Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
1 i, p. k1 k/ U! u0 }' c957009  CAPTURE        NETLIST_OTHER    Problem getting database property in mentor pads PCB netlist
957137  APD            DXF_IF           DXF out  command dose not work correctly.
957167  APD            GRAPHICS         Highlighting for Static shape with display_nohilitefont environment variable.
957232  SIG_INTEGRITY  OTHER            Allegro crash during Model Assignment.
# @0 k7 U! d9 ^" g8 f3 [957267  CONCEPT_HDL    INFRA            Packager Error after Import Design
957866  SIP_LAYOUT     DATABASE         Cavity outline is not getting deleted from symbol file
% h8 s. _8 m/ ^+ [8 w958010  ALLEGRO_EDITOR REPORTS          Wants the ability to extract "Batch"  reports from Partition ".dpf" files.
958252  ALLEGRO_EDITOR TESTPREP         Resequence testprep with the option - Delete probes too close crashes the design
: B, v; `, x; A* r2 g1 z958253  ALLEGRO_EDITOR REPORTS          Shape did not have thermal relief connected to pin but unrouted nets still shows zero.
' o% {- F/ m" e+ a4 r" z  C" E958433  ALLEGRO_EDITOR DRC_CONSTR       False embedded component DRCs
6 O$ ^# m) ?; d; i/ r+ s958753  ALLEGRO_EDITOR SHAPE            Dynamic shape is getting corrupted in 16.5
959011  ALLEGRO_EDITOR OTHER            copy problem of via and cline
; f  _/ S& D) @) }, r959101  ALLEGRO_EDITOR EXTRACT          Using extracta with excluding Thermal reliefs
; `% s1 q) d/ z. d+ v1 P) v959253  CONCEPT_HDL    INFRA            Design will not open
959299  APD            MODULES          Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side
8 O2 r5 {" D' |6 e* N+ a# z: k959884  CONCEPT_HDL    INFRA            Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.
959909  ALLEGRO_EDITOR SCHEM_FTB        Site level propflow.txt file is ignored property is transferred
960067  SIP_LAYOUT     PLATING_BAR      Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.
$ M4 O6 m) o5 d960126  SIG_EXPLORER   EXTRACTTOP       Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.
5 F# S) o' u, i( m8 n/ P, z960143  SIG_INTEGRITY  GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter
/ \9 [9 i4 Y8 V7 T# Y9 l961349  CONCEPT_HDL    HDLDIRECT        Motorola designs have broken connectivity compared to 16.3
961816  ALLEGRO_EDITOR INTERFACES       Normal Export > DXF fails and offsets  the pins of the BGA symbol
962519  SIP_LAYOUT     WIREBOND         Align option doesn't work for wb_tackpoint fingers

nbhand

s013，感谢楼主分享。

pmp_mcu

多谢分享。。。。。。。。。。。。。。。

bazhonglei

顶！！！！！谢谢分享！

fangqwas

谢谢分享

ZXCLH

15没装成功过,但还是谢谢你...
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cotterie

非常感谢楼主yulizi 的无私奉献，有了你这个论坛充满了生机和希望。

koncc

感謝分享{:soso_e100:}

reval

都更新些什么呢？？

luluman

大神啊，顶
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john22ppo

; [# ~, j0 |# _感謝分享

interrupt

说什么好呢

suiwinder

楼主好人啊.
5 f; q4 ~  S3 e0 r" p( l6 W太感谢了.
现在这cadence也太差了把

adolfchen

感謝分享{:soso_e179:}

mengshang

太感谢您了