|
|
9 U$ Z% e+ }: T
DATE: 12-8-2011 HOTFIX VERSION: 041
: g( B/ v! L& G+ a7 n8 L===================================================================================================================================
' [0 f+ ]7 l/ mCCRID PRODUCT PRODUCTLEVEL2 TITLE5 F: F" g9 S( i# l$ w
===================================================================================================================================
8 T: B5 g5 w" ~4 z5 j875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.
' K& @9 ?* p- q944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently6 @3 x+ n% J* ~( t
946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat& _* ^* B" O+ [0 m) u
951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original }% ?/ V7 u5 ]
952057 SCM PACKAGER Export Physical does not works correctly from SCM& e! q! `/ s5 r+ h9 ?' s0 M5 d
953018 APD REPORTS Shape affects Package Report result.
2 \( o: ~) J( M1 |: X- X953279 SIG_INTEGRITY LIBRARY mkdeviceindex is adding dml file listing in env file
% {# Z+ T+ J; |953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro5 T" b& u0 r( f \
953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly6 g1 e8 Y" t2 Q1 c; z% _
953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "“separate files for plated/nonplatedholes”! X, }( j0 O: q4 W8 e6 I4 x( w8 Q$ K
954055 CONCEPT_HDL CREFER Crefer fails with UNC install path, ~+ G+ g* E/ ?3 b
954858 CAPTURE LIBRARY_EDITOR Closed polyline used in pin shape is not appearing while using custom pin in part.; E, A; h1 L' X2 F+ [; e8 C9 u N6 R
955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view
# K2 i/ }! V$ K955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.. V0 n1 x5 g! w. G$ H
955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039
& }& ^ r% u1 ?0 r0 u$ j955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME
0 p' E) C& ?" A1 P* H" o2 V# s956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly
, f6 \3 C/ v( d' W7 O" j958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design3 {% W- {' S9 ]
958945 CONCEPT_HDL CHECKPLUS Checkplus from 16.3 is not running with our "Allegro Design Entry HDL XL (16.5 licenses)
9 x. j+ Y- h7 d. b8 D+ @4 a1 j) B, c+ E) I
DATE: 10-21-2011 HOTFIX VERSION: 040
2 E/ S3 t: }2 C; A: x, E===================================================================================================================================6 f |. z( Z6 H) V+ c! V r
CCRID PRODUCT PRODUCTLEVEL2 TITLE0 h5 q+ w/ R/ A E1 m5 S* n; h
=================================================================================================================================== Q3 j/ [ n7 l
735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape! R) w2 D! B$ C0 K2 ~8 X5 K! t5 f
935438 CONCEPT_HDL COPY_PROJECT Copy Project changes read-only hierarchical block permissions
! ~, F0 J* H% d- R& K/ n935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic
/ [' D6 C0 z/ Q' D# c937165 SCM SCHGEN Can't generate Schematic
2 Z/ y* P) S/ K: _ A941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!
& v2 S {" ?, J# H- q6 g; \* z" f" R941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen
2 h6 { w: {$ ^0 f942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel- J4 I2 s4 U( c! I
943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.5 m+ v8 l' ]: o1 J: g b
946350 F2B DESIGNVARI Variant Editor rename function removes all components
' a. m' w, D# C( b& y0 F% ?4 l946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form u& q8 d: G" a- p5 x
947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.2 t4 Q: l+ X6 Z( ^) x3 N
5 r4 k6 I* M0 h1 W+ A. r% f
DATE: 10-6-2011 HOTFIX VERSION: 0395 s" [* k! N$ [2 t5 ?# l, q$ j6 S, J
===================================================================================================================================
9 i" n) `. |- m! \# ^ ACCRID PRODUCT PRODUCTLEVEL2 TITLE
9 z7 u3 p% z; |% D+ q4 r5 _/ ^===================================================================================================================================
2 h9 N5 ?. V& \3 n; K! i841096 APD WIREBOND Function required which to check wire not in die pad center.
& X, S; b$ H! ^5 v5 ?$ @; W, c, {! m912942 APD WIREBOND constraint driven wire bonding" L a5 j) x i" z7 u) x
917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors
' H/ R3 Z. V3 E. e, [. k( G' J/ }& M923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure( V) ?8 R" U( p% }; w1 X
927950 APD DATABASE My customer name their layout cross section subclass name as “wire” in Die type./ `! e/ c0 C3 t% o8 d" E
929348 F2B BOM Warning 007: Invalid output file path name
L7 k8 D6 J, n. V# |930783 CONCEPT_HDL CORE Painting with groups with default colors
, \ x' k& c y m932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property
" x: v/ O; t( H8 x0 K932871 APD GRAPHICS could not see cursor as infinite
3 Q% F, \8 C) R' c0 Z, f$ K! A933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.
2 G5 s$ d6 ~$ z( h. j# L933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass
m4 f8 V& Q7 y# q! \( J# r934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values
' k5 Y6 Y v4 l9 E- D" Z! _' o934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
8 J2 k' W4 z1 \6 D) i8 N935911 CONCEPT_HDL CONSTRAINT_MGR Mapping of constraints fails after importing layout constraints
, S% @, S8 W, q936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.. p: y; i/ A" D. ~2 W
936794 CONCEPT_HDL CORE Unable to select Allegro Design Entry HDL XL, g8 Y! ^) _5 z% i% t. e
937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE" a) l7 c& U: r! f
937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About
& \6 F; q9 u6 B* [1 N5 X937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.
: O( Z; L1 ~7 b; V937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.
8 t' e, A9 i1 l: b; Z# y5 `; g938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR/ g. O6 ?( b8 C F- f' ?
938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins D3 G- }8 v" }" S D2 O1 l X
939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.0 x4 s9 Z( N' }& m
940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part' L8 ~0 b# w i3 L2 U0 V
1 A7 c7 T9 z- ^+ @% v2 l- `) h
DATE: 09-21-2011 HOTFIX VERSION: 038, L+ L, `0 q: V- o: S* t
===================================================================================================================================
! u$ r) e7 I. s' Z( ICCRID PRODUCT PRODUCTLEVEL2 TITLE
# u- W5 G. q8 N0 h' Q! G===================================================================================================================================
1 m' b2 |5 {+ P6 ]) O: K R! Z924448 F2B DESIGNVARI Design does not complete variant annotation. x, e: `" K* p4 k# i y- w: B, x
927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values+ \8 I( D5 X9 t6 u8 h% }
928738 PSPICE PROBE Y-axis grid settings for multiple plots
" J+ O9 e% f* x1 [& ?1 B4 {! B929284 CONCEPT_HDL ARCHIVER archive does not create a zip file. z3 [! Q0 ~7 i4 Y6 i
930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape% t N2 ~" f! b" |* J# K0 q& b
930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation
4 P, N7 \, J9 U3 z9 o930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command
0 k) _0 Y. C& o+ d930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name
6 g- [ y& h; z0 [$ [" d2 k* |$ P% \' {930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens
- L ]" Z" @$ b, J) w931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.4 ~; D+ m j2 k4 K: {/ Z& k
931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.
! m9 N5 T6 l( ?932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.
3 a0 P) C% d2 U2 o4 x" }5 u4 \9 h933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown! E; E& I A+ n1 `- E1 K4 Q) s: I
/ o7 A5 n6 `1 ^! Q3 {DATE: 09-9-2011 HOTFIX VERSION: 037
1 s1 z& W, y/ K! R===================================================================================================================================
- M, o7 U, c$ V# _7 E' \1 r Y; JCCRID PRODUCT PRODUCTLEVEL2 TITLE' O0 q" q, }# e$ }& E2 V( d4 V/ H
===================================================================================================================================
, n% z. s1 ?& B) V/ F& T734687 PCB_LIBRARIAN IMPORT_CSV PDV Generation of entity view fails after CSV Import
# A& |8 z+ D2 L' y734718 PCB_LIBRARIAN IMPORT_CSV PDV Import CSV corrupts parts and generates duplicate $PN on some pins5 Z( R9 F. w. ]5 k1 N, C9 ?, S
820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.
. z" Y- X% s- ^5 Q# q* b868712 SCM UI Why can't I modify CAP associated component?
$ f. E2 }% w5 z3 f, P920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.
4 h* H) B" |# C8 p9 k- c922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.% t: r8 h7 \8 l! r
925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way
; C! d6 o. R- E: W& F; F925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?4 u& n& s- J6 j
925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data! v8 ?+ c) }( \" i* _
926503 CAPTURE GENERAL Memory leak Capture/Pspice0 M: {7 T6 m r% g
926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical, ]* C8 Y; i- i" y H6 o
927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.
# G) f6 N1 M8 `6 G$ X928286 CONSTRAINT_MGR INTERACTIV The value of pin-dealy has gone with long match group name.* b! ?- h/ \/ S: z; a
928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list
6 x* k8 X. f8 z8 B4 o8 }929174 ALLEGRO_EDITOR OTHER Display mesure get different result between 16.5 and 16.3
4 k% j1 }, ~5 n" H8 P t6 k( h/ W929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error _2 w9 [& }8 X* |
; F' L: p$ c) r/ _% t! B6 h: G7 X1 QDATE: 08-26-2011 HOTFIX VERSION: 036# _0 r8 H! _- r6 V& p' n. \2 B
===================================================================================================================================
5 b" f8 U3 ^4 D1 b- qCCRID PRODUCT PRODUCTLEVEL2 TITLE
$ p. `, a( j% x: R" J===================================================================================================================================( d* y1 \& @& l' `/ N
891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode( Y ?- z- M7 z8 E4 `
909595 APD LOGIC Inconsistency between export die text out and show element after pin swap' [9 \& |1 ]7 W& d
914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity1 Q0 i2 c" d% ?
916321 CAPTURE GEN_BOM letter limitation in include file
0 m& p9 C* H, k( r) d: N( C917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.
3 \* m: W) B, n919976 APD DATABASE Update Padstack to design crashed APD.6 X8 Y% z; W3 i) Y: @/ }6 o1 l
922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all
) ^! l" J s4 N923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.8 S9 @+ `, `3 J( }9 w% |
924458 SCM OTHER Project > Export > Schematics crashes, l# l# f+ q& Y
924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth. K( i. Y) f$ p1 H
925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect
) j1 M0 l. P8 c926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.( [( C1 |- [6 b7 F
) C6 C* B4 ?$ S( J" j( ^. aDATE: 08-12-2011 HOTFIX VERSION: 035
! o. N3 C6 B) R) V: V% A; J% X g3 n===================================================================================================================================
/ w& x- q5 q( e3 [CCRID PRODUCT PRODUCTLEVEL2 TITLE) L- i: ^; ]/ b! j' ^7 J
===================================================================================================================================
9 Y* \8 c0 @' L' D& O861956 CAPTURE IMPORT/EXPORT V16.3 is not respecting if the net names were written in LOWER CASE or UPPER CASE in EXPORT FPGA.
+ d; d# ~3 P4 |) s1 A+ v868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments' a0 l$ I0 n3 y3 ]5 X
870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file
3 j# v* p" R% N" L# A874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.( i( ^, U% ]% x# u1 w' ?
882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.
5 d/ u+ A$ j* f6 A# C5 S4 M895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1' I1 A% s+ f1 u8 }3 C1 R
895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement
. O( |$ S C: E+ w( c* J3 L% P) E' r0 m903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.3 W- `! d. |- K6 `% F: l$ p
905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible6 {9 t9 j5 o9 h9 W1 k$ p6 m
905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.8 x0 b/ W6 M1 T
905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged0 r: {3 ~: |+ j/ ` V2 j
915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models
4 j/ r* f. n0 O L! y3 D' M' n915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP
# X0 s4 s2 d* W916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor0 G6 D5 f! j H( A X( F
916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer
) { \# ?5 t! o Z( v/ K917434 APD OTHER Stream out GDSII has more pads in output data.; q# p$ n& o( k* m- g, ]" C
918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.! n+ v# I. c% m' ?6 I! `
918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol8 Q! B! f& Z7 _0 R5 |! M2 e
919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file' w3 c; J5 A; r' B; @3 ^ C
919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working
7 l& x4 W( i7 a7 A, ]. o920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork9 I2 g0 @! H! {/ _- D
" T7 z3 {) V$ D# [ x* s; m* v* TDATE: 07-29-2011 HOTFIX VERSION: 034
) b2 y, U# a. Q" m& B. J===================================================================================================================================5 p5 }, C; H0 D% i8 m/ z
CCRID PRODUCT PRODUCTLEVEL2 TITLE, v8 { N+ f+ V3 Z) ?
===================================================================================================================================
) ~' u, p" W! b! e882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE
1 B/ o- u/ ]: R0 d6 T897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library. `- o" e( O e" V
902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains$ V7 r" e' Y: D# F* O q% C
903719 ALLEGRO_EDITOR INTERACTIV Nets highlighted by netclass cannot be selected on the canvas to dehilight, g6 ?( d' q: e, n
903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics
, `4 O% ?4 Y% C7 ]. _5 h904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.
8 J3 t% N" |- I6 k. i0 D, [905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues
( q8 A$ e3 |9 [6 R6 j5 [907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF311 k, I$ j$ N B+ v/ v
908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name
8 x* d& V4 D( B0 q" P7 X9 a( ?908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3
/ T- X, C: U/ ~" \, o9 j& j908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance
- C5 p2 O6 m) X908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature7 B; ^" J u2 E7 v3 O3 x
909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout" ~7 Z2 b$ I v2 C# Q( Y5 n
910713 F2B DESIGNVARI Variant Editor crashes when you click web link under “ hysical Part Filter” window.0 d2 V, `& M% R& P4 \. |
910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent/ K$ N2 t2 E- d5 f; k' r
911415 ALLEGRO_EDITOR COLOR assigned color cannot be removed) b4 \/ i3 ~( u d
912343 APD OTHER APD crash on trying to modify the padstack
$ T c- t! G- L9 h) @& `912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys
' ?2 |4 d7 k B0 z7 I912459 F2B BOM BOMHDL crashes before getting to a menu$ {" s6 K. t; y
912853 APD OTHER Fillets lost when open in 16.3.5 X x6 L% x `) d
913359 APD MANUFACTURING Package Report shows incorrect data1 W4 a3 R( F0 i' F a6 C% {
913521 ALLEGRO_EDITOR SCHEM_FTB Netrev error “(40) Object not found in database” for a part which is packaged correctly in FE
: Z+ p0 Q e3 T! U/ S5 Q1 k913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.
9 i: Q6 {0 S9 Z7 M5 H! M1 d914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.
6 B: P( @' j, _, R914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape _* B6 I5 S7 L$ Z7 P/ K3 \; W) k
915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol
* }# I {- |# m, Z916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report
( ]4 i+ m6 b5 J- k2 s0 G2 x2 O( j3 K, D
DATE: 07-15-2011 HOTFIX VERSION: 033# s) ~/ R# K0 o
===================================================================================================================================, [# \* S& |* u+ u
CCRID PRODUCT PRODUCTLEVEL2 TITLE
2 T+ Z V$ c; r* C5 J! J8 J; O===================================================================================================================================6 Z T+ |8 T. O4 M: t
746562 CONCEPT_HDL CORE Deleting attribute causes other property value to move/change4 Z0 R, L, \, }: o
902349 CAPTURE LIBRARY Capture crashes while closing library$ i! t$ c" z+ f; o
903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?6 G, M1 m8 I2 N
903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition% r7 \; a4 b8 ?
905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.: d/ R6 J6 L! m8 U# |, D/ u
906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.
4 }/ `$ J6 K% D906517 PSPICE PROBE PSpice new cursor window shows incorrect result.& f X+ J' b* m3 V3 A: f
906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.8 t; x: J I B3 K1 H& n
906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation) O& k) b4 _) R/ N4 p9 n. J0 l t
906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin
! [1 n2 V- d: X( s" U2 s, R907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used
& U5 H9 x* j/ w' W3 j908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.
' Y3 C4 j& U) q$ j h908595 APD 3D_VIEWER Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b3 Z! Y& d$ w D! G
908849 CAPTURE ANNOTATE Getting crash while annotating the attached design+ W# a7 z$ l; T4 Q3 p0 `* q
909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack4 l5 @* P8 O0 t; l6 h
909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031
( O# f1 G1 X/ Q3 c/ n) X4 k! m+ I9 m! c' ?4 \0 Q4 o
DATE: 06-22-2011 HOTFIX VERSION: 032
3 \ R6 Q7 M. z===================================================================================================================================
4 e- g" I0 ^5 V: i1 t9 xCCRID PRODUCT PRODUCTLEVEL2 TITLE1 t" j3 u3 W/ S3 Z3 q- v
===================================================================================================================================
! @6 P4 H5 E& y774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.
6 Z3 P1 c( L2 N! G9 s2 j833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL
; ?2 M1 @. l. H/ f* Y* E5 y893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias./ r, n8 v. T$ n7 O6 e
893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.' M0 {$ h7 j& J3 o0 a/ c* |
895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs
% W7 L- S% E5 ?/ l% u/ D; Z897484 SCM CONSTRAINT_MGR No match found for 'fileops.txt' in the search path
$ m* r( g! b- t& I. R! ]1 L! u L899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.
& C) ^# Z, @1 S& e; O4 H902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design# A" N- Y) z2 ]3 y ~
903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement., v" i- K7 l$ `% b& P: A; r0 l
904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module
/ b& I. j/ C' e8 `; \# u904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.
0 Z4 _/ B. C+ ` T905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM
# {9 q; x& [- l0 u( y+ A/ ]* h905273 ALLEGRO_EDITOR MANUFACT Drill legend creates more tables than nclegend creates tapes, L. u. }1 O7 V' v% s7 ~
905314 F2B PACKAGERXL Import physical causes csb corruption9 O! G6 p& O. J# ~! h" V, }% T
* s+ F+ k: A9 V: ]DATE: 05-28-2011 HOTFIX VERSION: 031
; A1 |# _. I6 I) o3 M===================================================================================================================================# J/ h6 Z' Y0 w5 p8 f% l% K3 j
CCRID PRODUCT PRODUCTLEVEL2 TITLE
- b0 B8 T: X) `# e4 m===================================================================================================================================; c v* u3 _8 ]: L% ` s- H3 z
606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart
8 i% r8 T# M, ^, j644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor) Y! g- W* r4 ?4 b9 s
799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write/ ?1 h i2 |: D2 e! h
866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line8 s( ^0 N- E. R+ e) Y4 n
866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF/ l& d, J7 {4 e* i6 i
868618 SCM IMPORTS Block re-import does not update the docsch and sch view
1 l3 W7 H3 [) e869971 SCM OTHER Lower level hierarchical block schematics missing $LOCATION values
7 u7 Y5 r8 p+ A6 ?7 v% a0 B7 ]$ E877091 CAPTURE SCHEMATICS DSN file size becomes very large after placing picture and not change after deleting it
9 O6 m: e; a1 B- ?, {/ R! z879361 SCM UI SCM crashes when opening project% j4 \+ a6 O) V- F3 a
879496 CONCEPT_HDL OTHER Customer wants to have “the tabulation” key as separator in HDL BOM.% Y1 e ?- o5 L% V+ e7 n' D2 V
883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder
6 n$ F, [. R4 w/ b* k885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.
7 g6 f2 v8 M8 K9 c& H" T886007 CONCEPT_HDL CORE All the read only pages are called PAGE1 in our hierarchical design
: ^8 a9 F& _% A8 u* T889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net
$ G: U, \ @; g; M" U- T! p5 }892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.
0 j6 P: h a7 F9 F+ h" [892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness
/ X8 J, o+ v* N0 t2 C. Z0 e! v893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.
# _" ?5 p- r2 U5 V9 u7 X+ T894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.
e; [& C W: Y894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.8 N3 d3 I% e0 Y' w, n' q- j
895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON
6 [$ F# r( ^2 i! k) f7 e0 a895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers
G! l4 {; ?& o7 y+ w+ Y" M' m895757 APD ARTWORK Import Gerber command could not be imported Gerber data
( T1 g/ J f, Z( Y2 c895964 CONCEPT_HDL CHECKPLUS The CheckPlus command “getFileSubstrings” is not working correctly
8 [' r2 G- A0 [, K896302 CAPTURE LIBRARY Pin spacing option in Generate Part from spreadsheet
) a: d) T) n1 ?$ A& ]8 k% P7 A896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced5 J* y) X; A: w7 y+ I
897362 CONSTRAINT_MGR TDD Unable to create Region Class in Constraint Manager
5 p- X6 }( r. D1 u* L# v. V% x897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.& ?3 E% ^9 A+ H% j; p
898941 ALLEGRO_EDITOR REFRESH update symbol moves refdes location of component placed on bottom side! ~' V& ~. I% M+ ?4 N# n+ D
899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing
8 U! R% ~! k5 }: q% E& r( T+ e900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.
* v" M0 Z' Q% V3 H# z& I! K900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration G8 D% t0 t$ D1 m6 j( q* J( G
900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.
- @8 o6 T) K8 N. L4 D3 r: g' j- x900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.6 w) v6 v7 }- D$ C3 k+ F. Z
901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong
9 l; o6 e2 |9 b! _4 u |902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic; R7 H3 M6 l' F* p- y/ B3 w& }% ]" Y
902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file0 t. k- {1 f0 U& ]. q
902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization
j3 `: i: e2 `8 { P4 Q7 b902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components6 Q N2 k8 k- H* a$ k" a" Z
902909 APD WIREBOND die to die wirebond crash
" C8 z4 L, O& Z902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body
. u: B+ }% f6 S- M& I; m( @
( f, x* R8 v2 r9 A4 b1 JDATE: 05-14-2011 HOTFIX VERSION: 030 R$ p/ f6 L7 S/ q) L. _5 ?/ P3 Z+ \
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CCRID PRODUCT PRODUCTLEVEL2 TITLE$ v- V) Y! b" }! a$ H+ A
===================================================================================================================================
, m; x2 A3 ]1 O% F" {5 _" S738247 CONCEPT_HDL HDLDIRECT Generate View hangs
; m- V0 O/ ^6 L+ w803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part- D% y h. V% c) Y* q% d
837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version4 {+ b: o4 U9 b n# z
838763 CAPTURE GENERAL Deadlock situation is reached while opening BOM reports ("<something>.BOM" cannot be opened)- s9 [9 ^! z/ B1 e4 q7 J! F8 K
858245 CAPTURE IMPORT/EXPORT PCAD import does not work in 16.3
9 @# _, U) p8 |% m1 {6 x860905 SCM UI Part cannot be replaced after it's added5 X7 ]# @% C D9 Q
869528 CAPTURE SCHEMATIC_EDITOR Refdes increment on copying part is not with respect to occurence value.
. W( V3 w" Y5 ]873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP' D a9 h3 e3 o7 c) C3 z
877994 CONCEPT_HDL CONSTRAINT_MGR Assigning ESpice model to active component with Class+ b" D# m8 \# d. F9 T' q
883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component
_1 f2 A1 E# K887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.
0 u# A$ X( T0 s/ t) e$ ^887477 CAPTURE NETLIST_OTHER Other netlist is missing some nets and components after refdes changes in the design
, q4 d. K+ C9 Y' E6 Z887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message
8 ]( D5 Z$ M' q0 ~+ S$ x& }9 D- f887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.% c" Z+ L' i* k$ K8 s z; b, _& L# C
888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.! N$ ~; X. L- A. H$ G, q0 z
888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic0 t- X1 F2 B3 b, S, X/ ^
888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.
# s/ i x' F/ v6 \* p/ P/ B888945 CONCEPT_HDL OTHER unplaced component after placing module8 o+ g8 l9 S6 M* ?2 ]' N0 [
889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3
1 K- Q" P2 `" @4 j" O( m889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62." ]# c) X1 Z! G) X8 j6 z
889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form
7 [" r/ f# K+ S4 b6 x4 J891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file
! L) [( l4 a7 [: V+ W" }9 \891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs D" Y& Z- h/ F0 q8 e
892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?
, @! W" a! m p# T892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode
7 X0 ?# R) W7 F- T/ n4 v892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations6 c2 G& P1 S3 K
892991 APD BGA_GENERATOR BGA Text In Wizard creating two refdes text at the same location.
: v2 X. M$ Y# z9 c4 J" }893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.
6 ?4 G! ?& e. O5 W( f, }8 n( t% @, g+ E! h3 g4 d3 V
DATE: 04-22-2011 HOTFIX VERSION: 029" ^$ b. ]1 z0 m' C6 f, Y
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CCRID PRODUCT PRODUCTLEVEL2 TITLE) b; S# _9 `- d
===================================================================================================================================1 \! _6 y/ ^5 p8 C; g& Q- K
789198 CAPTURE PROPERTY_EDITOR Newly added user property to a symbol can not be moved on the schematic page.
1 o9 M$ N' ~& P- v( H0 V2 N812501 CAPTURE NETLIST_OTHER Extension of PADS netlist is .NET in V16.3. It should be .ASC.6 z8 ~: {: Q7 w; ]9 { p
842161 CIS GEN_BOM CIS standard BOM taking long time
2 q6 X7 y5 @0 A2 M4 `% H4 [844125 CAPTURE NETLISTS Normal and convert view placed in same design don't get netlisted due to duplicate power pin names.. O+ f% P6 a2 o- H: q
847688 CAPTURE PROPERTY_EDITOR Property Editor changes selection on Display9 q2 Y! A) Q& [0 q
851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.) P+ f) U e8 v! w
862785 CAPTURE NETLISTS RINF netlist with net attributes generetaed by capture 16.3 is not getting loaded in CADSTAR tool2 c4 w& w3 y2 E8 T3 v% z" I7 |) C$ s
868118 CAPTURE NETLIST_ALLEGRO Differential pairs not getting netlisted in hierarchical design.( {# |7 J2 D% g. Z: h$ [
880219 CIS GEN_BOM Standard CIS BOM does not viewed properly if underscore presents in Part_Number property, j+ o' \7 o3 `: T
881792 ALLEGRO_EDITOR SHAPE Cannot Delete the Islands on the shape. No Error reported.5 P" C+ V' z/ S% Y1 e/ c: P
882128 SPECCTRA HIGHSPEED Difference in length report between Allegro and SPECCTRA1 a$ P! d1 V5 \/ F( w5 P% W3 u; y
883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager
+ L& \4 T( a( n+ L* g0 |883291 SIG_INTEGRITY OTHER Z-axis delay causes incorrect actual values for delay$ r+ q# d( a4 U9 r: N4 F, L
883971 APD EDIT_ETCH APD crashed when I tried to add cline in (-6674.79 -7506.74) via.
- V5 r/ q7 Q; e5 n4 ]$ p$ A884061 CAPTURE SCHEMATIC_EDITOR multi-line text zoom doesn't work correctly
- u8 n0 P( E+ V884181 ADW DBEDITOR Parts get released anyway without any errors flagged.2 @5 S4 [) j" r! w, R3 t/ R
885019 CAPTURE GEN_BOM Create BOM causes Capture crash with include file& c1 U, l, [0 I: ?$ X; g
886437 ALLEGRO_EDITOR SHAPE Change of behavior of NET_SHORT between 16.2 and 16.3
f" ]! |+ h- _; b887190 ALLEGRO_EDITOR PADS_IN getting parse error during PADS to Allegro Import
1 E' j- x% D; g" n! f887348 ALLEGRO_EDITOR MENTOR mbs2brd translator crashing without any error message in attached testcase -v16.3s0274 @1 f/ V/ d7 I7 [9 b
$ c; Z8 w- V1 R7 i! ~7 DDATE: 04-8-2011 HOTFIX VERSION: 028- w! K7 i; \1 T# B
===================================================================================================================================* I `4 h( ~* D" `, O" x/ X" _1 ^
CCRID PRODUCT PRODUCTLEVEL2 TITLE
T, k" l) j# K- W===================================================================================================================================
# F/ w& ]8 t5 d( C- k; @# u9 C4 O704398 CONCEPT_HDL CORE In Windows mode basic shortcuts do not work when in German language& R3 O7 v! s+ j2 y) p0 k
771137 ADW LRM LRM reports 'Injected Mismatch' for a value based on capitalization of ptf value4 O0 ]1 W. r$ J! w: L7 S
872547 CONCEPT_HDL CORE Document schematic - Published PDF is missing Bookmarks5 F9 i8 V! W: R/ v4 K6 P
875001 CONSTRAINT_MGR OTHER Click on the Constraint Manager selected net filter icons crash software.& d6 p6 a$ R! Y6 u4 J K; o2 H
875039 CONSTRAINT_MGR ANALYSIS RPD margin is not calculated in 16.3
v" ]+ Q( q' J. J6 k: U876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net% Z9 j3 f `4 B! X. f$ n1 U! k$ ^1 r" B; |
877912 APD DRC_CONSTRAINTS Shape to Shape DRC seems to be behaving inconsistenly above 90 um spacing on mcm database.; C2 M9 Z/ H1 ^3 k* u* a
878022 CONCEPT_HDL CONSTRAINT_MGR NO_XNET_CONNECTION is not working unless defined on last discrete before receiver( O0 T$ U! a& S' G$ u. H& r, K/ ]
878519 SIG_EXPLORER OTHER View Trace Parameter - stripline trace model display incorrect distance to the reference plane
6 e+ \4 e& w0 f$ Q879529 CAPTURE NETLISTS Misleading bus/pin ERROR [NET0081] message from PSpice netlist
" i- T1 `; P# s4 c9 d/ D881455 ALLEGRO_EDITOR INTERFACES Some Drill Figures missing while Exporting DXF
7 i7 z" |8 a6 A( R' X881711 ALLEGRO_EDITOR SCHEM_FTB Spacing constraints(Net Class) from schematic are not transferring correctly to the layout
6 {! }. i% X, c! ?" O882277 ALLEGRO_EDITOR DRC_CONSTR Get Bogus (false) "Thru Pin to shape spacing" DRC for Oval slotted pads.
3 L' d, ]! q: P* o' C882408 SCM SCHGEN Export physical fails due to netlisting error with the ASA exported schematic
" v6 v0 p, Q' w) }7 C- K6 |882796 APD OTHER GDS stream import results in a set of bumps misplaced... possibly rotated 90 degrees
/ h& O- o) F/ a0 G% P* @) w0 T9 r( G+ G$ v. N0 v$ }, N
DATE: 03-25-2011 HOTFIX VERSION: 027/ h' V! J n) \( E
===================================================================================================================================
4 F S) m4 t/ u$ B: V" XCCRID PRODUCT PRODUCTLEVEL2 TITLE
- f/ k. ^/ ], e/ p* } c' {===================================================================================================================================1 h8 J3 q, M& Q4 |6 [2 I
820901 EMI SETUP Request EMC system.conf file that can be read from CDS_SITE.7 x- H1 A5 G: X: p5 M; o
861999 ALLEGRO_EDITOR DRC_CONSTR DRC hang after padeditdb
" e/ W$ {6 N& e- L" j862463 CONCEPT_HDL RF_LAYOUT_DRIVEN Rotating and Mirroring RF components in DE-HDL requires RFFLIPMODE property to be correctly updated: h% n% [) p! \# x
867223 ALLEGRO_EDITOR SHAPE Shape fill disappears when Negative shape is converted to Positive in Cross Section4 N& ^- Z1 a3 n- x6 D( O
868733 CONCEPT_HDL ARCHIVER ASA Archiver not saving the entire design.6 y0 g- ~( z! H0 R+ L5 I
871548 ALLEGRO_EDITOR MENTOR Shapes missing after mbs2brd translation
, o8 M% r1 F& }- a6 m, f872003 SIG_EXPLORER SIMULATION TDR simulation results were different between 15.7 and 16.3.! }. J9 |* v0 H! S3 ?
872464 CONCEPT_HDL CORE DEHDL script works in SPB16.2 but not in SPB16.3
+ ~ q( V, V+ N* {0 s) t( T: U873772 SCM CONSTRAINT_MGR Importing a block results in subblocks coming in without properties
# \+ ~: P# S( ]# V- T# _874335 SPECCTRA ROUTE Route Custom crashes SPECCTRA after routing for some time during "Running Route Phase".
8 I: i0 ` k& F& Z874989 CAPTURE SCHEMATICS Schematics jumps to another page after a mouse click
, e6 o: l" K/ c- a7 T: ]875161 CAPTURE NETLISTS Creating Allegro netlist hangs Capture
( [$ C3 r: p) n! d/ \5 s; y F875411 ALLEGRO_EDITOR NC NC drill produces Error processing extract . Program terminated.' Q: P, `3 ~ ~8 H* k$ d
876004 ALLEGRO_EDITOR SHAPE Unused pad suppression problem in Allegro v16.3 since S020~S024 ^+ G5 }$ `% S8 C$ `0 b
876045 ALLEGRO_EDITOR SHAPE Oval hole drills do not void shape with hole shape drc when the regular pad is smaller than hole3 O* u* E) N: V. q
876168 SPECCTRA_MENT_ IMPORT option to have a switch to prevent merging of plane layers during mbs2sp1 k+ X4 z' e1 N9 w- S ]
876210 ALLEGRO_EDITOR SHAPE When updating shapes to Smooth the tool will hang.: n8 J0 A3 b3 u& K+ u/ k, v
876284 ALLEGRO_EDITOR DATABASE Executing SKILL file crashes Allegro
# u5 O5 |4 j+ F877057 ALLEGRO_EDITOR MENTOR Footprints are shifted when importing from boardstation8 z2 e' h8 e9 s" I& i5 b8 \
877549 SIP_LAYOUT WIREBOND Wirebonds not moving correctly when on an Interposer smaller than the die.% L3 o- Z2 C& w- L* h% ~( e
877862 APD WIREBOND APD crashed when add Wirebond without any dump and cannot record script.
' d# e9 R: a# Z4 p- x) n8 J878199 CIS DERIVE_NEW_DB_PA Change in Regional Setting causing problem in derive database+ K) E. Q, |& t4 f8 w
878216 APD OTHER stream_in - Stream file scan failed! `: w2 @( }+ c/ E S/ J
878400 APD WIREBOND unable to add a wire bonding on few die pad
3 c6 @* k: T) e# z3 E X% G* e3 E q
DATE: 03-11-2011 HOTFIX VERSION: 026
3 J/ B" D( r+ u6 c5 d===================================================================================================================================1 C, H* _; w, k! ~& s
CCRID PRODUCT PRODUCTLEVEL2 TITLE
& S' J/ |8 `4 | a. G9 Z' s& J===================================================================================================================================
) M, a5 L9 i6 ~# A( }4 i# F851882 SCM SCHGEN Multiple issues with the ASA generated schematic in preserve mode while using square bracket6 v ~1 O( f. ^. T) m& y, F
852063 ALLEGRO_EDITOR EDIT_ETCH What is being displayed in the HUD when a percentage is specified as a tolerance?1 `, m) v2 @/ [! e
854502 ALLEGRO_EDITOR DRC_CONSTR DRC not detected until DBDoctor is executed. Status form and sum dwg report are incorrect." w8 p4 b/ y0 X
856797 EMI RULE_CHECK Arc segments were detected as warning by bypass_plane_split.
p$ r/ [8 I H, q2 _" M859213 PCB_LIBRARIAN CORE $LOCATION size in PDV and DEHDL differ. `3 P- s2 j& m& e
860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser
1 w! w% m; n* x9 F+ h5 m/ W; m862259 SIG_INTEGRITY FIELD_SOLVERS EMS2D run twice during View Topology.+ n" ?; P2 d& e& a1 k+ A! s
865158 ALLEGRO_EDITOR SHAPE Shapes are not voided with Dynamic Shape Fill modes with Regions7 z# W" m) M% m& d
865295 PCB_LIBRARIAN CORE Part Developer crashs with symbols having Japanese notes
b% q+ ^! f4 c( [- \866095 PCB_LIBRARIAN EXPORT_OTHER Export DE HDL part to Capture Part Crashed
! M2 y, f4 w7 L. V! s866835 SCM UI User arguments not used over project arguments for new tool$ K/ r; S1 _+ n9 @" z* R+ w& w
867102 CAPTURE LIBRARY Incorrect pin number gets assigned to pin if a PDF is opened before writng the pin number.8 b9 {7 I7 ?% }0 c
868092 CAPTURE GEN_BOM Capture BOM in V16.3 is different than that of V16.2 for attached test case.
) B: V0 f. V- w/ X# y8 L# V868517 ALLEGRO_EDITOR ARTWORK A pinhole was made in the artwork file.
) R( l; K" t/ B$ K$ k( \' u868646 ALLEGRO_EDITOR SCHEM_FTB Change in the PIN_GROUP at the chips level not propagated to the board file does not allow the swap
6 v( Q5 `5 c/ A+ A0 d5 x868844 PCB_LIBRARIAN CORE BUBBLE_GROUP with no value causes problematic symbol" ~4 t) Q" T0 O) `' p2 \
869326 CIS DESIGN_VARIANT View Variant is not showing part as Do Not Stuff7 h2 F% U0 P) ^% m0 o6 n
869547 ALLEGRO_EDITOR SCHEM_FTB Error while parsing the alternate symbol
% ]' ~: ]3 \% q! H5 F R4 e& U' E869931 SIG_INTEGRITY OTHER DML Library Management rewrites library longer then 512 characters into multiple lines.
1 r9 K* ]+ }; Q0 |0 b869960 F2B PACKAGERXL PART_NAME property added to Export Packageable schematic parts, j3 B6 d$ [: T: ^
870392 APD EDIT_ETCH Route > Slide not performing as expected in 16.3
% U- R c3 N% j' o- H! R7 ?2 a870704 ALLEGRO_EDITOR PARTITION 2nd import of parttiotion unplace components in master1 S0 y3 ?4 a$ B1 m% N* Y
871177 CAPTURE LIBRARY Keyboard shortcut for closing the Place Part window- Q0 W' [: |* q
871552 PSPICE SIMULATOR Pspice tool crash5 Z7 Y a+ @5 T- _ l
871643 ALLEGRO_EDITOR INTERFACES IDF in batch and GUI for dra files fails to calculate extents correctly" M; T+ P8 I, [" | [
871968 ALLEGRO_EDITOR COLOR After using Clear All Nets, Color Dialog box needs to be reopened for adding custom colors.6 r* Z0 Q1 \1 a. a1 q$ }: c
872352 APD WIREBOND Move Guide paths crashed APD.2 g% b- j" D* y9 J
872380 CONCEPT_HDL COMP_BROWSER DEHDL crash when editing the ppt_optionset.dat file from Part Manager.
( E6 Z& j3 L9 c2 m' l1 c6 A7 I872450 APD WIREBOND Wire to die edge angle remains highlighted in red for wire bond status window in v16.3; i3 Y7 Y* ~2 ?1 n/ {9 a
872787 APD WIREBOND Some Unused Wire profiles be purged but still existing in Bond Wire Profile of Color Visibility?9 r5 T, V# f6 P9 T. J3 Y) b
873217 ALLEGRO_EDITOR TESTPREP Testpoint generation not working correctly
- x6 ~( z- s( s* W873500 APD REPORTS Total Plating value is 0# d" h! C5 J) r& ~
873505 APD MANUFACTURING fillet size changed when recreate Plating Bar
0 E2 |+ h5 c5 Q$ o; {7 P5 ]873600 APD OTHER When attempting to Display Pin Names the tool takes a very long time.% z1 ]' @2 @4 T2 \" S# @4 ~( {
874341 ALLEGRO_EDITOR OTHER "Gloss>Convert corner to arc" command made an unnecessary circular arc.( e1 u4 |4 I& b) k$ q5 ^' A
4 w% s$ H% T, U0 a6 ODATE: 02-26-2011 HOTFIX VERSION: 025 _$ W q& A/ D2 B) E
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( `( x$ ?6 `# m/ y7 ECCRID PRODUCT PRODUCTLEVEL2 TITLE$ w( e) t2 B/ ^+ O
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" j# Q& g0 [' p/ Z3 M2 D7 _8 p746063 CIS OTHER CIS Query Does not display initial search results
0 K1 f3 i) z# v9 Y779588 ALLEGRO_EDITOR PLACEMENT Symbol outline not rotated with component.
% X1 H( G3 X+ d4 c/ I805616 ALLEGRO_EDITOR ARTWORK Allegro produces warning about database extents exceed film size
/ \/ s v7 N8 U- i- k7 N843145 CONCEPT_HDL CORE Cannot copy grayed out properties in the Attributes form to the buffer) X* {# B! @" ~
845607 ALLEGRO_EDITOR EDIT_ETCH Sliding with arc gridless enabled leaves extra segments behind and 45 degree segment.
- S- v5 A+ d8 q0 H" u5 \5 t850428 SIG_EXPLORER SIMULATION SigXP failed to simulate the topology with designlink.$ K7 @. Q- B& j" b
853665 SPECCTRA CHECK Scheduling violations reported incorrectly.6 s1 u) U, R- M
855534 CONSTRAINT_MGR OTHER formula result does not update when length changed6 P D; O- _. S7 C& I7 M0 M
855793 CONCEPT_HDL CORE Rename Pin on Block is not working in DE HDL with HF 21$ \6 [! q% \% u% z. |8 d
856306 ALLEGRO_EDITOR INTERACTIV Modifying pad instance corrupts db8 W' j8 E6 Q" @! h) f; |, X
859437 SIG_INTEGRITY GUI Log Scale setting of EMS2D was cleared by re-open design.- a7 @2 {) \% c
859850 SIG_INTEGRITY GEOMETRY_EXTRACT Allegro freeze during topology extraction with EMS2D." s" t# b/ }. S* R H. V1 m
860366 CAPTURE CONNECTIVITY Netlist is different in V16.3 than in V16.2
! A9 M1 P. K7 O6 K+ J: V/ {! U860809 F2B BOM Bomhdl failed to create the design view check for existance of the packaged directory
/ B' N/ z( o) e& S861027 CONSTRAINT_MGR CONCEPT_HDL Unable to synchronize the constraints
( _( H" a( x- l) l P862137 SIP_LAYOUT OTHER SPB 16.3 SiP Logic - Derive assignment is unable to resolve connectivity of shapes
3 X" I, L/ V1 m862980 ALLEGRO_EDITOR EDIT_ETCH When sliding a via the potential DRC behaviour is inconsistent.2 v* H' j; L! c8 E- z
863400 SPIF OTHER SPIF does not translate the oblong pads correctly
- e8 V: i+ w4 `/ D3 d864363 APD REPORTS The Wirebond report is failing because there are Non-standard Bond wires present.0 l$ K- Y/ t& I8 a
864621 ALLEGRO_EDITOR DATABASE Database corrupted after adding layers in Cross Section and trying to save the board file.4 G% ^' g& b6 ^1 I. J4 y! x
865875 ALLEGRO_EDITOR MENTOR mbs2brd translator results in broken/unrouted nets even though the BoardStation design is fully routed) t9 j5 Z) a7 U: I
866202 CONSTRAINT_MGR OTHER Worksheet File import fails with error message due to character limit
* j5 ~' a( t) \1 {* c/ \866726 CONCEPT_HDL CREFER TOC (table of content) not generated in schcref_1 schematic (CREFER flattened output).
$ m+ V& o! L5 m6 `% p2 x3 S3 V867238 CONSTRAINT_MGR INTERACTIV Split Xnet for diff pair crashes PCB editor3 E0 a! W4 H- N0 i$ }% e
867696 SIP_LAYOUT DIE_STACK_EDITOR When doing an Info on this design it will crash.' A$ B- @8 Z6 e9 C! {+ U1 l
867742 ALLEGRO_EDITOR DATABASE Thermal Pad view for shapefillet on Negative layer0 y% b# A: w( a+ s% i
867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"
2 N0 _9 A9 C: H6 I868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets
! |0 D; i1 a( [- L( R869758 CAPTURE GENERATE_PART Generate Part option "Copy schematic to library" does not copy schematic page attributes! r- ~' m/ a) g; E+ ? K7 ~
869941 ALLEGRO_EDITOR PADS_IN PADS_IN unable to import Power PCB 2005.0 file in 16.3 but works with 16.2
* D" u! H' W, O! X( E870301 SIP_LAYOUT SHOW_ELEM When selecting Info and then a rectangle shape, the tool will crash.
+ g5 Y% a; W1 {" l6 e
2 ], W4 h d. D! XDATE: 02-11-2011 HOTFIX VERSION: 024
/ t4 [7 l6 o$ S( t. l===================================================================================================================================0 c+ O9 f& F/ R% t* b+ P; W" j2 F: z( Q
CCRID PRODUCT PRODUCTLEVEL2 TITLE' x. S% P4 }* j; m4 J$ `: ^" I
===================================================================================================================================" Y4 \ a) s. q7 s, o0 Z
858051 ALLEGRO_EDITOR OTHER Allegro's Help>About... System Info... doesn't work on Win7
) N! d7 F" W5 B8 U6 d: i862703 ALLEGRO_EDITOR DATABASE crash when doing a save_as( q( W! o' F+ q& C+ V' A! ~# M
866288 ALLEGRO_EDITOR NC Drill customization table won’t let you add characters in lower case% |( q4 j6 V5 g" e* J- A
866310 ALLEGRO_EDITOR DRC_CONSTR Testprep doesn't create a DRC for Testpoint > Component- q r7 h5 y# B; Z- w& M
866652 ALLEGRO_EDITOR SCHEM_FTB Allegro Spacing net class not updated with new logic
& I' d) o2 n8 j
r/ x# P- M1 N+ F7 w$ O, YDATE: 01-28-2011 HOTFIX VERSION: 023) R3 e6 x# s2 P. {1 O0 l# ?9 v
===================================================================================================================================
# h. k- t4 G- }CCRID PRODUCT PRODUCTLEVEL2 TITLE5 Z! D9 y( x; V7 K* E8 `3 W+ R
===================================================================================================================================
" U! _0 M4 `/ G& \. o739067 SIG_INTEGRITY SIMULATION about modal delay of diff pair net1 h! O5 \7 O7 b, c/ G1 K5 n
742237 CIS FOOTPRINT_VIEW 3D Footprint view in CIS Explorer
" `' @5 G! d" n* z762702 CONCEPT_HDL CORE Unable to change color settings5 j3 @8 a( W4 R# g- t/ ]) @4 H
800333 CONCEPT_HDL CORE Text change cursor not working on Solaris and Linux
' Y8 w0 m* }) g837479 CONSTRAINT_MGR DATABASE Import dcf with custom column cuases a problem
) {7 W9 J' i B6 \; s4 W8 s846679 ALLEGRO_EDITOR SHAPE Through Pin can not be voided correctly in dynamic shape.1 L: z, d1 ~: m% X6 o5 z2 p
852255 CONCEPT_HDL COMP_BROWSER DEHDL crashes when adding part from cat file( ?& p4 F3 u$ c! [: K- D
855553 ALLEGRO_EDITOR DRC_CONSTR Multithreaded DRC shows different DRC counts+ A$ k+ p: e$ L1 ?
856459 SIG_INTEGRITY GEOMETRY_EXTRACT No waveform was output if users set the Via type to Analytical type: H& c- Z1 ?( a* X
857030 SIG_INTEGRITY OTHER Inconsistency when signal model has "legal" spaces within it. U4 O T5 c# @/ S. u! R" Q
857120 APD WIREBOND Enhancement for Redistribute Fingers.
7 p( F2 B. ^- O4 l5 d% D857165 SIG_INTEGRITY OTHER Model Name Changed Warning appears every time after Export Physical, R) @6 g$ r% T
857237 ALLEGRO_EDITOR SCHEM_FTB UserDefined mapping mode
) j8 j1 ]' c* c; I& I0 z857650 ALLEGRO_EDITOR DRC_CONSTR Hole to line DRC unavailable on inner layers for mechanical pin with no regular pad definition., b" X7 n/ C% l7 g3 v8 ]
858046 MODEL_INTEGRIT TRANSLATION Ibis2signoise fails translation when the unit of Pin section is "ohms".
3 o/ w/ K) J0 |. E858154 GRE DETAIL Net not following the plan during Plan Topological
, P9 h+ \$ e% T: Z" {* ?4 R% Z858192 SIP_LAYOUT SHAPE Program crashes when attempting to add polygon shape.. \. [, k" r% E6 s1 W
858307 CIS DESIGN_VARIANT Homogenous part not showing correct DNI on schematic- e# _8 d( a+ L, s
858624 ALLEGRO_EDITOR PAD_EDITOR "Save Padstack to 16.2" command is needed in 16.3 pad_designer.& s# }( x8 @0 p; v2 V
858814 ALLEGRO_EDITOR MODULES place module not placing figures present in mdd
4 F' _0 }6 L+ ^$ L859514 APD IMPORT_DATA Die Text-in cannot change unnamed Begin Layer to selected pad layer in step 44 U4 R9 `3 V3 ~
859640 ALLEGRO_EDITOR PLOTTING Shape based pads not output as polygon in IPF
$ m ^" [1 \3 ?: Z0 E$ z) v& A. ]859680 ALLEGRO_EDITOR DRC_CONSTR Multithreaded DRC shows different DRC counts
" R; k2 x- y9 g4 y% P0 I860069 ALLEGRO_EDITOR OTHER Import Logic hangs then crashes and displays Netrev warnings.+ r9 G: \' X, W
860535 APD DXF_IF a2dxf got an error message
4 y" m8 J9 M! f1 U$ E+ ?860860 CONCEPT_HDL COMP_BROWSER Component Browser freezes: g: B/ ~4 O6 v5 q( X
861295 CONSTRAINT_MGR ECS_APPLY Diff pair PCSet value overrides ECSet values in constraint manager spreadsheet.
* F8 {$ i( E7 K/ q4 D/ }4 o4 H% D862279 SPIF OTHER running 'Allegro PCB Router' Crashes
& o7 t! h) s. c) k+ c$ E3 S9 [; i T* j9 Y
DATE: 01-14-2011 HOTFIX VERSION: 022
9 h" x$ |$ W V9 Z% D: f' U! j& H6 Y===================================================================================================================================# }: `0 m& f+ Q" _+ O! Q" ~
CCRID PRODUCT PRODUCTLEVEL2 TITLE
+ g3 ]$ N7 e- i===================================================================================================================================
- S4 u4 D7 M* t& D$ y1 |' P! V372240 CAPTURE SCHEMATIC_EDITOR Allow component move with connectivity change should be checked by default* L6 t0 o F J! J, h& D6 a
769139 SIP_LAYOUT DRC_CONSTRAINTS Wire to Bond finger rule in the CM needs profile to profile constraint capability+ e8 O4 ?; Y w- R) y
772299 ALLEGRO_EDITOR GRAPHICS Via doesn't get highlighted properly with OpenGL disabled" A5 G; ]5 o$ D$ [) x" a
830519 ALLEGRO_EDITOR GRAPHICS Disabling openGL causes highlihting problems.
. _/ R" t( _4 [3 E& \833981 RF_PCB FE_IFF_IMPORT DE HDL Import IFF unit conversion and unit display in RF schematic1 q" o" T, T$ `- _$ W
835698 RF_PCB FE_IFF_IMPORT DE HDL Import IFF to assign simple sig_names like RF001 RF002 etc8 {8 @3 ^! P L+ y: ^; j) g
840094 RF_PCB OTHER dlibx2iff does not translate complex polygon pad4 j& ]3 A2 R8 m( E
844504 SIG_EXPLORER INTERACTIV EMI Regulation setting of the board is not reflected correctly when the net is extracted into SigXP
2 u4 p/ M6 n8 @5 \. X8 g5 }! [: p6 D846210 PDN_ANALYSIS PCB_STATICIRDROP IR Drop mesh is not correct.
' \* Q1 A2 t1 P2 B C& T/ Z8 C846228 SIG_INTEGRITY OTHER ZAll and Wirebond calculation in the Prop Delay formula
6 n# U: M+ P& j) ^$ g( [7 ~846259 CONSTRAINT_MGR CONCEPT_HDL Why dont I see the P1_8V_DIG net in CM ?6 u, T* R8 U# M7 a: d; ^4 _
847278 CAPTURE TCL_INTERFACE TCL/TK PDF Export Change Page Size
' i+ z+ B8 S' @3 h9 ]847942 SIG_EXPLORER OTHER The solder resist layer was not included in Interconnect Model of SigXP.) ?9 |5 M/ |( G
848181 PSPICE DEHDL Model association for concept symbols with a chips view doesnt work( s: }2 A" l1 q7 T" v1 b. s( p- b$ g
849707 ALLEGRO_EDITOR MANUFACT Thieving creates unwanted thermal reliefs in this design.
8 v% H. y0 T) j: I7 @" U' N851070 CONSTRAINT_MGR CONCEPT_HDL The Match Groups are not visible in the CM
1 g7 w9 _! N4 F851171 F2B PACKAGERXL Design will not package with exclude_cdsNotOnSym
# d# H( Y! Q2 B3 |( z6 }7 T; q' I851290 APD PADSTACK_EDITOR APD/SiP crashes when the user defined mask layer is edited with padeditdb.
7 l- p- i& e/ y r9 U5 @851477 SPECCTRA ROUTE Allegro Router runs out of memory during route passes
$ V0 G8 a3 W* ~6 W, j. R851658 APD EDIT_ETCH bunceback behavior while slideing cline
' f: F, g, `% R5 L, E; t6 S851725 ALLEGRO_EDITOR DATABASE Number of DRC is not consistent on each DRC update., S3 g* L8 r! ^2 H0 R% R0 X
851789 ALLEGRO_EDITOR SKILL Skill axlAirGap for Via & Text causes Allegro to crash1 O# Y1 w, v/ s& f6 L
852325 ALLEGRO_EDITOR DATABASE Perf advisor doesn't check high pincount devices for RATSNEST_SCHEDULE2 D/ W3 B$ `( u2 i* ~
852360 SIG_INTEGRITY OTHER Appling toplogy template to a diff pair object reports UserDefined in CM4 ~3 o# g3 \, x3 G/ P0 K
852395 ALLEGRO_EDITOR DRC_CONSTR Same net via spacing broken drc shows up to date {. }7 M1 L& M/ g
852764 ALLEGRO_EDITOR SKILL axlHttp beeps and gives error E - http 423 ? | x1 x: _
852787 CAPTURE ANNOTATE Tool is crashing during annotation if Ref Control is set/ M* y& o M; {2 c B
853110 ALLEGRO_EDITOR ARTWORK Allegro Crash on selecting Mfg > Artwork if any Parameter syntax is wrong in art_param.txt
. z. t' ]3 E6 }. j+ P5 i854031 ALLEGRO_EDITOR MANUFACT The stream out data xxx.scf seems to be incorrect.
, v; [9 ?9 L; V. a1 g- r" I854246 ALLEGRO_EDITOR MANUFACT Stream out data of Oblong pad is strange.9 y6 |% }8 G& a+ A& |( q
854293 APD OTHER dynamic fillets were disappeared when open in 16.3., z% T7 B: Z2 g, X2 c! i
854356 ALLEGRO_EDITOR OTHER Fillet adding doesn’t check same net spacing rule in both static and dynamic mode. O" V+ `1 \ d X
855101 ALLEGRO_EDITOR OTHER Drill figures now smaller than expected
0 ?& ~& i4 |+ ^; n" i- W3 a# p855124 APD PLOTTING The "load plot" command did not import Drill symbols(Figure) and Characters in APD.
K. l* z9 d3 j9 \% h. R: ?855348 ALLEGRO_EDITOR EDIT_ETCH Differential Pairs do not slide to correct geometry, S/ H6 o5 K' K, a" s$ [
856220 ALLEGRO_EDITOR INTERFACES Export DXF in the 16.3 S021 build rotates some pin locations
" D) V' S x; {' k5 \) l3 m856256 SIP_LAYOUT WIREBOND When editing a single Wirebond all wirebonds attached to the finger get highlighted.+ S+ A1 \, T" b+ u6 y* B
856674 ALLEGRO_EDITOR AUTOVOID drill hole to shape autovoiding clearence is wrong for Same Net Spacing
7 o+ x1 o" A- {9 }! L; Q- C% g% M/ w" K& d6 }. i) j& s
DATE: 12-10-2010 HOTFIX VERSION: 0214 K5 h9 j5 F7 L& P! ? ]9 U) {
===================================================================================================================================
* B* O: |2 w- B( o' |0 M DCCRID PRODUCT PRODUCTLEVEL2 TITLE7 k% Z8 W( T/ y! K( X z4 g
===================================================================================================================================; F J% c0 {; b7 Y3 S& r- P# ?& s# P3 h
708992 ALLEGRO_EDITOR SCHEM_FTB Design Differences fails with Error #534& N, B, M% G F/ G8 S
748982 CIS FOOTPRINT_VIEW Respective pin number from schematic does not get highlighted on 3-D footprint viewer.( m9 ?1 A& O/ |8 W
775788 CONCEPT_HDL COMP_BROWSER Component Browser search is too slow
' a; x9 L8 s. ?802152 PCB_LIBRARIAN IMPORT_EXPORT cap2cond design translator is also looking for Capture feature string in license - this is break from 16.2( ^# {* f4 `, w9 T- v7 c3 E
803910 ALLEGRO_EDITOR GRAPHICS Request Rat like display for REFDES text to component.* R) ]! A8 X3 e# P4 {
823599 SCM REPORTS Ability to generate DEHDL style BOM report$ O, S" I+ Y. Z2 p3 D% j5 g
826558 CONCEPT_HDL LWB-HDL Module definitions for cells is not included in the simulation verilog netlsit on LINUX
4 O: [8 d: C/ O% ]828689 CONSTRAINT_MGR OTHER formula constraint lost when Constraint Manager closed
* m0 ^% j) [! O5 o. D r0 T831192 SIG_INTEGRITY GUI Cannot close Analysis Preferences window.
' z/ j8 U0 e) C" ^9 {) y831229 ALLEGRO_EDITOR INTERACTIV When mirroring sym PLACE_BOUND shape does not mirror til placed2 p& x$ K$ X# z' Z
832315 ALLEGRO_EDITOR SCHEM_FTB ECO.txt file should not list net names if schematic and board files are synchronized.
/ ]8 ?5 N8 h# E832644 ALLEGRO_EDITOR DRC_CONSTR DRC error disappears when the size of Constraint region is changed.( y$ \( `, o, A% ]8 b! t, e
833061 MODEL_INTEGRIT TRANSLATION Model Integrity IBIS2DML fails to convert data correctly for pre-emphasis using Driver Schedule: ]2 b: x* m6 w
833487 SIG_INTEGRITY GEOMETRY_EXTRACT Probe sim failed if VARIANT_TO_IGNORE was set.
, s/ L: d7 k4 a+ f$ i% V" l4 y8 L" I833922 CONCEPT_HDL CORE Move pin on blocksymbol using Block -> Move Pin command change the Pinname textsize. |% s2 k d; R- n$ P Q4 C: q
834103 ALLEGRO_EDITOR DRC_CONSTR dynamic diff phase highlight not showing
+ z# j7 Z1 H1 ]. h( i. u834868 SIG_EXPLORER OTHER View Trace Param crash if sweep param was set for loss tangent.2 B& v3 t1 \. g$ B5 e4 O2 J% O) ]
835006 CONCEPT_HDL OTHER Locked BACKGROUND directive is changed in DEHDL session
& M7 ], H& o- i8 S835326 APD SPECCTRA_IF Specctra does not open from APD using Allegro Package Designer XL (Legacy) license" `+ {% J* B3 e: M6 L6 @
835622 CONCEPT_HDL CORE DE-HDL crashes when selecting wire having global sig_name in opened block schematic
7 m# `: j0 O6 z+ y8 Z836962 CONSTRAINT_MGR ANALYSIS Simulation will crash% Y3 A2 {. i& ]! \% U8 M/ Z2 _
837216 CONSTRAINT_MGR OTHER Custom measurement Rslt lines being duplicated in a different worksheet.0 i* U( t: y0 a# x
837322 CAPTURE LIBRARY Library is not getting freed even when user has closed it.0 U3 t- E9 F* ~
839517 CAPTURE MACRO Macros (for place part) created on 16.2 version works differently on 16.3* g" y5 g/ {2 |' E0 N
839749 ALLEGRO_EDITOR MANUFACT Drill entries are repeated in .drl files
c$ j0 s2 d; ], i840738 ALLEGRO_EDITOR ARTWORK Shape symbol in padstack moves when Artwork is generated - Break again after fix in 16.00 B0 U3 M; n6 \" R2 X* ?" d
841176 CAPTURE ANNOTATE Homogenous parts are not getting packaged correctly in annotation in 16.3
6 h ?, U4 C/ A0 u0 S# d! j+ G841355 SIG_EXPLORER OTHER Trace model parameter does not update when linear Range are entered.+ G, p1 d. O. B
841730 CONSTRAINT_MGR OTHER Allegro Crashes while working with MGs in CM3 I* E4 R8 q2 T# a l
841759 F2B BOM BOM creates an incomplete output when design packages without errors
% k1 p3 v% @6 x* @2 w/ ? W* ~' ?841928 CONCEPT_HDL CHECKPLUS CheckPlus fails when pin name contains _N in the middle of the pin name8 L2 p9 C- X9 s( E1 X8 L5 A$ |
841991 ALLEGRO_EDITOR PLOTTING Offset of text and line on importing a plt file7 ?% R t3 z' r j( D
842204 ALLEGRO_EDITOR DRC_CONSTR Arc creates false DRC on edge of Constraint Area
' w+ _/ a4 l* l9 o' y1 [5 J9 g% H843114 SPECCTRA ROUTE Specctra rules file taking very long time to load
1 B4 v6 x& _3 _8 f843254 CONCEPT_HDL CONSTRAINT_MGR Unable to invoke CM from DEHDL CM Crashes with an error Olecs.exe The application has quite unexpectedly) k. a% ^" H6 U' G
843518 F2B DESIGNVARI Variant with FAIL_OPEN& h+ n$ n$ h+ O3 Y; M' o
843933 ALLEGRO_EDITOR DRC_CONSTR Cancelling drcupdate will either hang or crash Allegro
3 w7 h( h. H- I' f+ v% \1 ^844074 APD SPECCTRA_IF Export Router fails with memory errors.* q: z( B# F" |) w# R: F6 q8 X
844246 ALLEGRO_EDITOR SHAPE Long Thermal_Relief connecting to XHatch shape* F8 [! [' s3 \! e% i% p9 t. M
844355 CONCEPT_HDL COMP_BROWSER User seeing CDS_NA appear when placing component
" J0 }- [( [2 E844381 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin - Pin is connected to net <netname> not reconnected.# s: `% u/ S' ^
844662 SIG_INTEGRITY OTHER Cannot uncheck options in analysis preferences.9 G) p8 _) W8 V" u# |
844796 SIG_INTEGRITY OTHER Get an error E- Illegal model name. Cannot add model RE_RES_0402-16570580,when doing Auto Setup during Model assignment
) M# {- y$ A$ I6 r+ D k8 [. J- G846172 APD OTHER Cannot generate the dxf file from this database
! S7 ]% g$ t+ R4 m; `846270 SPECCTRA GUI SIGNAL_15 layer missing from the color pallete in Specctra$ V6 }6 V8 x+ w
846352 ALLEGRO_EDITOR DRC_CONSTR Route connect does not select the pin-pair width for routing., \: }) b% R. n Y, h. F
846420 F2B DESIGNSYNC Design Sync failes due to FUNC_VIEW_FILE missing messages' x3 T+ ^ c8 K
846918 ALLEGRO_EDITOR PADS_IN Pads_in crashes when importing ASCII file, Runtime Error6 i0 [6 v/ h( u/ q: t; R' ~/ a5 r
847079 ALLEGRO_EDITOR DATABASE Allegro Crash while trying to unlock the board file
% y# D e) O, I! L: e848143 F2B DDBPI Adding part crashes DEHDL
7 a2 p: R2 [8 v0 l/ O+ W848415 CAPTURE STABILITY Crash on Mirror Horizontally( e* L i9 t& l5 |
" \5 Q/ Q# h( O3 R- k7 m2 oDATE: 11-11-2010 HOTFIX VERSION: 020
, ^9 j a% m4 _2 x, {. ~ [===================================================================================================================================, k9 f: Y- m' G& F# }; i/ _2 H
CCRID PRODUCT PRODUCTLEVEL2 TITLE" {" l- s+ R3 k6 g f
===================================================================================================================================
8 ~( u8 M: O6 [" P! E501606 CAPTURE OTHER Descend Hierachy does not open first page4 q# ]& e3 G' m* T' L
764482 SPECCTRA CHECK Allegro router same net checking different then PCB Editor.- [7 S- }) g x0 G8 @6 p
809055 APD EDIT_ETCH Shove Preferred changes trace widths of shoved traces during routing
, y( w( e* C" ?. `! I" u, q t- X) @816920 ALLEGRO_EDITOR PLACEMENT Update symbols causing Allegro to crash$ w8 W* j+ B: n3 u
826762 SIG_EXPLORER OTHER The rotation of element are different between pre 16.2 and 16.3.2 t# b" k# c" B! s1 @' ^) Y
827769 CIS FOOTPRINT_VIEW 3D footrpint viewer doesn't shows circular geometry on footprints
% {# m+ A4 @" j) m1 U8 A' X3 V828830 F2B DDBPI LRM does not update Parts which have a ALT_SYMBOLS value Added3 W( V0 |' C& v3 o
830319 SIG_INTEGRITY SIGWAVE Sigwave load errors out with "Requested resource was not available" after large bus simulation
4 o% o2 y7 d: l1 q4 W2 ?5 O7 e830359 CAPTURE GENERAL Crash on link Database Part! ^. B3 O, S) a
830627 ALLEGRO_EDITOR DRC_CONSTR Incorrect thru pin to shape SPACING error
( a) }% }* ]0 G2 _$ w( k* \" p5 d830716 CAPTURE PRINT/PLOT/OUTPU Capture crashes while printing a Capture CIS Standard BoM with ISR s0017.
, K! y# [- [ B+ s* F: m" y$ w830791 SIP_LAYOUT LEFDEF_IF Improve the LEF Library Manager to import passivation layers4 ]* Z" E/ X6 [8 ?( a) H9 A
831210 CAPTURE OTHER Users get an error message everytime While running Update Cache with V16.3 and V16.2 with latest ISR
' H- J# P T, Z831231 PSPICE SCHEMATICS pspice com wrapper error: n6 m4 V' f5 @& [8 u9 I
831692 ALLEGRO_EDITOR PLACEMENT Application becomes sluggish to nonresponsive when trying to place mechanical symbol: @) V1 j3 s s
831704 CONCEPT_HDL CORE ASA stuck in an error condition.
3 p! p% Y; C1 h( R7 J1 h2 O- W T G; j833116 PCB_LIBRARIAN IMPORT_EXPORT Getting LMF-02018 Error while Importing Capture Parts0 u3 J1 @) {8 x6 @7 G
833433 ALLEGRO_EDITOR TECHFILE techfile in/out round-off a value of Conductivity(Xsection).
3 ^) A" \0 Q4 A9 J0 |5 A& P; [833921 ALLEGRO_EDITOR ARTWORK Gerber filled lines stick out from filled area on Fillets* d% ?3 N$ i, N. h
833950 ALLEGRO_EDITOR ARTWORK Artwork process create recrementitious circle for AutoSilk data.7 s+ k1 c' Q/ F/ k" W
833975 SIP_LAYOUT DATABASE pad not on subclass
3 {; N# n9 V6 W' {8 L, l2 ]5 O# T834152 APD EDIT_ETCH Route Slide of a Diff_pair section moves all of the cline instead of just the segment that you want.0 D6 Y7 L- _7 r0 m
834861 APD OTHER package integrity runs for hours. results in no more room in database
" h0 g7 P) Y8 Q/ n9 {835367 CONCEPT_HDL SECTION Packager-XL reverses the pin numbers of connectors
" ]6 T2 [8 d4 [7 O. J837805 ALLEGRO_EDITOR EDIT_ETCH Add Connect crashes Allegro when routing from a cline (not on a net) through a region.& H) ^; E7 s3 O% N g" b L9 E
838057 CONCEPT_HDL CHECKPLUS CheckPlus crashes with long parameter." ^! L7 e9 t5 a. B, u; |% J' @
838356 SPIF OTHER File > Export > Router Crashes Allegro and dsn file creation stops
* H- K) ]; v# x7 c+ C' b838521 APD MANUFACTURING When creating pbar some clines are gone.$ @( N5 v. Z9 J" ^
838766 ALLEGRO_EDITOR EDIT_ETCH Sliding with arcs making sharp corners instead of arcs.
! }7 U& ]% ^& {; [3 t* s838830 SIP_LAYOUT ASSY_RULE_CHECK Assembly rule check flagging a DRC for item not near edge border
4 C- ?, l7 X5 R838836 ALLEGRO_EDITOR SKILL Pb to check license with skill core function, L& a+ n' R! _, L4 E- S
839218 APD 3D_VIEWER 3D view of this mcm file is not getting rendered and the 3D GUI screen shows up blank in APD
" D( `( h# _7 d! ]8 x: X `839362 ALLEGRO_EDITOR EDIT_ETCH trying to slide a bbVia crashes Allegro
" P* b+ _. k& t( ^839984 ALLEGRO_EDITOR ARTWORK Some pinholes were made in the artwork file.& d7 z- S2 ]3 q
840016 CONSTRAINT_MGR INTERACTIV Cannot manually create pin pair for unspec pins of Xnet.( i# ?9 z' s6 N+ A+ N# V
840455 ALLEGRO_EDITOR INTERFACES IDF exported/imported from symbol have no drill information for pad.
- j' R, q9 p, v' w' x841431 CAPTURE NETLIST_ALLEGRO Upgrading from Capture V16.2 to V16.3 some nets get shorted on the schematic page.
2 n% U& T, H* o$ e) w) ?% v+ E- T8 u3 w4 ~
DATE: 10-20-2010 HOTFIX VERSION: 0198 [% p% O* ?% ~) i) @8 W) _
===================================================================================================================================
3 ]' r7 P/ H. `0 `CCRID PRODUCT PRODUCTLEVEL2 TITLE
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717365 SCM SCHGEN Option for Schematic Block to have the defined Sheet symbol/Page Border+ F+ F1 Y1 Q" x! l# n! K" z
751477 ADW COMPONENT_BROWSE UCB in DB mode does not read local worklib for block symbols
! h- ~, w. Y- D9 L+ n5 N4 j792545 APD PADSTACK_EDITOR Can not rename user defined Mask Layer in APD/SiP.
4 x" ~4 y# N! B5 j9 p813436 SCM OTHER Option to have a directive in the cpm file to distinguish an SCM project from a DE HDL Project
) C. R; `/ U6 k820640 SIG_EXPLORER OTHER SigXP Crash after doing Transform For Constraint Manager
. f2 v4 m# C; D/ I7 x8 ~: T824527 CAPTURE PRINT/PLOT/OUTPU Part ref-des resets when trying to take variant print from Part Manager- Y+ U# y; Q# h& {
824688 SIG_INTEGRITY GEOMETRY_EXTRACT PCB-SI crashes when running more than 2 simulations9 @/ T4 A0 ?' I7 J, z4 g# J
826571 CONSTRAINT_MGR OTHER Import of .dcf crashes in 16.2 but not 16.3
5 t o, ]( C! I" b' R5 N$ z826626 CONSTRAINT_MGR OTHER Creating a Netclass from a custom worksheet breaks the Netclass object upon the next invocation of Constraint Manager.
L R3 d! G+ w; Q1 p$ R4 ^" K, e826799 SIG_EXPLORER SETUP_ADV can not close Analysis Preferences form when Advanced Setting button is opened and closed once( _" Z4 m5 Z, x2 d7 P
827375 ALLEGRO_EDITOR DATABASE Need to check why Net class assigned on the Net are not visible in CM
* t5 P8 H: A9 o6 K* w# n+ K827521 CONSTRAINT_MGR OTHER Allegro crashes when trying to open Constraint Manager." T; x2 O2 F* j- u
827713 SIG_EXPLORER INTERACTIV Cannot move object by click and drag after RMB>Note.
) r# L/ j. e I3 ~' q828803 CIS UPDATE_PART_STAT Crash on update part status from Part Manager
& b2 ^: K# ], O+ p+ i4 e829005 SIG_INTEGRITY FIELD_SOLVERS SigXP crash when RMB click on the Trace Model with EMS2D.+ o! ?+ V. D# N. v6 a) \2 s
829008 SIG_INTEGRITY FIELD_SOLVERS SigXP crash when RMB click on the Trace Model with BEM2D.5 j1 \6 n% z7 Z1 t; O: y
829233 CONSTRAINT_MGR UI_FORMS Physical Csets applied on a diffpair is not followed while routing, though visible in CM." V3 S4 ^4 u! n g8 ^1 L3 i) Z
829340 CAPTURE LIBRARY_EDITOR propertries are shifting after being placed# O) y2 @9 v3 q6 P! ]$ C
829747 SIP_LAYOUT DIE_EDITOR Move pin incremental coordinate
" N; r4 S6 x; m6 ~7 @829991 SIP_LAYOUT OTHER The "axlAddAutoAssignNetAlgorithm" function is missing from the Allegro SKILL documentation.
4 | m; V, z+ U6 w830509 APD ARTWORK The measured airgap aren't between features in the design aren't consistent in Import > Artwork.5 C5 x8 @9 e2 I' b5 T {
830809 ALLEGRO_EDITOR TESTPREP In the testprep report the Pin type is getting appended with net name
3 P$ t8 A% R9 a \+ m830907 SIP_LAYOUT DIE_GENERATOR SiP will crash when adding a Standard DIE using the Die Generator.. _7 h9 l" u+ |/ ?; K
831176 ALLEGRO_EDITOR MANUFACT Testprep Resequence crashes this design.1 n+ ^* E+ ?5 Z
831199 SIG_EXPLORER OTHER error in _sxUtilGetAllegroPart message was displayed.
0 v( u4 u# @6 {: R831610 ALLEGRO_EDITOR EDIT_ETCH Sliding with Diagonal Entry (45 Degree) is sliding the the adjacent vertical segment when Constraint region is present: @5 k$ O/ z4 O6 d6 C6 w8 u* R
831946 ALLEGRO_EDITOR OTHER Cannot re-open Command Browser if it was closed by Undo.2 ^+ e( \$ x, z0 |
831998 ALLEGRO_EDITOR SHAPE Allegro crash when user execute shape vertex add command.
. X! S# g* U; e832059 APD SHAPE Shape does not keep Shape-Via(w/ Fillet) spacing.- w( Y" Q0 y" f7 B! [( U5 V8 r* h8 u
832169 ALLEGRO_EDITOR EDIT_ETCH Sliding with Diagonal Entry (45 Degree) is sliding the the adjacent vertical segment when Constraint region is present
2 x$ |" t- p1 z- P r832197 ALLEGRO_EDITOR EDIT_ETCH Sliding diffpair slides adjacent segment
' A8 {6 P( @1 d# M" X832613 ALLEGRO_EDITOR EDIT_ETCH Adding microvia and bbvia crashes allegro at location where overlapping shapes exist on other layer
4 q1 K/ N% ~3 a1 F4 a: N/ C2 i832922 ALLEGRO_EDITOR PARTITION Import partition board crashes Allegro.
# a4 \# H& M! V" f6 q833127 ALLEGRO_EDITOR SYMBOL With 'unused pads suppression' the padstack (clearance) does not get rotated in the internal layer
% R6 l4 r+ ~+ i3 {9 h4 x6 F833251 ALLEGRO_EDITOR SCHEM_FTB Power planes on Layer E3 and E18 change to dummy net after Refresh Module.2 m7 A0 j; A' Y' F
833586 ALLEGRO_EDITOR PLACEMENT Allegro crashes while placing jumper3 g: N& |$ V. o1 @" r G
6 S9 w. A: x9 W2 U. a0 n* H* I* g
DATE: 10-7-2010 HOTFIX VERSION: 018
+ b' y0 S; `$ S$ l" e1 s) Z$ p===================================================================================================================================
: s7 y3 s5 L D3 w5 DCCRID PRODUCT PRODUCTLEVEL2 TITLE3 x0 S4 w- W: @$ B* x
===================================================================================================================================
8 G' O3 |6 b9 x4 t! L& ~+ J' H398114 ALLEGRO_EDITOR INTERACTIV Need to differentiate between tracks and shapes on an etch layer.5 q# m2 `1 }1 N9 o( w
530659 ALLEGRO_EDITOR UI_FORMS Allegro Place Manually and Update Symbols GUI missing checkboxes on Windows Vista
: \, P- p/ d% A7 l3 x770576 ALLEGRO_EDITOR INTERACTIV Design Partition - Place replication not working correctly. l4 p0 j, c4 M- x# q
777925 CAPTURE OTHER Capture crash immediately after invoking
" F% [9 i0 @2 p# _807089 FLOORPLANNER INTERACTIV Logic > Net Logic hangs tool in Linux2 _" s, t9 L+ w% a, G7 l( ?
809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs
8 G7 Q: b1 |* \; l6 U7 Z- b812046 CAPTURE NETLIST_ALLEGRO Design not getting netlisted in V16.3 due to illegal characters in pin nmaes3 Z/ `$ V1 G7 p$ T
814607 SIP_LAYOUT IO_PLANNER update genfeed to add options to dumbp all chips files from design3 a/ s2 w4 ]2 x
814750 ALLEGRO_EDITOR DRC_CONSTR BBvia and Microvia overlap DRC issue
* w* C( z U1 A1 ~! `815621 SCM OTHER Enhance time shown in session log to support DST3 r$ _; r2 z1 [& |% `% Y
815681 CONCEPT_HDL CORE The TOC symbol shows multiple entries for the pages
" X- j; R* J0 X/ E3 E/ b. Z817380 ALLEGRO_EDITOR DRC_CONSTR Incorrect or bogus line to line DRC errors are appearing between the nets of a diffpair
# P9 ?/ h$ x6 A( T6 {817881 APD ETCH_BACK Create Etch Back Mask failed2 I% W, L/ `5 {. y) u6 L9 b
820771 ALLEGRO_EDITOR PLOTTING axlLayerPrioritySet does not provide the same capability than the 15.7 Color Priority system5 J2 G$ L9 r. |2 b, f. v7 } i
820773 ALLEGRO_EDITOR INTERFACES Import 3rd Party Logic $SCHEDULE removes visible ratsnest from database when using T-Points: e( Y% Y* X/ V) g$ S
820792 ALLEGRO_EDITOR INTERFACES Import $Schedule command is returning illegal loop error for pin-pair based rules
/ q# @$ ?6 g, Z. Z, R+ X821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format& Z2 J* v" t( }! ]
821504 MODEL_INTEGRIT TRANSLATION dmlcheck failed when .dml translated from .mod was opened by MI.* I$ G* C- c. w
821827 ALLEGRO_EDITOR EDIT_ETCH Allegro Crash on routing Diff Pairs
0 i0 O" ~% ]9 ]6 _8 {821836 CONSTRAINT_MGR OTHER Why the min/max propagation delay analysis is failing for one of the pin pair in this design!# N% U6 B u/ K
822090 CONCEPT_HDL CONSTRAINT_MGR Crashed the Constriant Manager and SigXplorer from DE HDL
9 V2 e% x* \, q9 a5 K. k: o$ N+ A822744 CONSTRAINT_MGR DATABASE Xnet lost after DCF file imported into Constraint Manager
" _; K: ?8 d2 L G822827 PSPICE SIMULATOR Simsrvr crash upon running simulation/ _, r; P9 {- g$ n3 o
822844 ALLEGRO_EDITOR SCHEM_FTB Constraints are not updated in the brd file when working with Library defined diff pairs
$ u" B9 R4 l4 q4 B: k$ |- r822942 F2B DESIGNVARI Variant view does not show DNI on functions
" L, V$ @; l1 K/ K w6 h$ X823177 SCM BROWSER PPT_OPTIONSET_PATH defined using environment variable is not recognized by ASA
9 d( m: r# ]: H823200 ALLEGRO_EDITOR OTHER Import Logic hangs when dynamic phase control set/ F) P0 F3 Z& F7 }* |2 d
823589 CONCEPT_HDL CORE The operation could not be performed because no object on the drawing was selected
, S$ M) p4 O: Q- C h. a' v6 W823821 ALLEGRO_EDITOR MANUFACT Allegro crash when trying to Gloss -
+ ?$ a9 ?% \8 d G& F823833 CONCEPT_HDL CORE show vectors command
H' V/ E6 A+ [8 }! c824902 ALLEGRO_EDITOR DATABASE Lose connectivity when copied via and cline structure" [. {: B: D( `0 E2 h( w
825289 ALLEGRO_EDITOR DRC_CONSTR duplicated drc and waive drc! Y) D: j; ]: U1 F% D ]& { }0 p
825969 CAPTURE SCHEMATIC_EDITOR Refdes are getting reset after doing a replace cache/update cache for a generated pat7 Y; a: r8 E0 @
826068 ALLEGRO_EDITOR MANUFACT Adding Thieving on the negative plane layer doesn't show up
. n: J( o4 s7 U+ o. ~826266 ALLEGRO_EDITOR DRAFTING Datum Dimensioning Crashing Allegro in Linux8 @ D o1 H* F& x
827032 SIP_LAYOUT ASSY_RULE_CHECK SiP Layout crashes when running Assembly Rules checks3 a* o1 e; Z( P* r- ]5 q) V% b
827494 CAPTURE GEN_BOM Include file is overwritten for the STD Capture BOM if .txt file used as include file
! |& A0 \6 H7 C, k l827575 CONCEPT_HDL CONSTRAINT_MGR PINUSE
9 L. G1 m$ N `5 _827708 APD 3D_VIEWER 3D viewer assign black color for all layer+ }# f4 K# c' O- M* h5 a: \0 u
828263 APD DXF_IF When the DXF out is executed, offset of the padstack is not correct.' Y7 K M3 W" e/ w
828788 ALLEGRO_EDITOR DRC_CONSTR Soldermask Waived DRCs reappear in 16.35 V U, v! z" y( _( m
829046 APD MANUFACTURING create plating bar makes net name changed to dummy net
+ [+ c2 U" q3 W; ]# T0 R% V9 N829331 SIP_LAYOUT PLATING_BAR Create Plating Bar is deleting existing fillets.
% S9 p2 A) s$ h$ g5 d829336 APD OTHER Request the ability to merge two nets together into a new net.! M% r9 _7 y6 `
! R: [# `' [& h# k$ b% {( cDATE: 09-23-2010 HOTFIX VERSION: 0174 [4 Z; a" n( t/ m0 g+ ^
===================================================================================================================================7 S/ R9 Y- V( L9 K% q
CCRID PRODUCT PRODUCTLEVEL2 TITLE
4 i. a: F9 [2 R% J===================================================================================================================================
; w$ K6 i- M( f, I0 M676210 CAPTURE PRINT/PLOT/OUTPU Enhancement for correlate lower level pages with H blockes in PDF! N6 A; q! C: B
736942 ALLEGRO_EDITOR INTERACTIV Autosave is not working with every application mode.
9 d3 h. K& a/ g5 g0 G746256 CAPTURE ANNOTATE Intersheet refernces change their position in V16.3 even on unchecking ‘reset position’.
! O/ |/ p8 h% q+ p4 B. K/ i785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error/ X# `0 Q2 z5 _6 @2 R: c, U
791549 PSPICE PROBE PSpice cursor does not remember value outside zoom area
8 M3 q& [, n+ c802639 F2B DESIGNSYNC BOMHDL crashes if colon is used as a sub design suffix separator
5 c* @+ s1 l8 \* o1 O4 F. z804475 CONCEPT_HDL OTHER RMB+MMW doesn't zoom in/out anymore with ISR012
- N# I9 ?4 z8 `9 X/ H807025 PSPICE PROBE Loading dat file slower in 16.3 as compared to 16.21 d$ s' p4 N4 e- z K- O( o- A
808550 CONCEPT_HDL OTHER On Linux Import design does not obey umask or setgid settings
- ^ S ]5 H. [810568 ALLEGRO_EDITOR PADS_IN Can PowerPCB 9.2 - Basic file be converted to Allegro?& U T( C* L( U3 ]( \, L
812089 CONCEPT_HDL OTHER The colors on the Options form dont seem to match the colors displayed on the schematic canvas
: X7 P3 \/ c/ @" x/ |, ]812475 ALLEGRO_EDITOR INTERACTIV Saving .mdd always results in working directory
C3 Q) Y9 i( \" ^7 x% f# q O812836 CONSTRAINT_MGR DATABASE CM Custom Fomula -Handling of Pin_Delay is inconsistent in Analyze, P& h7 F0 A8 w
812994 SPECCTRA ROUTE Max_total_vias constraint not working correctly when wiring option is set to "starburst".
+ q3 r% _" U, [, i816561 CONCEPT_HDL CONSTRAINT_MGR OLECS.exe Runtime Error occures when attempting to launch SigXP from a net in CM8 G$ F+ N# S y( _( m, a
816879 SIG_INTEGRITY SIGNOISE Program has encountered a problem and must exit in 16.3 S014(v16-3-85AT).2 F' e8 b6 y6 F
817006 SCM UI SCM copy signal changes existing signal names+ B, S) b! G" X) E3 b, P6 L
817896 APD ETCH_BACK Etch back - improper use model
+ k2 k4 T: d+ I! O2 w818242 ALLEGRO_EDITOR SHAPE Thermal relief connections not orthoganal and creating acute angles.4 G$ U2 S& e2 y* ?( s5 t
818429 ALLEGRO_EDITOR PLOTTING Pins created from shapes do not plot solid.$ I$ l4 W, B5 Z3 A, C6 E. }
818513 F2B BOM Alphanumeric BOM not placing REF DES in proper order
1 e% L7 a2 {" D2 C- Z# e/ F818818 ALLEGRO_EDITOR INTERACTIV Place replication does not recognize mixed case characters in file path1 b' J H8 Q- T
818910 CAPTURE FPGA NC simulation flow is not working with 16.3 release+ o; g# F4 U& s# x) j
819108 SIP_LAYOUT DATABASE Wirebond profile constraints lost after saving and re-open sip
9 a2 A) u7 [ h" T819151 SIP_LAYOUT ASSY_RULE_CHECK ADRC is showing X-D DRC markers on good Soldermask Shapes when doing a min. shape check.
4 r2 S' X# H( b3 q% V+ c: G819183 ALLEGRO_EDITOR MANUFACT NC Drill file generated for Backdrill layers show wrong Quantity of the drills
+ p) E1 i. P( ^ t819269 SPIF OTHER File > Export > Router Crashes Allegro and dsn file creation stops
5 s1 Y4 E/ r- p4 S1 H819463 ALLEGRO_EDITOR DATABASE VIA has illegal connections.9 i4 t4 M/ _$ b$ e6 i$ C
819842 ALLEGRO_EDITOR INTERFACES File Import Logic fails on syntax check when following documentation for $schedule command! d& u3 [7 G. B7 A
820177 CONSTRAINT_MGR CONCEPT_HDL Net_class objects that are changed in CM at Front End are missing after Import Logic7 M3 M+ e+ k- E, v( n
820231 ALLEGRO_EDITOR DRC_CONSTR Allegro hangs when multi thread DRC is performed after updating padstacks
* t3 K/ i# i; w3 L K4 N+ S2 N0 V5 L820373 SIP_LAYOUT OTHER Update symbol flags the "edited pins" error but still updates the symbol and then crashes.
1 R( E: U! r6 ]: N820381 SIP_LAYOUT WIREBOND When opening a new design, with a design already open, the tool will use the first designs profile settiings
# c4 F6 q) C5 [+ [! J, S, d820634 CONSTRAINT_MGR OTHER Netrev fails without any useful message when importing ECO netlist
& h3 |$ a+ o) S+ |820665 ALLEGRO_EDITOR REFRESH Qvupdate is not working in 16.3 b' X7 y/ J" g8 |* \
820849 ALLEGRO_EDITOR MANUFACT NC Drill has wrong quantity and also a drill is missing
2 ?3 I* y! t8 k821154 CONSTRAINT_MGR CONCEPT_HDL DE-HDL CM Import Analysis Results fails without any feedback
5 @7 E7 D3 _; G" d821195 CAPTURE OTHER Updating Cache generates errors including CAP0027 on Capture DE CIS with ISR s0014 and onwards.
/ l7 w, ]% x. Q2 Q3 O( b821856 APD MANUFACTURING Create Bond finger Solder Mask issue
0 o7 H3 C+ R7 K821936 SIP_LAYOUT COLOR Can not clear custom color of bondwire profiles
6 @% T5 j0 z% L0 a$ [# | g: \822841 ALLEGRO_EDITOR ARTWORK An issue about Gerber6X002 n; y! Q; m( ^& ?4 C, @" X* N
822842 SIG_INTEGRITY OTHER CM and Show element report different lengths2 r1 m- V1 G( |- z l
823559 SIP_LAYOUT BGA_EDITOR When doing an Edit > BGA the tool will shift the BGA's position when at 90 or 270 rotation.7 ~+ M9 T2 C7 C% D4 o: b2 o7 {
823688 SCM SCHGEN Schgen changing the physicals bus name in the preserve mode for some of the bus
) x6 N5 T; i) N& _; }. ?: C9 x$ s) \823792 CIS OTHER Capture CIS performance over WAN for bulk operations are slow
' Q9 L# I$ Q$ @# f6 ^, I: i0 y) s! x X! M' A9 [7 i
DATE: 09-10-2010 HOTFIX VERSION: 0160 F% S4 ^2 \7 I
===================================================================================================================================% x# m" ?/ M/ [- @" c1 l
CCRID PRODUCT PRODUCTLEVEL2 TITLE! k. C `0 e$ V, X) H9 p: X$ q" s9 ]2 Q ]
===================================================================================================================================% B- M# l$ G2 V3 i" w C' S7 H
604662 VLS-L VIA When changing Rows/Columns values in Edit Via Properties form, different value are assigned./ e3 }9 [) C" V) a4 B4 O+ p' n: q
747191 PSPICE AA_SENS Pspice crashes when starting Advance Analysis: x" g6 n ~- v8 x/ [: R
756103 CONCEPT_HDL ARCHIVER Archiver does not include all the Parts when design blocks are copied from one location to another
, [- u+ b m5 h$ F$ `758487 APD 3D_VIEWER package substrate (BGA) outline should be on a separate layer, not on bottom conductor layer.5 d" `* S% C" ]: f' ^% i% {
764417 APD EDIT_ETCH Routing with Diagonal entry (45 degree) to Constraint Regions does not work
, E9 s) F2 M, a766409 PSPICE PROBE Copy to Clipboard changes the label text colors& w2 I5 ^# v' D2 y! z$ W
784577 CONCEPT_HDL COMP_BROWSER SingleclickAdd 'true' places does not pick the correct version
+ q" h( n+ u0 I784814 SIP_LAYOUT ASSY_RULE_CHECK accuracy of acute angle DRC
7 `+ C1 }, ^6 ?) H: Y4 A$ E! E- {792039 CONSTRAINT_MGR OTHER Doing a File->Import->Worksheet Customization from Constraint Manager will change the working directory.1 m+ {4 l4 |6 |9 E# ~$ P
796517 CONCEPT_HDL COMP_BROWSER Component Browser showing wrong symbol# w/ I o; k; H1 _& y. w
801944 SCM UI SCM dropping terminators and pull-ups when renaming signals (copy - paste special)5 A+ e% [5 C: D
804627 PSPICE PROBE Printet text labels have wrong location
7 f% _8 b$ B3 h& N3 c810479 FSP DESIGN_SETTINGS Not able to connect some peripheral signals to FPGA manually
, `5 }; N7 o) z810814 CONSTRAINT_MGR OTHER T-point does not create when import DCF file.' [/ S) a7 `; s: D3 p( y4 c
811032 ALLEGRO_EDITOR EDIT_ETCH Enable enhanced pad entry to support pads as shapes* y' P3 H9 {' b4 h0 L# D' {- l9 R7 n
812643 SIP_FLOW CONSTRAINT_MGR Physical Constraint values disappear after entering constraint mode
% E4 F; a- s8 t$ M8 {, e812835 CONSTRAINT_MGR INTERACTIV CM Custom Fomula - "Analyze" on the header of Actual does not analyze pinpairs4 I2 f5 q" l0 D
813435 SIP_LAYOUT DIE_ABSTRACT_IF Invalid parameter passed to ICP utility API: ?8 h* s! w+ H$ p6 x
814060 CONCEPT_HDL CORE Read only library becomes writeable when updated
3 q) s/ S" P+ ^! ?- |: j# t814347 ALLEGRO_EDITOR ARTWORK It seems like not work ”detailed text checking” on 16.3.4 h8 K, s$ u1 ?- Y1 e9 ~3 s/ M" n
814451 ALLEGRO_EDITOR DATABASE Allegro get crash when run dbdoctor
" c; \. }& a, c6 b" d4 ~814496 CAPTURE ANNOTATE Lower level part refdes resets to ?
4 g1 T, S, _) |! ^/ l! j815150 SIP_RF OTHER sip layout export chips output is not correct
' `% o/ x- @0 `; T# X816034 ALLEGRO_EDITOR MANUFACT Backdrill Passes not work from bottom' n. ~. l6 Y5 f: [: L
816065 APD DATABASE Export Libraries with no library dependencies selected creates package symbol without pins.5 _3 \! ]5 o9 k( l+ v
816426 ALLEGRO_EDITOR SHAPE Dynamic shape not updated when component is unplaced
8 ^ e. j& R+ W* g816616 SCM SYSTEM_OBJECT codesign incorrectly maps primary and secondary codesign object
% C6 n' }9 h& ^2 K5 S816686 ALLEGRO_EDITOR TESTPREP Probe Spacing rounds off 3 place decimal to 2 places8 x: k9 `! }; W k/ x: c" u
816917 SIG_INTEGRITY LIBRARY Issue for loading interconn.iml
# a6 x- l( H' g& ~5 h6 a+ S& J- [5 p4 X816986 ALLEGRO_EDITOR MANUFACT Mfg>NC>Backdrill analysis with passes set at Bottom layer is automatically switching to top, hence failing!
5 z. e' u$ w5 n5 O817473 CAPTURE NETLIST_ALLEGRO Backslash (\) is considered as illegal character for netname but it was allow in SPB 16.30.010
. x* |9 J6 v# H: |+ N3 k817606 SIP_LAYOUT WIREBOND When moving Bondfingers the Via's are sliding too when they should not.
5 ~/ X' |4 a& _5 p, d% ]4 H. k$ L; q
DATE: 08-27-2010 HOTFIX VERSION: 015
" R$ M# X8 B8 x# h( l6 o! Z# ~6 j===================================================================================================================================
# C" Z4 n) `8 ~ H( E7 dCCRID PRODUCT PRODUCTLEVEL2 TITLE5 I; v( [. _6 T$ I9 L3 h( l2 T
===================================================================================================================================; `, O, U1 P0 Q9 j Z
664821 CAPTURE NETLIST_ALLEGRO Improve error messages when netlister finds illegal characters in the pin names
8 h' v/ L U, q4 U753867 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV crash when graphics from one symbol to another
' H- e y9 e* q7 L% [+ V& V4 j8 x0 t777559 CAPTURE OTHER Why the Reference designators get lost in project with external references.
+ D$ @8 z$ n( l+ V777657 CAPTURE PROJECT_MANAGER Archive Project causing Capture to crash
: v: k/ r' \7 Q5 A7 _5 e785748 SIG_INTEGRITY OTHER 16.3 SI model library path directives behave inconsistently if the ~pcbenv/env file is present: V7 j* w5 G/ ?+ o1 n
789529 ALLEGRO_EDITOR EDIT_ETCH Neck Gap changed to Primary Gap when executing Delay Tune command.
' x. p; x7 z" p$ q: m T791853 SIP_LAYOUT EDIT_ETCH via slide clips to 45 angles near BGA
8 t( y, u4 w& o796604 MODEL_INTEGRIT TRANSLATION ibis2signoise replace V_fixture_min with V_fixture_max based on the value.
2 h0 p7 B& O; c8 ?2 i2 ~797657 CONSTRAINT_MGR CONCEPT_HDL constraints from the brd file are not passed on to the schematic.
4 n+ s0 Y1 n9 v802760 ALLEGRO_EDITOR NC nc route not generating the circle correctly5 Q3 K$ m, K2 j9 x' I
803572 MODEL_INTEGRIT TRANSLATION quad2signoise fail if MODEL name include backquote.9 b& {, `$ g2 W, k$ c
803869 SIG_EXPLORER OTHER Trace parameters form does not update with correct stackup data9 ]. \( C6 f3 {( L0 r3 _
804070 ALLEGRO_EDITOR SKILL The skill setting objects not match to all items in CM.
( Q" \. v1 F- M/ _$ H. r805641 ALLEGRO_EDITOR COLOR Clear all nets fails to remove the custom color on the Color Dialog form
) F) s- D* Q8 I- H" U806115 PSPICE MODELEDITOR Cannot generate a Capture symbol from Model Editor because no Capture license.
6 x. X% g% e/ ?, E- W. V806196 CONSTRAINT_MGR OTHER Netrev fails with warnings.
5 E3 ~0 K6 x- X+ ?* {1 q806864 CONSTRAINT_MGR CONCEPT_HDL "Selected nets/xnets only" option in CM connected to DE-HDL
. x' `* K8 O3 e( o6 q; i807960 ALLEGRO_EDITOR COLOR Click OK to Color Dialog box and Shadow Mode ON/OFF setting will be lost.' S* k/ ^; P( m4 P% @
808155 F2B DESIGNVARI Variant Editor variant.lst and BOMCompare not the showing the same data0 ?; \1 Y/ H- O9 R+ a
808392 SIG_INTEGRITY OTHER Cross section impedence not calculating for SPB 16.3 with single license for OrCAD PCB Editor" Q4 x* b- r; Z7 `% y) `
808978 CAPTURE STABILITY Unable to Place > OLE object > Visio drawing file. Capture crashes as well
4 p( |2 g: \9 Q9 R7 J8 u( W809163 SCM PACKAGER scm crashing when running export physical! L7 v5 q% Y0 P" t
809526 ALLEGRO_EDITOR DRC_CONSTR multi-thread DRC hangs when replacing padstacks+ g9 Z2 g* R" w- e
809587 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV crashes during Text Cut/Paste operation in Symbol Editor
; n! v- N" Q- M. P0 l809636 ALLEGRO_EDITOR DRC_CONSTR drc update reports incorrect DRC count when run after deleting unused region in constraint manager.
/ @; k& i( p: L/ P. R% k9 m809847 PCB_LIBRARIAN CORE "Auto add SWAP_INFO to chips" problem. q3 P. t7 E9 v( F
810024 ALLEGRO_EDITOR SKILL axlGRPDrwText does not work for left justification
) ?& V& b# m5 c+ h+ j! E810530 ALLEGRO_EDITOR EDIT_ETCH Sliding vias on differential pair is not selecting both nets: o( Z; g5 _6 ~9 E6 c' S6 S
810860 ALLEGRO_EDITOR DRC_CONSTR Improve Update DRC efficiency+ B4 ?* E, a/ ^5 @
811506 CIS ICA Using Capture V16.3 ISR0013 “Save Schematic Part” option is missing in "New Database Part Wizard".
" z7 o* a8 e2 R/ z& l9 \812259 ALLEGRO_EDITOR SCHEM_FTB scm crashing when running export physical- AGAIN
, x9 K2 I: X" d: E' o7 H0 g) L812269 APD WIREBOND Wire diameter and wire profile automatically is changed when executing wirebond add command
/ B) m! |% } k- |6 s3 p$ O& s8 |812597 PSPICE SIMULATOR Pspice crash.2 T: b. I, c& s5 K* M% i
812655 SIP_LAYOUT IMPORT_DATA Importing Stream data multiple times into a .dra will have inconsistent results, each import is different.# o; o$ B" f* f! n$ ]' y4 A5 V
813253 ALLEGRO_EDITOR DRAFTING Datum Dimensioning Crashing Allegro5 @6 O4 B1 @/ O# j5 k
813265 APD WIREBOND Wire Bond Report fails with wires present that were added with the "Add/Edit Non standard" option./ I* k- _2 k* r, U
# z6 v3 q7 S. f9 @! L) n; s$ o
DATE: 08-13-2010 HOTFIX VERSION: 014
3 U0 B: G3 e* @6 y+ [===================================================================================================================================
! I6 g9 ?& ?1 X9 I& kCCRID PRODUCT PRODUCTLEVEL2 TITLE/ Q& X* a8 W( B
===================================================================================================================================' f2 Z1 O; D+ n
792354 CONCEPT_HDL CONSTRAINT_MGR Viewing a second net in SigXP from Design Entry HDL constraint manager generates an error5 p; ~ Q& W" E" o! c6 a( |- p& q
800336 GRE CORE GRE's Plan Spatial crashes Allegro.
8 t# T% {0 a1 [4 w$ ~801116 SIP_LAYOUT WIREBOND Wirebond -> change characteristics with only wires selected should not modify connected fingers' placement at all.( T- V- D0 [: E9 h2 t- f( e& _
801463 ALLEGRO_EDITOR EDIT_ETCH The Allegro axlShoveItems SKILL function behaves differently in 16.3 than it does in 16.2. ]4 G H9 l$ T. o9 Q+ r+ u% F% Z
803049 MODEL_INTEGRIT TRANSLATION quad2signoise cannot translate OpenDrain Model correctly.8 U+ N3 V* r1 D# k0 J- t2 [
803878 ALLEGRO_EDITOR DRC_CONSTR 'Via_At_Smd_Fit' not working correctly when the via fully covers the pin.) x" o+ j, y9 K4 `; _$ S+ q4 s
804273 ALLEGRO_EDITOR DATABASE Running update DRC gives different number of DRC.
8 v; s1 J) R& o7 y# b/ B" h. i804330 F2B PACKAGERXL Packager is changing the refdes in preserve mode for components in hierarchical block
# Y1 s L( n# @3 W+ J! a805335 F2B PACKAGERXL Packager fails reporting empty location values when the location values do exist' f! D) T" \) d# P4 P2 v
805676 ALLEGRO_EDITOR DRC_CONSTR Update DRC hangs while updating differential pair checks with dynamic) ]# O$ A' K2 e G! z
805747 SIP_LAYOUT EXTRACT Extracta crashes with this testcase and command file.
% P. w: b8 ~ a1 L0 A7 a' _806028 ALLEGRO_EDITOR TESTPREP Allegro testprep parameters causes crash. D! c- ?4 \- F7 B6 J8 r
806120 PSPICE NETLISTER “Enable PSpice AA Support for legacy" option results to undefined errors
]. a2 [9 T$ H; U1 g806182 ALLEGRO_EDITOR SKILL axlPolyFromDB will crash if object is a pin on an unplaced component
" t& U& s/ X" F5 _3 D, V/ n$ o807543 ALLEGRO_EDITOR DRC_CONSTR Via at SMD Thru DRC not working correctly in Solaris
6 M# I# W7 v- N1 `808047 SCM SETUP scm not loading all parts from pcb after running brd2asa
8 l) G" M2 ^% F8 }808831 ALLEGRO_EDITOR DRAFTING "Oops" command(in dimension angular command) crashes Allegro.
/ Q0 B: Y) Q4 L* _6 r( s8 w- D# r' w F' F: x6 r% o |
DATE: 07-31-2010 HOTFIX VERSION: 0132 v0 y5 F$ D0 m# C# f
===================================================================================================================================$ j5 v( [9 k' `% i
CCRID PRODUCT PRODUCTLEVEL2 TITLE
+ q- ?+ c( k/ c/ C7 [- L& }===================================================================================================================================' @8 C/ s5 \ X( j& a9 M
576133 CAPTURE ANNOTATE Annotations in the design getting reset to ?3 _ M3 H6 [$ o# u" _6 |/ W
688692 CONCEPT_HDL GLOBALCHANGE Global Change does not respond to RMB> Done
% ?& n' d2 _1 a! h: x8 A/ X* ^731045 CIS EXPLORER Double click in CIS explorer places two components
7 V3 K- a/ i# y( u' T5 Q763550 CONCEPT_HDL SKILL nconcepthdl in 16.3 no longer recognizes skill functions that worked in 16.2
" z. {& o/ x4 i/ _( `3 E0 u7 R) t764130 CONSTRAINT_MGR OTHER Export Excel from CM hangs/crashes Allegro on attached design- p) Z( p+ @3 w, C/ N
766750 ALLEGRO_EDITOR INTERACTIV Request to enable datatips when constraint manager is open and a command is active
) N7 h; W6 J Y$ Z8 d774466 CAPTURE CORRUPT_DESIGN DSM0008 - Unable to open design in 16.3
4 e. r0 k$ r2 X777862 CIS PLACE_DATABASE_P Absolute path in field Schematic_Path causing incorrect display property
* a4 e+ |4 m0 G K782370 CONCEPT_HDL OTHER CreferHDL $XR hyperlinks do not work in PDF Publisher - they did in SPB16.2
- q. {0 h2 l/ a" E' g. H783036 SIG_INTEGRITY SIGNOISE Problem for Waveform saving with -w option in signoise command.7 {+ V' ^0 o; f" B( t
784205 CONCEPT_HDL CORE Schematic block generated from SCM needs to have DIFFERENTIAL_PAIR property on the ports
, ` a* q% s2 `, J* o786387 CAPTURE OTHER Update cache does not update the parts on schematic3 N# F& |/ v3 \& ]4 ]
786560 CAPTURE NETLISTS Sqare bracket [] is not allowed in PADS netlist.9 W4 K3 H/ e' Y6 k( \+ e& D: m6 @
786808 SIG_EXPLORER OTHER RMB > Via_Model_Name doesn't display the generation param of the via.8 X0 G8 g: D' {: M& R3 ?: }+ K, c) C+ {* o
787414 CAPTURE PROPERTY_EDITOR Part value can’t be moved on schematic if a part has been copied to a new design and not saved yet.
3 n1 W/ h% K9 S2 X6 q. x* Z [ z791965 CONCEPT_HDL CORE group move should not snap to center of group- P# u X! l7 Q9 `1 O
792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets
; e, J' p2 m; H& u; ?9 F _; C% S794900 CAPTURE NETLISTS Attached design is not getting netlisted in V16.3. It works fine in V16.2# o6 E& S4 u$ H+ F- |, f4 O0 p$ n
795914 PSPICE SIMULATOR Getting RPC Server Unavailable Error
" H9 n l* c, g( g8 k5 @7 g, H795997 ALLEGRO_EDITOR TECHFILE crash when importing dcf file
6 n$ }5 [; _& H2 S& c# x796124 CONCEPT_HDL CORE Messages overflow console
$ W& m) m( C! I1 x: v796168 CONSTRAINT_MGR CONCEPT_HDL Create ECSet in DEHDL CM moves focus to DEHDL
3 @! J. |' N0 }) ?) {1 \796378 ALLEGRO_EDITOR PADS_IN Pads_in has error while translating PADS 2007 asc file
$ D d1 Q5 l. R5 W4 A. _/ z796658 APD OTHER Allegro can not import the property section of 3rd party netlist correctly.2 l. l7 d: Z% r: l3 u5 w4 l
796926 CONSTRAINT_MGR OTHER Importing Custom Worksheet file does not overwrite the Description field./ T- I' S) c1 _9 x) r4 h' S) w
797387 SCM SCHGEN Increasing the grid units from 25 to 100 breaks the bus into bits on the generated schematic.; z$ y6 {5 x: G2 ^" W
797529 SIP_LAYOUT IMPORT_DATA import BRD to SIP fails if database has partitions. even if only silkscreen and documentation exist9 c6 X4 _2 f# V' t4 H
797634 SIP_LAYOUT DIE_EDITOR rat control buttons in edit die mode are invisible until user selects an action- W* K5 c( C$ q; \0 E/ L& I
797663 SIG_EXPLORER OTHER Current probe could not get from sigxp left symbol panel.
# h9 i9 g0 e0 A: y/ n& s7 f798118 SCM REPORTS SCM report not resolved with CCR 697709
3 p7 p E5 [. h8 I798464 ALLEGRO_EDITOR SKILL axlDetailLoad not filling shapes in 16.3 s10! c( r1 i. W5 Q3 I* S2 U9 z
798980 ALLEGRO_EDITOR DATABASE Unable to open board file as it fails with a error message Found bad data pointer, run dbdoctor.; S" B' w" f0 f/ C, v
799445 PSPICE MAG_DESIGNER Magnetic Parts Editor crashes while saving newly created Magnetic component
0 A7 l; [% b! G799539 CONCEPT_HDL COMP_BROWSER PPT Options settings lost when cancel done in PPT Options form b; W- b9 ?, K9 [' W4 ~
799957 CAPTURE CORRUPT_DESIGN Capture crashes while doing save as in 16.3
0 A, {& k* Q0 t# M: n9 g800280 SIP_LAYOUT WIREBOND Swappoing Dies in the die Stack will cause the bondfingers to move and create DRCs% W, l, n5 {4 p
800542 POWER_INTEGRIT SIMULATION Multi Node Simulation does show actuall waveform# \) E0 O+ g, q6 p: D4 b
800695 CONCEPT_HDL CORE Genview changed behavior in 16.3 HF 11 breaking the design hierarchy+ K& V/ d/ _: R6 q; m9 Y
800751 ALLEGRO_EDITOR DFA DFA placement does not understand package keepout
1 O: {% `# A( Z$ {# g801017 ALLEGRO_EDITOR REPORTS APD Crash when creating Unused BB Via Report; @% z( |6 J; j4 X" |; Z" z* h
801043 SIG_INTEGRITY OTHER SigNoise Case Update seems to check ActiveDesignLink value incorrectly.2 _% z( {3 C& m+ ?3 }4 x, W
801433 ALLEGRO_EDITOR MODULES selected figures do not end up in the module& o) Y& N4 F7 E
801705 ALLEGRO_EDITOR SYMBOL Shape symbol was specified with RegularPAD of the PAD stack become "Null".
# m3 _& K) h+ W9 S1 _; l( l802319 ALLEGRO_EDITOR SHAPE Shape status cannot be changed to smooth using suppress pads.0 @3 v1 m* ]+ T, U9 ]
802474 CONCEPT_HDL LWB-HDL Testbench generator not working in Linux6 D$ O5 G; J/ p; n: L
802887 ALLEGRO_EDITOR OTHER Adding the No_Shape_Connect property to via causes the application to crash.1 O$ ~0 ~7 k7 ~! L8 a
803393 SIP_LAYOUT DXF_IF Cannot generate a dxf file
1 f5 E4 Q" ^) E" k4 }) y7 v! _9 |4 N% q
DATE: 07-16-2010 HOTFIX VERSION: 012
& p `" P6 G8 V9 |" U# R( A===================================================================================================================================
! g: D$ Z8 k; q3 QCCRID PRODUCT PRODUCTLEVEL2 TITLE1 p- T: `- p( L7 A, p
===================================================================================================================================2 T- U9 P* W# z; v& N5 H
757157 CONCEPT_HDL CORE Zoom (using SHIFT + mouse wheel) to work such that the tool zooms based on cursor location, Z' ~4 e U5 H' D& D3 d# v
766639 ALLEGRO_EDITOR EDIT_ETCH via structure disappearing after selecting place manual hide icon.8 a" b0 {. i! h2 B; H. X
770910 PSPICE PROBE Printing from probe yields text label with too small size4 f3 M: ~) f9 p
773603 SIG_INTEGRITY SIMULATION The characteristic of S-parameter model is different.% {" ?7 _6 z, H% J
774363 CONCEPT_HDL CORE hier_write didn't report error.
. ]0 q7 H2 w1 ]776991 CONCEPT_HDL CORE The Wire> Bus Name command does not use the Net Name font setting
5 u3 R& t0 N! y781965 PSPICE PROBE Unable to add trace expression with small letters4 Y1 B9 H4 e9 z4 u. s% A- o
782847 SCM PACKAGER PKG-10002 - Cannot associate a logical part from chips.prt
: H) W& ~3 o2 O* b783245 SIG_EXPLORER EXTRACTTOP extracting net with trace on plane layer giving unconnected topology/ Y j& e: L; t7 ~1 o w
785320 LAYOUT TRANSLATORS L2A translation fails with error "output directory is not writable".
$ u$ q. V* p) k785401 SIG_INTEGRITY OTHER The "View Geometry" or sigxsect command is not working in SQ 16.2
! q6 |, q% H- H6 p# D785715 ALLEGRO_EDITOR PADS_IN PADS_IN fails to convert some components on Bottom Layer and adds two components at same location
. T+ c* L. B2 Y785868 SIG_INTEGRITY OTHER Unable to generate Parallelism report as the report seems to have hung the SQ Session.: \5 Z/ t9 \8 O& W
788523 CONCEPT_HDL CORE selecting QuickPick toolbar button should not reset canvas zoom5 U7 ] P& A6 R) M6 ^5 v. p
789333 CONCEPT_HDL CORE Font colors not being used as set in the SITE .cpm file. V% i5 b. Q( [# G$ C; M
789348 ALLEGRO_EDITOR EDIT_ETCH Via Structures removed from database when switching to any App mode from Placement App mode: H( |1 r2 \/ s, s0 |0 c. I
789473 SIG_INTEGRITY OTHER Via delay is not included when t-point is at the via- A* _4 \3 b; C. V! H
789744 ALLEGRO_EDITOR SHAPE Update Symbol with cline at symbol level do not connect clines properly) H- b4 r# p+ z9 B& e9 ]6 Q/ h$ w# Y) u
790170 F2B DESIGNVARI Function of Variant Editor and Annotate schematics
0 M" d$ F# L* P790811 APD ARTWORK Some Void shifts by the artwork output.
" K' N0 Q% d$ C' |791371 ALLEGRO_EDITOR REPORTS Dangling line with cpoint not reported in the dangling lines report.
+ v- v6 u7 F0 h% M' z8 s- e4 r- q791486 CAPTURE PLUGIN_INTFACE Unable to open a PSpice Project by double clicking the .opj file, if Capture is already open/ W. f& @; R2 s& q8 _6 L# s
791663 CIS RELATIONAL_DB Relational view doesn't appear when capture opens second time
: I3 a4 e, }* D: ?791690 ALLEGRO_EDITOR EDIT_ETCH etch editing/routing in placement mode, allegro looks for all libraries adding delay in routing.8 c3 w7 Z; u% u. p1 b; q
791720 ALLEGRO_EDITOR DATABASE Color Net param file does not have some nets with special characters in the Net name.
6 ^% j2 |5 B1 H5 U791987 ALLEGRO_EDITOR PADS_IN PADS Translation fails with no error message
3 D% m$ V) `1 C; {9 K) E# n792232 ALLEGRO_VIEWER OTHER Import parameters not bringing in plane colors in allegro viewer+ A- }: Q7 a+ `& {6 ]$ I! F4 x
792559 ALLEGRO_EDITOR DATABASE Error when executing refresh symbol command. }. m& M4 x, X9 w! t2 H
792923 ALLEGRO_EDITOR OTHER sted fails Can't open STED stroke file ~pcbenv/allegro.strokes% j# K! o) g( Y' x( f# ?
793358 SPECCTRA PARSER When I try to invoke Allegro PCB Router it fails to invoke with errors.
+ R/ [8 u/ E% _$ \- q9 L* {793605 CONSTRAINT_MGR OTHER Importing custom consmgr.wcf file crashes Allegro., F: o% o' u) y
793955 ALLEGRO_EDITOR DRC_CONSTR add connect launch signoise even so electrical drc are all at off
3 y1 K: z9 m; O. T) O& y5 _6 @2 t794748 LAYOUT TRANSLATORS import fails with message not valid Allegro subcls
2 F' O" O: g* N' h8 d. a2 P/ K2 R794775 ALLEGRO_EDITOR SCHEM_FTB Import logic runs forever or get a netrev error without any explanation
9 ^( j) b5 i. H; y! i" \8 E795261 CAPTURE NETLISTS Create netlist hangs in SPB16.38 q8 |" F& g1 v: m( x
795364 CONSTRAINT_MGR OTHER bookmarks are not getting saved in CM
" s! H4 z# G$ F8 ]: p795410 APD BGA_EDITOR Using the Edit > BGA tool I cannot get it to modify the pin numbering of a BGA
* a; H. z3 S* [% Q) v& s* ?795501 PSPICE PROBE Unable to see the Multiple Mark-Labels in Probe2 ^" G( O2 `- b+ A& @! P% [- d2 F
795761 ALLEGRO_EDITOR DRC_CONSTR Design is crashing while executing Tools > Update DRC: E% V6 M; w. |* |' A
795770 ALLEGRO_EDITOR DATABASE void moves when upreving from 15.7 to 16.3+ U2 l8 o l+ S% |
796026 CONCEPT_HDL CHECKPLUS CheckPlus reports text overlaps inccorectly on Linux
( {; B: V8 D/ i# t" r796092 MODEL_INTEGRIT TRANSLATION ibis2signoise crash if Submodel section exist next to Component section.9 n( O' G% c. i3 F' Q
796361 SIG_EXPLORER OTHER When dml file is loaded "Illegal format in device file" is outputted.) ^8 c: D$ a$ X% u$ J
796366 CONCEPT_HDL CORE UI windows in DEHDL are scattered* b2 M" S! m0 J. ?5 V
796590 APD DRC_CONSTRAINTS CM Hole Spacing rule always set to 1905 in a new design., G2 z; q! r L# u. \
796858 ALLEGRO_EDITOR DATABASE Deleting layers that has only vias moves etch from other layer on it and prevents the layer from being deleted.4 P3 b( ]" \! \$ G: ^
9 ]! l( ]: q; z/ Y$ H
DATE: 06-25-2010 HOTFIX VERSION: 011* c n! v3 H. Z! M
===================================================================================================================================
* c6 H, D S L/ ?- YCCRID PRODUCT PRODUCTLEVEL2 TITLE
, d/ }5 r5 |( d+ B===================================================================================================================================7 I6 j& C7 N* C/ U/ [8 E9 ?
644128 ALLEGRO_EDITOR MANUFACT Enhance Backdrill for HDI Buried Vias3 u( [' l- [* ]0 U! B
743746 ALLEGRO_EDITOR MANUFACT Sub-laminate back drilling -Arbitrary from-to layer drill capability needed
: P- t0 i4 X- e: P& e6 Z773066 CAPTURE EDIF PinSwap information written in EDIF does not back to Capture schematic
6 V- u; g& {2 Z" t( U' \8 \& J775690 CAPTURE STABILITY Design is not properly translated in 16.3
, m$ n0 w! d: A& ]9 P% d782854 ALLEGRO_EDITOR COLOR Component Keep Out for the Top & Bottom layers not showin in the Color Dialog box, only ALL shows.
' n! `% j0 O4 \0 M& u784439 SIG_INTEGRITY OTHER CM of 16.2 recognizes the differential pair nets as Xnet.
# Z& S6 X" i: L' i# e785135 CONCEPT_HDL CONSTRAINT_MGR Applying an ECSet to a diff pair crashes Constraint Manager
- \5 m% v, K. ]1 Y% }5 C* K/ S* |785179 SCM OTHER Changing a differential interface signal to local corrupts the con file and ASA is not able to load6 x0 `; O& [. i; X
785332 SIP_LAYOUT LEFDEF_IF unable to def in to sip layout
( j. i9 f/ z, g785423 SCM SCHGEN Schematic having incorrect connectivity& e$ M w J; |
786858 SIG_INTEGRITY SIGWAVE want to select license at launching sigwave& K* P# {/ V+ X6 X u5 j" ~
786871 ALLEGRO_EDITOR SHAPE Allegro dynamic shape not updating8 [. r) x- G8 b( |# D: [7 Z9 d
786957 CAPTURE MACRO If an off page connector is renamed using macro the net name attached to it is not getting changed A/ W' n' ~2 O* B1 Y8 i
787003 CONCEPT_HDL CONSTRAINT_MGR olecs crash in CM when rename librray defined diffpairs on this design.
- |$ w3 J4 D# t1 ?4 i2 T0 m787087 ALLEGRO_EDITOR DRC_CONSTR Diff pair Static Phase tolerance Error
& e* k$ B+ j& M+ n( ]787174 ALLEGRO_EDITOR MANUFACT Reading filmsetup.txt file crashes Allegro8 s% y7 N3 w/ |% z
788521 ALLEGRO_EDITOR DRC_CONSTR There is a difference of DRC between SPB16.2 and SPB16.3.& T) _- a8 U a/ P8 Y4 g8 {. e/ y
788652 F2B DESIGNVARI Variant Editor cross highlights incorrectly to Concept2 n2 O* l# \" D$ g* X
788658 CAPTURE NETLIST_OTHER OrIntegra.dll netlist has inconsistent behavior
: z$ |: X$ }. K- A4 _4 l788718 ALLEGRO_EDITOR DATABASE Board crashes upon deleting Cline segments within BGA using Allegro PCB Design XL License.
. j7 [) I4 ~* L# s3 f789206 ALLEGRO_EDITOR SYMBOL Merge shape option causes attached *.dra file to crash) G* \* ?$ X" r6 o/ }
789324 CONCEPT_HDL CHECKPLUS CheckPlus output producing wrong values
! |' u$ ?' N$ v4 q& Y790049 SIP_LAYOUT EXPORT_DATA Offset wire tack points disables wire in AIF Output
+ @( x; ]" Q% s: o0 t2 t790503 ALLEGRO_EDITOR SHAPE Shape Void not correct7 i1 v0 x5 n- t% J
790567 SIP_LAYOUT TILING unable to run the ndw tile die generator
! P& {: \, A4 ~0 J; P790622 ALLEGRO_EDITOR SKILL line width of internal segments within hatched shapes not correct when created using SKILL
9 N/ q! ?" v& D! k& m4 i( _0 w791075 SIP_LAYOUT EXPORT_DATA The shape that connects Merged Bond Fingers is missing in the DXF output.% b) o P) t0 C( C
* w5 M% n2 j8 U+ T' j% @* {, BDATE: 06-11-2010 HOTFIX VERSION: 010/ s4 {* T; O7 W/ [0 H4 o# g
===================================================================================================================================( L9 M& G: b' {- k/ K
CCRID PRODUCT PRODUCTLEVEL2 TITLE
8 k, o x: Y& _1 \' W===================================================================================================================================
3 O, p- Q( A# ]+ S/ N; v4 c3 ]701724 CONCEPT_HDL CORE Page Down (PgDn key) Key is unresponsive) I4 A: k" V4 ~8 Q0 V
722773 ALLEGRO_EDITOR DATABASE How can i add DUMMY NETS to a Net Class ?
x- o N9 N7 @" H9 s767874 ALLEGRO_EDITOR OTHER Component Geometry/Pin number not imported.' P4 P" m I/ `: m9 s6 V5 Q
769644 ALLEGRO_EDITOR SCRIPTS Why Command line script in non graphical mode prints everything to the screen when working with Windows?
& {' ^- g |6 G- a3 Z9 @0 `( I778086 SIG_INTEGRITY SIMULATION extracted net yields unrealistic resuts +/- 100v swings! ~% s S, ?3 _4 O: D8 u+ a
778915 ALLEGRO_EDITOR OTHER Export library dumps symbols with mechanical pins instead of connect pins
/ ]( |0 G) B" i2 N; n- g) X* a779119 PSPICE ENVIRONMENT MC Analysis does not seem to honor Custom Distribution$ o$ Y0 l: N* b- |5 L# U
779161 ALLEGRO_EDITOR OTHER Getting error-"illegal arguments passed to a dba routine" when connecting CLine to via
5 J2 V' [- a9 X; V+ ~# o# Y779335 SIG_INTEGRITY SIMULATION HSPICE sim from PCB SI caused netlist error.
. E7 F$ x% s! K7 U. `780314 SCM UI ASA crashes on paste special.! W0 h) [4 H, Z9 @
780345 CONCEPT_HDL CORE Pins look garbled when part is vertically mirrored
1 T' E# U' ^* i5 ~5 B- k9 m: {+ H( R780811 ALLEGRO_EDITOR SKILL Request 1k limit of SKILL API be removed." O6 t/ M5 N* o: ^8 _) @7 r
781111 SIP_LAYOUT IMPORT_DATA Import Brd to SiP failed
3 O/ v- O/ ~ y6 j781259 CONSTRAINT_MGR TECHFILE Import tech file crashes Allegro
0 w$ M g( b7 O8 {/ V G4 _781287 ALLEGRO_EDITOR DATABASE dbdoctor removes tespoints from odd angle clines leaving V/L drc
3 l' h6 S2 D7 d7 K( M+ D7 e! Z781331 ALLEGRO_EDITOR SCRIPTS Script executed by command redirection operators is giving different o/p for v16.01 and 16.3
2 x' u0 u6 W# N6 V# K781647 ALLEGRO_EDITOR MENTOR mbs2brd is defining extra additional testpoint that is not present in Mentor database8 a5 t( |0 y( g+ _# D; ~
781650 ALLEGRO_EDITOR DRC_CONSTR Update DRC hangs while updating differential pair checks with dynamic phase tolerance added from the logic import
. U d! R% `6 ?! E1 c781665 PSPICE DEHDL_NETLISTER Error simulating delay component
! d0 U( r! f/ n6 r- A781688 CONSTRAINT_MGR ANALYSIS Application hangs on Solaris when executing DRC update" d$ f$ K v! Y3 a# R
781799 ALLEGRO_EDITOR OTHER Unexpected results when exporting and importing text parameters% H% X9 [9 [5 ^
781922 ALLEGRO_EDITOR SHAPE Pin doesn't connect as a thermal.0 z3 `1 }# V6 g/ r9 A/ s, F) Y
782124 CAPTURE PLUGIN_INTFACE Bias point display not getting updated for projects on network4 N3 o, ~& Y4 h; K- \4 L
782415 SPIF OTHER File > Export > Router takes 5 hours to create a .dsn in windows....1.25 hours in Linux.
: d% O' b( q# S9 w782566 ALLEGRO_EDITOR PLOTTING It seems like not work PLOT parameter "Auto Center" on tight paper size.4 S* ?; J7 |0 F" f7 a, s/ \
782628 SCM NETLISTER Connection change not updated in the Verilog Netlist( n7 J4 L0 X8 y* b9 r+ e
783059 ALLEGRO_EDITOR DRAFTING Create Detail with "filled pads disabled" doesn't work with irregular shape pad.
# d% C: d$ L- E' K% j5 A4 T783142 SIP_LAYOUT IMPORT_DATA import bga text in on connector crashing sip layout
7 q% m C: V6 V a! ?9 m. Z$ W783222 FLOWS PROJMGR Edit Physical and Spacing constraints9 B: {+ F) D" b7 F. h
783241 ALLEGRO_EDITOR PAD_EDITOR Pad Designer hangs when attempting to save to file.1 H& | U3 o) F' H6 [2 Q
783283 SCM IMPORTS scm crashing with import physical) {# d' P* `) S `
783301 SIP_LAYOUT WIREBOND All Bondfingers not sliding along path.5 U7 w2 z; U2 x3 S
783496 ALLEGRO_EDITOR MODULES Problem of module placement.
2 N, H* Z+ H9 d0 l0 Z. u5 @$ z. x783813 SIP_LAYOUT BGA_GENERATOR Request to add new JEDEC BGA sizes to the BGA wizards standard JEDEC pulldown menu.
5 y, I) x" X4 }; z' E784441 APD OTHER Users cannot delete layer even everything was deleted
' e. Q9 P9 h( X784639 ALLEGRO_EDITOR DATABASE both dbdoctor and allegro are crashing while opening this database* r0 P5 a( F/ H+ j% ~
785100 CONCEPT_HDL CREFER Cross Referencer must not call Unix command on Windows platform+ n v* k; C8 i Q. x
785385 ALLEGRO_EDITOR MANUFACT Allegro Crashes when using Datum Dim with Shapes.4 ^7 Z# } L: a( G( R
9 N! P( i5 p' y2 _5 F' G
DATE: 05-28-2010 HOTFIX VERSION: 009+ U4 I! b3 H0 D: O9 ?
===================================================================================================================================
* k$ B' U, i' a! Q% m* d( e6 pCCRID PRODUCT PRODUCTLEVEL2 TITLE8 l! N4 H. x; H
===================================================================================================================================
7 i# ~3 s& \, I: i758913 APD OTHER uncheck default check buttons through options/preferences
5 H' l4 w) [5 Z) o3 w6 v, _763566 PCB_LIBRARIAN PTF_EDITOR The ptf command in batch mode always returns "abort"
" P- z; Y4 m0 V$ F3 V* L# D763662 ALLEGRO_EDITOR INTERACTIV Place replicate update creates numerous DRC on win platform, c9 x5 m4 L) W, b
771088 CONCEPT_HDL COMP_BROWSER QuickPick adds incorrect property value when ppt optionset file is used* i: ?9 Y+ ]% a6 l7 |1 B
772285 MODEL_INTEGRIT GUI Model contains recursive calls fater port rename reorder funtion is performed on it., ?! N S: r1 h4 y3 A
774070 ALLEGRO_EDITOR DRC_CONSTR Allegro crash when sliding connections.7 m) c* I, O& r d- u
774880 ALLEGRO_EDITOR INTERACTIV Place replicate stops with No available buffer identifiers.2 u3 M! b- z( p
775443 APD EDIT_ETCH The routing of DIff Pairs when transitioning from a region needs to be smoother.6 ~+ ?2 Y" I2 ~# r7 a
776022 ALLEGRO_EDITOR INTERACTIV Allegro crashes when we use Ctrl+Click in Etch Edit mode for selecting a Cline Segment in Allegro PCB Design L
3 m- B! q# _# q: a776151 ALLEGRO_EDITOR REPORTS Shape report incorrectly lists thermal connections for SMD,Via and Through all as Through.
# r' d' C }7 p+ z) m+ ^776190 ALLEGRO_EDITOR INTERACTIV place replicate crash; select polygon zoom points
9 V1 ~7 a$ `8 s1 F+ s2 E5 d( t# p776284 PSPICE STABILITY 16.3 design crash while simulating the design
4 |$ B, q7 A @0 R777556 SPECCTRA CHECK interlayer clearance output drc even so layers are separated by a power layer
, V8 A6 E3 B, P! Q# p4 L777689 ALLEGRO_EDITOR SHAPE Shape do not void if Curved Fillets are used
- h+ t# a. |& s: y777698 CIS RELATIONAL_DB CIS 16.3 ISR s007 - Relational feature doesn't work4 C* ]/ A* B6 F. y0 R+ s
778042 CAPTURE PRINT/PLOT/OUTPU Some text are not searchable in Capture generated pdf; y: W# u( b; a0 d2 }* _( b# Y
778350 ALLEGRO_EDITOR SHAPE Multiple Drill on pad gets round void instead of rectangular. n4 g8 p1 T5 C9 c5 y
778356 ALLEGRO_EDITOR SKILL Duplicate Vias with axlDBCreateModuleDef# X6 P# B( |9 m _" R
778782 ALLEGRO_EDITOR OTHER Display-measure and axlAirGap incorrectly report no air gap for multiple drill pin
% y6 ?; h; }* H) Q" z0 N7 M779146 ALLEGRO_EDITOR OTHER Moving component crashes Allegro
: b9 e; m7 _& o3 X9 R780213 ALLEGRO_EDITOR DATABASE Design saved in GXL when opened in XL gives misleading message.7 @0 h2 _/ J A& B
780773 ALLEGRO_EDITOR SHAPE No DRC displayed when Place Bounds are edge to edge
* M3 X: J' d6 n$ C) M; H: U' s q9 O& p* G9 A! |
DATE: 05-14-2010 HOTFIX VERSION: 008
8 H: _* b5 h9 `% g6 ~: q===================================================================================================================================
0 w- g1 O! E: ?/ aCCRID PRODUCT PRODUCTLEVEL2 TITLE
* T6 P& e- N9 }9 K- \' U===================================================================================================================================
# y2 N$ {, S* k+ J( @" s697699 CONCEPT_HDL HDLDIRECT SCM Verilog output contains the line “defparam <instance number>.SIZE, L# ^( q; b8 a6 d4 r) G* S3 x% r
734169 ALLEGRO_EDITOR PLACEMENT Wildcard asterisk character giving "illegal char(s) in refdes entry." error in quickplace.& g- r# v# K( D3 X) j5 n, @8 f
738970 SIG_INTEGRITY GEOMETRY_EXTRACT power bus issue with SSN simulation when device is on bottom
+ _1 B* p+ ^0 d. k6 }744762 CONCEPT_HDL OTHER Connection dot sizes do not match on printout vs. screen
. U5 W9 i8 e( o0 v e9 l% a% Q) G750371 MODEL_INTEGRIT GUI Model name in physical view cann't match the model in right workspace
' P# B: ?8 G5 h- f1 P2 A8 N9 g1 N757024 CAPTURE STABILITY Capture crashes while exporting to EDIF
7 W: b0 I! z1 {; A3 s759094 CONSTRAINT_MGR INTERACTIV One member of a diff pair will show Analysis Failed when analyzing the design.
6 R/ O+ a9 [+ e/ ~760178 ALLEGRO_EDITOR EXTRACT Crash Allegro when executing extracta command for big size design(size of .brd3 L4 {& S/ b- t1 T* C2 z1 C
761391 SIG_EXPLORER OTHER Incorrect rise time
# X2 t, Q0 V* @% S$ x762402 ALLEGRO_EDITOR MANUFACT When photoplot(RS274X) of MM unit was loaded, shape was broken." r- U/ N4 A; H& e3 G2 i
762783 SIG_EXPLORER INTERACTIV sigxp - coupled tline on stackup layer should show solved impedance
* Y3 A: X0 ]1 \2 `763150 ALLEGRO_EDITOR OTHER Request - IPC356 output truncate the padstack size to fit into the columns 59-62 and 64-67& s0 D/ v; d: f& _# F& [
763556 SIP_LAYOUT ASSY_RULE_CHECK Assembly Rules Checker is displaying an array of confusing DRC's on a Soldermask shape.
5 t/ V! S5 q- q' V$ X# Y764399 SPECCTRA ROUTE Manually routed trace in Allegro are ripped OFF after routing in SPECCTRA using Route > Route Editor.+ i9 N: g% I7 H: \
764475 SIG_EXPLORER INTERACTIV topologies from earlier versions cannot be opened in 16.2 on a machine
; ]. d1 O* p: A5 L765287 ALLEGRO_EDITOR PAD_EDITOR attempting to open padstack fails with - database has a non-recoverable corruption.0 [- p. h5 @. W: r$ \
766041 ALLEGRO_EDITOR OTHER Auto B/B via generator incorrectly defines some BB vias
$ |9 j* U/ u, g1 ~- L766153 ALLEGRO_EDITOR SKILL Allegro crashes when trying to extract padstack information8 o* @/ _6 `& x0 u1 ?, e5 J
766611 ALLEGRO_EDITOR EDIT_ETCH slide creates DRCs in ARK area
' X- e% j( V3 y( x1 W/ i767041 CONCEPT_HDL CORE The tap command failed because the specified tap body CTAP is invalid1 c% k* G& [1 ~/ [9 U: O; e* b
767146 FLOWS PROJMGR Project manager open last open .cpm in 15.7 version not in 16.3" ~, X8 B: }/ n" t: e N. \
767526 FLOWS PROJMGR Project Manager customization does not work9 Y+ ?- K. X4 z) d- f: \% c
767671 APD DATABASE Crash creating cline with axlDBCreatePath() on this database.. v2 `6 p) h+ t5 h; d
767951 ALLEGRO_EDITOR DATABASE color net param file omits nets with bus brackets in the name
% }" S, S7 W! ~2 X768168 CONCEPT_HDL CORE Fontsize on instances changes when doing backannotation7 n0 F: j+ W" c' w2 J: k: H; E
768207 CAPTURE STABILITY Capture crash while editing properties$ V2 Q, T/ Z3 Q% a2 v4 L, B
768734 CAPTURE PROPERTY_EDITOR Properties of title block are not getting editted through spread sheet.
: n' C/ U; y! h: B! N( F768832 APD DRC_CONSTRAINTS Following Performance Advisor instructions results in much longer DRC check time.
' P( {2 E7 m& t4 r: H( [, X1 i6 R7 z0 s768990 F2B PACKAGERXL RFSIP architect 16.3 85Y Schematic to SiP fails due to softinclude in cds.lib file this problem does not occur on 16.2. j0 J, Y4 w, `! {6 K2 o
769097 SIG_INTEGRITY GEOMETRY_EXTRACT Sip Digital SI-Bus Simulation function will shut down auomatically when it is running5 r/ G- c j7 ~5 `. c7 o7 y( R
769235 SPIF OTHER need to be able to remove mbs_spif* properties added by mbs2brd
2 M% u" x9 X# r D' Z769326 CONSTRAINT_MGR DATABASE Length by Layer crashing& O: F4 t& f2 b/ I! A. q U
769336 ALLEGRO_EDITOR TESTPREP testprep density - returns Unable to add the PROBE_DENSITY subclasses.% U2 V% d3 q Z. |
769458 ALLEGRO_EDITOR OTHER SMD Jumper has a problem about the connection point when using the Add Jumper
- R- I7 v) Z" X$ i6 V1 T769845 ALLEGRO_EDITOR EDIT_ETCH Diffpair routing out affected by line to line spacing rule.7 W8 I9 o: U9 {5 e5 f$ _
769934 SIP_LAYOUT WIREBOND Duplicate Finger Name.8 o$ \, c3 @' w
770006 ALLEGRO_EDITOR OTHER Ratsnest_schedule[Power_AND_Ground] can not show figure without move symbol.
9 S8 W9 g: {6 D+ T5 J770125 ALLEGRO_EDITOR DATABASE PCB SI GXL Via Labels grayed out on formand labels not visible on the canvas
& O! n/ M5 d5 L2 `7 }# @770212 ALLEGRO_EDITOR DRC_CONSTR Incorrect Etch Turn under SMD pad DRC error on this board
5 b, m( _: j( L6 [% Q0 D: l3 {6 ?" t770230 ALLEGRO_EDITOR ARTWORK Artwork fails to suppress unconnected pads on pins with the net_short property.
6 l. _6 {% U. ?, t2 b# `770233 ALLEGRO_EDITOR MANUFACT Fillets are not behaving as intended.2 g, T1 i' U% G# N" Y. `1 v9 X; J! s
770442 SCM PACKAGER Error during Export Physical - The subdesign block instances ares not updated with reuse properties
4 z+ i& |( \ ]2 x770556 CONSTRAINT_MGR ANALYSIS PCB Editor's Constraint Manager not updating custom constraint cell.# y. w* T1 `/ `4 }* K* {
770861 ALLEGRO_EDITOR PADS_IN PADS translation fails with no error message
9 M6 @+ ^$ V( M% Y' a- l% Q# }) G0 i770872 SIG_INTEGRITY OTHER Opening Orcad PCB Editor for this board takes Performance License as well2 [5 v c5 L3 f5 s1 _5 _5 V8 p) S# q
771117 ALLEGRO_EDITOR DRC_CONSTR Allegro PCB Editor crashes on Update DRC-16.3/hotfix0064 b" X+ R) ~! u$ @' e8 {6 Y
771181 ALLEGRO_EDITOR PLACEMENT Component deleted completely from board file after we Mirror and rotate them while moving them.
8 v5 {6 [, T9 o; l# r! b771256 ALLEGRO_EDITOR DRC_CONSTR Update DRC consumes system memory and crashes allegro after approx 30 minutes
& s- q A6 {8 s# E771423 ALLEGRO_EDITOR SHAPE Shapes - Update to Smooth - Low on available memory please exit the program.
$ I2 g1 F. G: {1 `771456 ALLEGRO_EDITOR EDIT_ETCH Allegro 16.3 crashes when using arrow keys
& b1 b' A( H- E- Q9 m" L- I! E771719 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license.
5 [7 u) L6 H0 y" O4 s. T* \771765 ALLEGRO_EDITOR PADS_IN PADS translation fails to translate symbol8 u+ ?1 P8 h% k& A
771766 ALLEGRO_EDITOR DRC_CONSTR Moving certain components takes a long time on this board database.
: S) U P& R6 C D+ f771815 SIP_LAYOUT IO_PLANNER SiP OA co-design flow does not allow a save to the .sip file after modifications in IOP1 g- l: \9 q/ r8 k$ P' [
773072 SIP_LAYOUT ASSY_RULE_CHECK wire to wire same profile
' o- M' P- R: I+ r! _1 s6 Z1 @5 c4 O773126 CONSTRAINT_MGR UI_FORMS Constraint Manager "Value Filtering" for Topology Schedule is missing TEMPLATE and "UserDefined"9 g$ a/ b, ^! s+ k
773179 ALLEGRO_EDITOR PAD_EDITOR pad_designer crashed when attemting to delete internal name layer.
) K( _1 d' i+ X' D773229 ALLEGRO_EDITOR OTHER Netrev never end importing netlist generated from Capture CIS
" {9 a' _+ H8 y6 W2 B" f9 f773329 ALLEGRO_EDITOR MANUFACT Allegro closes when performing a Linear dimensioning and then selecting the undo icon.6 @1 C: M. f! S# `2 e% j+ t( z
773483 ALLEGRO_EDITOR MODULES place module problem- w" ]! b7 H9 S$ ]7 y- q% G- j
774036 ALLEGRO_EDITOR INTERACTIV Rats not shown after move->mirror command/ k$ f6 c1 ~# \4 M2 X1 S
774170 ALLEGRO_EDITOR DATABASE DBDOCTOR fixes Error but it reappears and Artwork fails
0 K$ J" ~% J8 f4 t+ x774602 SCM OTHER ASA crash while working with hierarchy
5 }5 B" O9 B8 f774643 CONCEPT_HDL CORE DEHDL crash on edit of attributes4 Z. B9 o" }; Q
775201 ALLEGRO_EDITOR SKILL Color palette can only be changed one time using skill commands
7 X9 G9 o+ J3 K9 ]' y T4 t' |/ e775815 SIP_LAYOUT WIREBOND Unused wire profile once purged using wire profile editor are still available in CM and Color dialog
. u. k7 V1 _( r& l. g9 g775826 SIP_LAYOUT WIREBOND Cannot change the Wire Profiles on the wirebonds in this design
1 M2 i' H* m% h# _+ x8 C3 w775842 SIP_LAYOUT WIZARDS Die text in wizard is changing DIE location when origin set in DIE text file is other than 0, 0
) ~5 l1 f+ ]+ Q/ C8 P# q* P/ Q/ o) r$ U! U
DATE: 04-23-2010 HOTFIX VERSION: 007. e. E( J) Z2 T8 ?$ @
===================================================================================================================================' D9 y, u0 H: `' r/ Y# {! ~
CCRID PRODUCT PRODUCTLEVEL2 TITLE
' Z. ^( p# E! K7 g8 z9 X% c& _===================================================================================================================================) |6 O$ `/ d, j. n0 ^: }% v& v
721859 ALLEGRO_EDITOR OTHER update shape to smooth creates tmp file on remote file server working dir why?1 G3 v& r/ R& ^/ l! i
740201 SPECCTRA_MENT_ IMPORT Wrong stackup order after translating from mbs2sp
/ u( K7 g( o% `$ ^0 s' A- J744797 SIP_LAYOUT OTHER Cannot Copy a connector (IO) symbol in APD and SiP tools8 G# \5 o1 O3 e
747831 CIS CONFIGURATION There is a delay of 5 to 10 mins in opening SQL database in V16.2 and V16.3. It is fine in V16.0.- y$ q" z' E) |+ l
747848 CIS CONFIGURATION Unable to configure CIS with Oracle database due to Capture crash.
, G1 X0 A. r$ f+ S Y$ w751372 CAPTURE OTHER Copy / Paste Issue in capture 16.39 Q: Q" p+ ]% J @2 k4 ?
757434 ALLEGRO_EDITOR MODULES Allegro hangs the board file after creating Placement Replicate circuit.: B2 |5 Y0 L" c5 ^/ k6 [- D8 Q
759906 CIS PART_MANAGER Property copy from one to several parts doesn't work
\, N9 w' W: ?( Q. j/ ~7 |760154 PSPICE NETLISTER Model parameter (Tj) is not affecting Smoke Analysis result
2 B( k& x9 p l! e: j1 a761177 CIS OTHER Error Message - Memory exhausted2 w1 e. T" q, _- G# |6 q
762602 CIS EXPLORE_DATABASE CIS doesn't open datasheet for parts if it is not stored at default Capture location.+ @: J2 |3 F* \) U
763677 APD EDIT_ETCH The "Via to Via Line Fattening" tool is inconsistent in which clines are changed.
' H& a9 z: {* o3 G" Z6 }+ u- ]763715 CAPTURE NETLIST_OTHER A long pin name gets truncated upto 31 characters when the wirelist is created.
% D9 |! N; \0 K7 P2 j763878 CONSTRAINT_MGR DATABASE Why Pinpairs disappear after closing Constraint Manager?
$ e) k( ^9 V1 T3 a0 y2 G764020 CAPTURE NETLISTS Usernetl.dll has changed between 16.2 and 16.3
! p5 y n/ R+ d7 v/ @1 v& C5 e& k! `764101 APD EDIT_ETCH Perpendicular routing through a Region does not work when the region segment is drawn at an angle.
+ S8 ]" X1 K2 r2 N. q( `0 q+ O3 u764200 ALLEGRO_EDITOR DRC_CONSTR Via at smd fit drc on a via that is placed fully inside the padstack having custom pad
" N, h9 l2 Q+ ^" A+ ]764903 PSPICE ENVIRONMENT 'Run in Resume Mode' does not work in SPB 16.35 X n/ M7 p( k, y) P$ p7 ~
765206 F2B PACKAGERXL Unable to feedback subsequent pin swaps from Allegro
! W9 F2 C$ \( R4 p7 `765319 APD DRC_CONSTRAINTS Identical Constraints in Performance Advisor question
! j( M& w" {% G: b, i/ J, n765541 SIP_LAYOUT SHAPE Set via oversize value to 3 in dynamic shape instance parameters will make overlap shape.. Y! o0 v5 k/ a5 L4 [
766147 APD EDIT_ETCH Resize/Respace Diff Pairs does not work on 45 and off angle% H- @6 ^7 [' U) Q+ a- x
766337 SIG_INTEGRITY GEOMETRY_EXTRACT Geometry of Via model Extracted from board file is not identical to Original Via geometry design
$ y/ P, G5 G3 m1 y2 Q) X F4 ~766443 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd in 16.3: w' l7 e/ N, ]9 F* U% l& T
766581 CIS CONFIGURATION In 16.3 capture.exe remains memory-resident after exit% y3 `' a1 R; Z" s. D; w
767161 ALLEGRO_EDITOR SHAPE The behavior of Add Fillet command is different by Hotfix version.
5 L/ n' V0 l1 ?- O767217 SIP_LAYOUT IMPORT_DATA The Die-Text In wizard and it is crashing on the "Finish" step.. D/ F/ X5 Y$ z+ v! L
767598 SIP_LAYOUT WIREBOND Can't wirebond SIP designs as it just hangs.
3 K' u5 i M T& S) \) D0 o1 |$ r767832 ALLEGRO_EDITOR DRC_CONSTR Reducing Design Accuracy updates Physical Diffpair constraints wrongly
B- P0 X4 }' k; h5 ?: {768822 ALLEGRO_EDITOR SKILL axlSetParam return value is divided by 10 to the power of the design accuracy.9 Q1 o2 m W T. f
769150 CIS PART_MANAGER Update All part Status on a group changes “Do Not Stuff” status to “Stuffed” in V61.3_ISR_5.
: h7 R' T+ H) A( M6 [: q
' l7 h( D: I, |9 h7 mDATE: 04-09-2010 HOTFIX VERSION: 006 }$ O1 y! u. \' [# i+ b2 Q
=================================================================================================================================== L0 K$ C# d9 s f+ Y* U' p9 l
CCRID PRODUCT PRODUCTLEVEL2 TITLE
+ {0 X. u! F W" i) N) M===================================================================================================================================
$ d$ ?) I9 ?- x8 F2 o. G7 e3 H745241 CONSTRAINT_MGR TECHFILE Importing a tcf file automatically enables On-Line DRC.
2 }1 C' I% v. K) Y" i752587 ALLEGRO_EDITOR PLACEMENT Uppercase File name(XX.mdd) for Placement replicate update on Linux.- W2 k( Y! }: b. c* t, _ Q
753626 CONCEPT_HDL CORE newgenasym error while saving the hierarchical block symbol
( a7 N5 u" R8 s( G9 G \753894 CAPTURE OTHER Case sensitive version control S/W# Q) [5 x' T4 H0 v2 U
754487 RF_PCB OTHER Various asymmetrical clearance problems uncovered - calculation issues?
) _1 h" Z, j: q% y! U$ t758272 CONSTRAINT_MGR UI_FORMS Entering values on the Min/Max Propagation Delays worksheet hangs the application./ |+ D( | {- w+ O1 g
758911 PSPICE PROBE Pspice crashes while exporting probe data using our sample project
/ ]2 h6 `& e0 l759871 CAPTURE PROPERTY_EDITOR Save option in Right Mouse Click on property editor of nets doesn't saves all the changes.3 Q i7 F8 L" `* t" G4 }- T
759890 SPECCTRA ROUTE Specctra autorouter ignoring prerouted nets
5 `+ V3 o! I% h3 X! x% _0 m760067 ALLEGRO_EDITOR SHAPE Dynamic Shape not getting filled on board with odd angle placement and routing
z n6 o& f: Q$ ~2 z7 U760284 CONCEPT_HDL CORE Update Sheet Variables turns of the grid4 {8 K: D& l9 g |0 V" ?: P d
760480 MODEL_INTEGRIT OTHER Message open clipboard failed when trying to open the rename/reorder dialog in Model Integrity
+ N+ Z% [ a. r4 P/ Z760667 ALLEGRO_EDITOR PADS_IN The pads_in.exe translate incorrect drill shape from PADS 2005 ascii database.7 r7 @: V/ e9 S! t6 \4 Q6 ]
760741 ALLEGRO_EDITOR MENTOR mbs2brd does not work in 16.3 but works in 16.2" z1 @+ W& F: p8 |% Z
760810 CONSTRAINT_MGR INTERACTIV Deleting Region Deletes NCCs' o; f, X5 {4 g: v8 j, N
761114 PSPICE PROBE Refresh issue in Display > Cursor window# _3 Z% r7 }3 T, W& a+ N
761180 ALLEGRO_EDITOR DRC_CONSTR Via_at_smd not working for custom shaped padstacks.
, }3 F7 a6 B- c9 m! z, d+ Y- T$ `761305 SPIF OTHER Allegro crash when seleting any of the Route - PCB Router - submenu items.
# `8 L4 O$ P. [$ D# I! K761376 ALLEGRO_EDITOR PAD_EDITOR Wizard_Template_Path is not considered for symbol template look-up ?
" V8 `4 K7 M0 k4 c761416 ALLEGRO_EDITOR DATABASE Allegro crash on chaning the subclass for group of clines
& K6 P. T( i2 L2 `4 I* m761492 ALLEGRO_EDITOR SKILL about axlTransformObject function
8 t+ r1 z2 \; {# _$ W7 a7 Q761518 F2B PACKAGERXL about mismatch library path between cds.lib and actual6 t& u/ t! z% b. }7 b
761737 ALLEGRO_EDITOR OTHER Running Dbdoctor after executing Skill is giving symbol fit error for the .dra file
, f* F8 I; G: A& g6 i762155 ALLEGRO_EDITOR SYMBOL Updating a symbol changes the netname of the cline resulting in drcs.
% `- [! T5 B/ g* w762181 ALLEGRO_EDITOR OTHER Allegro netrev crashes for long device name in PST* files
8 z8 k8 Q S+ b# l/ Z) e8 A% {762316 ALLEGRO_EDITOR MANUFACT Allegro disappears on Adding dimensions for the symbol file
; l# G1 Y" ~" a$ m8 G/ }& l762792 ALLEGRO_EDITOR PADS_IN PADS_IN fails for SPB 16.35 h: p0 z) _: [- f& N, A# f. Y7 i
763108 ALLEGRO_EDITOR SHAPE Z-copy shape create an error like VOID boundary may not cross itself
2 V1 I+ d4 `" s/ Q4 ~+ S8 b763134 SIG_INTEGRITY SIMULATION Bit 7 of a simulation is out of sync with rest of bus. It should be the same for all bus values./ s/ Z" F7 }; O' n! Z' n
763149 CIS GEN_BOM CIS BOM in V16.3 is not correct if database has Quantity field and its value is 0.
5 T+ J5 T, m- y. ^+ e l0 e763296 ALLEGRO_EDITOR REFRESH The error was happened while doing the SUM
3 R' n- S$ N0 F- }! e) r5 H763303 ALLEGRO_EDITOR OTHER SMD Jumper has a problem while using the Add Jumper
6 w4 ]! I, U6 X# N( W' m U763315 ALLEGRO_EDITOR PADS_IN pads_in got error message WARNING ERROR(SPMHDB-205)
6 @0 U! i$ ?, X& W+ H3 Q# k( J763354 ALLEGRO_EDITOR PADS_IN Auto suppress redundant shape while using pads_in translator
+ a* o8 d1 e( c+ U, a. O+ l& b1 X763428 ALLEGRO_EDITOR PADS_IN enhance pads_in.exe translate spacing and physical rule into Allegro.
3 |* {3 g0 V0 k! W- X9 F' H763446 ALLEGRO_EDITOR REPORTS missing fillet is reporting pad without drill
7 }6 F: o" M `+ \# ]8 F& h1 {763448 ALLEGRO_EDITOR DRC_CONSTR Performance advisor shows Cset as unused nets when it is assigned to Diff pairs or xnets.( ~5 A7 ~9 f* [1 J
763586 ALLEGRO_EDITOR DATABASE Allegro rounds off the value after decimal in CM5 y/ G% ^9 C( g$ Q. p q9 s @
764077 CONCEPT_HDL CHECKPLUS The output predicate in the Graphical environment is not always returning the pin object for an output pin.
# X+ T, C; @0 i6 c4 ]) g% H( o+ H# T8 D! ?, ]$ }3 ?* X0 @
DATE: 03-26-2010 HOTFIX VERSION: 005
8 _1 s# d% |# S6 B- @6 g===================================================================================================================================
4 X& T$ l$ Y H; J: g# eCCRID PRODUCT PRODUCTLEVEL2 TITLE
! s; [& H9 a! U3 ~2 E===================================================================================================================================
7 r% J2 A5 v0 o$ n% Z599819 SIP_LAYOUT 3D_VIEWER display soldermask by default in the 3d viewer
2 B) g# o8 U- l: R735992 CONCEPT_HDL CORE Create Test Schematic does not use the correct package type
3 I) i1 d" K) ^/ [1 w, K3 p7 g743787 SIG_EXPLORER OTHER 16.3 SigXP crash if sigxp.run created by previous version exist.: f. D3 j/ n9 ?) e4 g
746320 CAPTURE NETLIST_ALLEGRO Remove Semi-colon from invalid pin-name check during netlisting3 {5 P k* S0 ]# V8 [6 `
746444 ALLEGRO_EDITOR OTHER show element fails to display info on a via if it is in a module.
; M! C) j2 W- {" \) t7 G7 ~$ T746726 SIG_INTEGRITY SIGWAVE Save As and Open Dialogs open in last saved directory& D) `( ~3 t# F* y' c# j
750080 CAPTURE NETLIST_ALLEGRO Improve error message ERROR(SPCODD-390)
3 r* j' s* K: V& [3 T" w5 E750606 SIP_LAYOUT ASSY_RULE_CHECK Wire to BF same profile check
}9 g- H9 h9 _751492 CAPTURE FPGA Option to swap the pin-numbers rather than their locations in the Schematic after back-annotation! Q7 b; _/ C( x9 V- e% P& \ u& j W
753834 CIS LINK_DATABASE_PA unable to link multiple database part
9 R) m2 g7 T5 ^+ }7 N753990 F2B PACKAGERXL Delay in opening the subdesign tab in the Export Physical setup in SPB 16.3# }+ U) I4 R% _
754328 LAYOUT TRANSLATORS L2A gives error Subclass name TOP not valid Allegro subcls with s029 hotfix
9 ]. Y) J7 u2 \# o! b; t754434 CONSTRAINT_MGR OTHER allegro crashes when deleting matched group2 _2 @; q- \" X
755111 ALLEGRO_EDITOR INTERACTIV "ALT_SYMBOLS_HARD TRUE" property does not work when I mirrored symbol using move command in 16.3.
/ D- D2 j8 q; P% C8 K4 }756131 PSPICE SIMULATOR Capture crashes while re-running simulation
+ F* D6 @2 G9 I0 P756148 PSPICE PROBE Zoom Area in Probe Window does not work for digital signal in SPB163
* ~- Q' v" E9 S( ?4 b$ n756169 SIG_EXPLORER OTHER Signal Explorer crashing due to sigsimcntl.dat5 Y6 U9 x9 O; h& e
756176 PSPICE PROBE Trace color is wrongly interpreted in PSpice probe window.! Z) A# ~7 A2 ^/ Y
756224 SIG_INTEGRITY SIMULATION Simulation aborts reporting that VIA models have changed
0 \; q) z: F8 ^2 O2 {5 x756281 ALLEGRO_EDITOR OTHER Why *.sav file cannot be recovered from PCB Editor utilities? @7 s: i5 K3 O& E; b' _2 u
756673 SIP_LAYOUT ASSY_RULE_CHECK Running ADRC Metal to metal checks causes false X-D DRCs, cannot clear them and trying crashes the tool1 U& s$ F" z4 U1 b9 h0 T
756918 ALLEGRO_EDITOR OTHER Allegro angular dimensions working incorrect in 16.31 G! ]+ i& I2 D# O' f# X {
756932 ALLEGRO_EDITOR CREATE_SYM Create symbol fails with error duplicate pin number
3 ?5 M% X: H0 v+ W: A8 z5 G1 I756976 ALLEGRO_EDITOR SKILL axlChangeWidth always return nil in Allegro version 16.3
; x! @1 s5 d, b" e9 A/ A757000 PSPICE NETLISTER Incorrect Hierarchical Format Netlist created& w/ e) c: \ ` ]+ O) L7 M
757406 APD OTHER Implement Segment over void features in APD L
3 S7 E2 j7 c2 x757624 SIG_EXPLORER OTHER Sigxp runtime error when simulation is run and exit without saving the topology/ I/ P% u1 q' [9 h( B
757820 ALLEGRO_EDITOR SHAPE Shape does not void to hole if there is no pad& f$ v2 b3 Y$ S7 }& M- Q# ]
758009 ALLEGRO_EDITOR OTHER Export > Library (MECH_SYM) adds a new subclass NCROUTE_PATH, data moved from one subclass to another.
5 }3 n: s, }8 K2 j9 V758022 CAPTURE DRC Capture crash while running DRC with “Run Physical Rules” checkbox.
4 F2 ^+ f" @8 B758190 ALLEGRO_EDITOR PAD_EDITOR PCB Editor crashing on pin move in this design
7 _7 b4 @! t0 k3 @2 o4 @. v758374 F2B DESIGNVARI Problem with Mechanical part in Variant Editor
( S( k9 C8 t! }) F0 s758471 SIG_INTEGRITY OTHER Differential impedance does not change on changing the etch effect values.
U% d% R; g/ t' [: c* T, G758490 CIS CRYSTAL_REPORTS Different crystal report output in 16.3 than from 16.2
# \( J% F& _1 g9 Q k758498 CAPTURE NETLISTS PCB Editor netlister hangs
& w7 h A; o9 L! p1 G, ^4 S6 S758584 APD SHAPE Shape not voiding all elements: F* Y3 S9 v3 P
758886 ALLEGRO_EDITOR REPORTS Total number of nets is wrong into Testprep Report0 Z5 G; x7 P" f$ y. T2 p
759146 ALLEGRO_EDITOR SKILL The title is not displayed in the form by the version.
; [5 V4 x! ]/ \1 b& s759339 ALLEGRO_EDITOR ARTWORK artwork output fails by SPB16.x.
9 c: L0 M7 y$ p2 ~8 x. v8 L+ R759591 ALLEGRO_EDITOR SKILL axlSetParam fails and does not round the value as indicated by the warning message
- M; `9 M9 L% M; W1 j: q0 z759816 CONSTRAINT_MGR OTHER Allegro Hangs when double click on a Bus in CM
& P; U" Y. B: K759947 APD OTHER Need an a way to convert Lines into Clines" x+ E) r4 X& r# p! I0 X1 N
760353 ALLEGRO_EDITOR MANUFACT Allegro crashes and creates a .sav file on running the silkscreen command from Manufacture > Silkscreen
- Q# V$ ?4 ~+ b9 ]. m4 I760432 ALLEGRO_EDITOR PARTITION Unable to remove fixed property after partition import" E$ A/ N+ v! [: f( V4 [
760638 ALLEGRO_EDITOR PADS_IN pads_in translator can not handle " PINPAIRGROUP ".
7 D: o% k/ D( k: b4 \& q( F760734 ALLEGRO_EDITOR SHAPE Different therma contacts on rotated partsl
: y) f7 ~% }. \4 d+ N7 W$ s761436 CAPTURE NETLIST_ALLEGRO SPCODD-53 Error when creating netlist with PACK_SHORT
; s0 }) z! D: F. M! s h: j2 f9 q5 n! F" ~0 N- L, r# |
DATE: 03-12-2010 HOTFIX VERSION: 004$ a7 I0 W+ ?1 s) w- L0 \: m
===================================================================================================================================0 r( F+ m4 j8 O0 w( E# O
CCRID PRODUCT PRODUCTLEVEL2 TITLE
3 t7 X8 A' R' t" g- G" y8 H===================================================================================================================================7 y8 @$ r7 O% ^) W- k! L( x
689495 ALLEGRO_EDITOR DATABASE corrupt database4 _: T/ r( z8 n' H o1 j5 z8 ?
725944 SIG_INTEGRITY GEOMETRY_EXTRACT xtalk make allegro freeze and never give hands' ~6 A5 m! b! M" {5 o
732604 SIP_LAYOUT SHAPE Shape Issue - added shape will not clear around other elements.
5 H! N, h! Q% Q, u6 N740106 PSPICE NETLISTER The "Enable PSpice AA Support for Legacy" option does not give the Desired Monte Carlo results
# H- P' x5 w! R6 h k1 n744259 SCM UI Signal order reversed when a Vectored Signal name is renamed in reverse4 m- Z f4 f$ q: I! o; B
745554 SIG_INTEGRITY GEOMETRY_EXTRACT Time to get Xtalk simulation result in 16.2 is lower than acceptable by comparing the time in 15.7
8 \8 l# \7 L: [, U. Q7 V& `' N745595 RF_PCB FE_IFF_IMPORT import iff RF_PCB give an empty block+ b3 c) j8 U. e, `2 ~% h
747133 CAPTURE STABILITY ERROR [DSM0006] Unable to save9 m, R: {7 ~ ^2 Q9 Z
747679 CAPTURE STABILITY Trying to Save the Design in 16.2 format gives DSM0006 Error and crashes Capture% S1 i* d- ]% c/ [1 n8 A
750460 CIS FOOTPRINT_VIEW 3D footprint viewer doesn't shows the footprints6 w/ e' K- ]; r4 R- P$ g$ K
750777 SIG_INTEGRITY OTHER Trace impedance showing wrong# n2 R, U8 E6 }8 {. \+ k
751424 ALLEGRO_EDITOR DRC_CONSTR Unexpacted DRC for Shape to Route Keepout
7 g6 H1 P' K( a751897 SIP_LAYOUT SPECCTRA_IF Radial Router crashing SiP tool2 ^7 v O8 h8 ~4 l
752029 SCM OTHER Cross probing not working between SCM and Allegro Editor in Linux Environment
+ s6 Z! Z6 u" z# A' G0 l' t; u9 H752450 APD PADSTACK_EDITOR APD crashes when selecting a User Definable Mask Layers.
$ `$ S% x) ]( w2 v4 S$ K1 K752581 PSPICE PROBE Pspice probe window crash7 A* t: I' q& f
752709 ALLEGRO_EDITOR PLOTTING Sheet content doesnot plots title block
) ]" K7 M- b0 D! @' D( |752908 ALLEGRO_EDITOR INTERFACES Output from Export > DXF shows one instance of a via on the wrong layer2 g- s* w# S4 k" ?" R: `
753226 ALLEGRO_EDITOR OTHER File > Change Editor doesn't shows the default Product Options
2 I( V6 i, ]" t9 J. A K8 R) b, f753622 ALLEGRO_EDITOR GRAPHICS Enahnce capture image command to default the save as location to working dir9 x+ Q F4 s" b: B2 C
753773 APD WIREBOND Requesting the option to set the diameter of the default WB_TACKPOINT power ring pad.' ~9 G F! m! g8 k
753778 APD IMPORT_DATA Import NA2 displays the design momentarily and then crashes
, m6 R& b/ z2 J i753866 SIG_INTEGRITY OTHER about Select by Polygon after move command' z5 x% ~: V6 ], ~& x1 a" C- ?
753958 CAPTURE OTHER Capture V16.3 is extremely slow while edting schematics of design placed on network drive via VPN.
2 m) Q A+ m9 z* z' _- f) g754050 ALLEGRO_EDITOR UI_FORMS Why show element window disappears when scriptmode is set invisible
) `8 B; }, y: J754143 SIP_LAYOUT OTHER SiP Package Design Integrity - running Extra Cline segments generates report without Layer number
: H+ @2 B o% _% }* ]" G) ]# q+ S754327 ALLEGRO_EDITOR OTHER Rename Sub Class is not working as desired.
1 L9 }1 v3 ?* E" |2 m) a5 }754364 ALLEGRO_EDITOR PLACEMENT Crash when applying placement replication
* J7 v+ @: m4 e8 M( k1 X6 u754462 ALLEGRO_EDITOR SHAPE Allegro circular dynamic shape fails to fill
5 U& f5 O/ a5 I% q/ B# O754819 ALLEGRO_EDITOR OTHER Create details shows wrong graphics for filled curves7 N9 R5 K! u( c
755176 ALLEGRO_EDITOR PADS_IN Pads translation succeeds in v16.2 but fails in v16.3 on this ASCII file) _2 H% Y! @4 Q4 o
755256 ALLEGRO_EDITOR OTHER Attached script is crashing the designs in v16.3. y/ _2 V* d9 W9 o7 ?5 [
755610 CONCEPT_HDL CREFER Cref hyper links does not work for signals where number "0" used to define the zone for page border8 I% b1 B& I+ H' }. X
755787 ALLEGRO_EDITOR EDIT_ETCH crash using resize_respace_dp command u7 c- Z g$ |6 `; l5 ?6 m/ O
755881 ALLEGRO_EDITOR DATABASE Swap component crashes application* U# h) E" V! A) g( }* Y, G. A
756092 CAPTURE PROPERTY_EDITOR property editor flickers and loops on value edits8 E9 T' T5 w% g: R: E8 w
6 p w. B9 I) w/ |* I7 TDATE: 02-23-2010 HOTFIX VERSION: 003
2 H' W6 p5 H6 P) ]===================================================================================================================================, m9 ^+ t7 i: j1 Z( B, B2 A5 Z. o
CCRID PRODUCT PRODUCTLEVEL2 TITLE( `0 P+ ]% b/ v( b' T {3 k8 c) e
===================================================================================================================================: N* l* U+ F' m* J/ K# W6 m
263504 CONCEPT_HDL CHECKPLUS Checkplus fails to run if crefrpt exists in the design
. U2 U) ]9 D; K) J3 o6 L726836 ALLEGRO_EDITOR SKILL axlGeo2Str() and axlGeoEqual() return different results
% W+ d. {/ e: A730820 SIP_LAYOUT PADSTACK_EDITOR Changing the Via diameter will cause the SiP tool to crash' e: H/ w' N, W2 ]4 ~
735193 CAPTURE FONTS Pin_names and Pin_numbers get convertred into darkened blocks in ‘Zoom to all’ view in V16.2.
* A# T- {0 ], ~737307 SIG_INTEGRITY GEOMETRY_EXTRACT differential pair extraction to sigxp fails to extract coupled sparam via models% V2 w4 Y& Z3 P C6 w
740936 ALLEGRO_EDITOR SYMBOL Confusing error message during Create Symbol; u: ]6 |1 ]( e' \. c7 K) {- e
744191 ALLEGRO_EDITOR EDIT_ETCH Arc routing enhancement
8 \ f6 f( `+ T: w) k' H' ~3 L744497 ALLEGRO_EDITOR INTERACTIV PCB Editor Crashes with Data Customization Feature
9 V6 q( z7 p3 \% @* R/ _7 D, p746572 ALLEGRO_EDITOR DATABASE Reoccuring error in attribute pointer to attribute invalid on dra.
& f1 j+ g2 f \6 N y$ f! \4 ~746978 SIG_INTEGRITY SIGWAVE 2 licenses were used for SigXP and SigWave.
2 j/ d+ P8 D6 u$ r, l) C747219 SIP_LAYOUT SHAPE Dynamic Filleting not working with odd angles7 E; ?2 T$ G& {; ]3 Y0 [# |
747593 ALLEGRO_EDITOR PADS_IN Some RULE_SETS cause the PADS translation to fail.8 c6 v, `6 o8 Y, F: ?
747746 ALLEGRO_EDITOR OTHER Request for more detail in downrev.log file
) _: H; x1 T) D748033 GRE IFP_INTERACTIVE Enhancement in GRE where Show Element on Bundleshould show the total number of nets that are part of the bundle0 i2 c( t$ f& R, Z' A* g; v, M
748333 ALLEGRO_EDITOR OTHER place by schematic page number not showing pages correctly
2 e8 ]7 N% S' S, [# A6 A [748375 ALLEGRO_EDITOR MANUFACT gloss - line smoothing causes crash. V, c2 s: a) t# J$ \
748818 ALLEGRO_EDITOR DRC_CONSTR Undesired DRCs shown in allegro 16.3 while moving component and the same are removed by update DRC
/ H Z4 N C6 Z- U3 G" Q748865 CONSTRAINT_MGR OTHER Allegro 16.3 slow to move component with CM open' s( }9 I) H7 x9 B' Y3 o
749009 APD WIREBOND a part of function of the finger alinement doesn't work7 m$ k* W) D4 }9 f/ t8 p4 b
749162 SIG_EXPLORER INTERACTIV Unable to proceed after RMB > Preference > Cancel2 s: ^$ L0 s* C4 g% p
749307 ALLEGRO_EDITOR MENTOR mbs2brd fails with error VIF_Allegro_Write C, Y, I: R- N+ r& d; v0 L
749435 CIS DESIGN_VARIANT Cannot create variant part in 16.3
8 @5 E2 B. B C5 I6 {2 C; \' b749854 APD PADSTACK_EDITOR The value of user-defined mask layer is not retained in the design.3 w/ w; v: v( Q) W; B
749891 ALLEGRO_EDITOR PARTITION Unable to delete existing partitions! u9 c7 w! w9 Q3 ]+ I% \
749949 SIG_EXPLORER EXTRACTTOP A Topology extraction fails using APD and SiP series with the latest hotfix(SPB16.30.001).
1 ~ _! z2 x( ]+ w750008 CAPTURE NETLIST_ALLEGRO Netlist different in SPB 16.3 and after installing SPB 16.3 hotfix 1" r: q2 z4 H7 m5 B/ V+ c( b4 g( F
750591 ALLEGRO_EDITOR DATABASE Analyze diff pair object fails to display uncopled lenght values.
1 n; Y( ?4 o! ?( X, x8 S750888 SPECCTRA ROUTE specctra is crashing while routing
+ ^) i! ]. S* M, e9 U751204 F2B DESIGNVARI Design difference crashes while reading funcview
! a9 S2 g/ |7 W. a% b- @751398 ALLEGRO_EDITOR OTHER Allegro Crash when Edit is selected in Setup > Outline > Room outline
( C2 D, |2 F0 s: s& h/ g5 q% R751578 ALLEGRO_EDITOR PADS_IN pads_in hangs while conversion" y& r$ I, ]0 ?
# i5 Y6 N9 E! ?8 Y& bDATE: 02-09-2010 HOTFIX VERSION: 002( i) S: f3 M, j8 @. ^0 p% J
===================================================================================================================================
3 |6 r, W' L7 [% u- `1 XCCRID PRODUCT PRODUCTLEVEL2 TITLE2 b% f! A. n" H
===================================================================================================================================, d! P# u5 K8 r+ y" _. X
527012 SIG_INTEGRITY IRDROP Severe Memory leak in IRDrop
' W5 h3 C# W0 S% g623678 PCB_LIBRARIAN CORE PDV freezes when changing grid8 Q% j! A* _3 b" J
672592 ALLEGRO_EDITOR SHAPE Shape does not void correctly untill a clearance oversize value is added; g# T- h% J% c& R" i$ q
688062 PCB_LIBRARIAN CORE PDV Strange characters appear when copying text into Bus Arrows ( Text symbols)" B( _! z W, d; A1 l6 [
710170 SIG_INTEGRITY IRDROP Run IR Drop even if all components on the net are not placed.
" F3 Z" ~% ~1 j# B5 K3 r710174 SIG_INTEGRITY IRDROP Audit function for IR Drop.$ L8 U, A1 @4 s& u
726833 PSPICE DEHDL Modify the methodology for migrating 15.7 and 16.2 users of ConceptPSpice) _1 [( I5 U+ L% ?9 W/ K( Y
730717 SCM UI Unable to delete a zero connection signal in SLP which has a pull-up1 [1 s8 U5 B9 A: ^
731017 ALLEGRO_EDITOR DRC_CONSTR DRC's show out of date when artwork is run! O; [5 p+ f7 L
732145 CONCEPT_HDL OTHER Incorrectly generated VHDL netlist
+ n" G' w1 t7 W" N# o- s740123 ALLEGRO_EDITOR GRAPHICS Capture Image command fillin missing from jrl and script files/ u/ S: W& \! _1 P. d9 W; M) ^2 ~
740278 ALLEGRO_EDITOR OTHER Jumper fucntion for Single Side PCB Design
, |. k5 `" _ g8 |) i) Y740656 ALLEGRO_EDITOR GRAPHICS Can we place custdatatips.cdt file on a site level for SPB16.37 c# d% a) L5 e& l( {/ j7 w
741222 CONCEPT_HDL CORE Replace command (in Windows mode) causes crash
0 A) T: e! i& `/ m5 Y" q& ?; b: H _742389 ALLEGRO_EDITOR EDIT_ETCH Change or add message when using Countour route5 @( ]* I2 C; h, e7 x# S) a
743275 APD DATABASE With DRC enabled, this design seg faults in axldbid.c (solaris only). DRC update takes orders of magnitude longer on sun
; Y/ {% p( H7 Q/ u8 k743623 F2B PACKAGERXL Pxl error when using pack_ignore on reuse blocks9 s9 W8 X/ E! {& q
744348 F2B BOM PART_NAME column getting word wrapped inspite of sufficient space in the HTML BOM report., a( R7 c, j# S
745062 CONSTRAINT_MGR OTHER import techfile does not add new layers in cross section; m$ }: p, l! L* h
745148 ALLEGRO_EDITOR GRAPHICS Allegro ptf driven HEIGHT value not pushed into 3D Viewer& [0 n8 m! M0 _3 F, f. M7 v) M
745301 ALLEGRO_EDITOR DATABASE Allegro 16.3 crsh on moving component: q) A, ]7 O P9 q9 K- z
745518 ALLEGRO_EDITOR DRC_CONSTR DRCs not shown when "Enable Antipads as Route keepout is checked in"
; |+ T3 {+ A. @7 w$ i745745 SIP_LAYOUT WIZARDS Die Text In changing the pin names on duplicates
5 a, [) K/ B7 n$ A9 i" u* i" e4 J745785 CONSTRAINT_MGR UI_FORMS Unnecessary window opens when the cell in PCSet By layer worksheet was clicked.
) t& o: F t; s2 N/ X8 E% u; c6 Q746002 CONCEPT_HDL CREFER Could not find pc.db in the root design* B* o; L3 U+ G! s) [
746010 CONSTRAINT_MGR SCHEM_FTB Updating the brd file using the "Import Changes Only" option overwrites the modified constraints in
7 u1 C( k& F$ X) N: z746080 CONSTRAINT_MGR OTHER Click Constraint Manager filter icons crash software
+ V/ m+ d- f% ]746137 APD IMPORT_DATA Import > NA2 not transalating certain layers and padstack sizes
7 n( z9 `# T! l! a- ?+ l+ w0 n746370 ALLEGRO_EDITOR GRAPHICS Setting infinite_cursor_bug_nt variable flips mouse movement on flip design* i4 }* z+ {; N. H5 O
746519 CONCEPT_HDL CHECKPLUS CheckPlus the if statement is not seeing the True condition or the output predicate is not returning the True condition.
& J- T: ^& P/ h5 t) n746546 PCB_LIBRARIAN VERIFICATION con2con choosing incorrect PART_NAME in PTF File during verification# t) k+ Q- r- O" w% V
746865 CONCEPT_HDL CORE Tool generated pspice net names in core concept design cause short with copy all.$ B/ n+ K/ f4 U
747636 SIP_RF OTHER RFSIP Layout RF Module Export chips & connectivity is not writing die attach method to chips file, J! g2 [* g/ N
! E+ N$ ~* l3 g1 g7 z) KDATE: 01-31-2010 HOTFIX VERSION: 0012 ]9 B, V* x/ S8 C: g4 H
===================================================================================================================================
0 D7 I7 K/ g; g2 u5 L) ?) A, ACCRID PRODUCT PRODUCTLEVEL2 TITLE
, m" [3 _1 C5 r2 O W===================================================================================================================================
7 Y" O0 K3 c+ H& J) x ~ o491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute
" a+ b/ f0 H7 W# }; ?496910 CAPTURE NETLIST_ALLEGRO Inconsistent netlist creation
7 ?" e3 x/ S/ q# N5 k& C2 Y558783 PSPICE NETLISTER Why do Models with "awb*" prefix need wirte permissions to "*.ind" files?+ k: i9 ?& u- E+ U+ h
643241 CAPTURE SCHEMATIC_EDITOR OrCAD crashed while replacing cache
1 y% V: Z8 ]+ I# c; Y i654292 ALLEGRO_EDITOR DATABASE Propagation Delay constraint behaves differently between 16.01 and 16.2
, e5 I& M) Z) P; e6 s662829 CONCEPT_HDL GLOBALCHANGE Global Update should honor property visibility settings in ppt_optionset; a9 {* k) h# Z! ]1 }3 y0 S
672718 SIP_LAYOUT EXPORT_DATA "Export>Symbol Spreadsheet" should export a .cvf not a .txt D6 u3 l8 q$ ?+ @+ q1 t
676233 CAPTURE NETLIST_ALLEGRO Cross probing stops working if design name has dots' ~: h& v4 W+ t! ]" X5 Q+ B# J$ J$ L
678739 CONCEPT_HDL CONSTRAINT_MGR Manually added targets in matchgroups lost when reopen CM
4 H" ]( A; f6 b: p( J7 C% N$ Y690618 F2B BOM Write protected template.bom fails to write callouts
# O" M! d" v+ m; _% X( `0 ] u( G700246 CIS LINK_DATABASE_PA Need option to update symbol always when linking part in CIS- W7 ]$ a0 ^/ c' F% n+ d
705393 CONCEPT_HDL CORE ConceptHDL crashes while switching to another hierarchy level under File > Plot Preview.
) x+ s) h V4 A M, o! {708634 ALLEGRO_EDITOR SHAPE Shapes getting incorrectly displayed in 16.24 U% g+ ~# F. D' u8 r2 X; e+ A
708950 CONCEPT_HDL CORE Tool crashes while trying to change the text on the schematic using a text editor.
; @) d' O4 h9 y: [' [3 w: |709823 ALLEGRO_EDITOR OTHER Arcs not converted properly when upgrading symbols4 K4 l* k) w8 |
713964 F2B PACKAGERXL Net property Probe_Number is getting changed during the packaging run# @# `+ {, P4 a5 l' d2 I
718119 F2B BOM Exclude the callout file name from the template.bom file0 [# Q) w W1 R/ c0 [
718496 SIG_INTEGRITY SIGWAVE Frequency at smith chart.9 N. V9 k! e# E5 W q9 _- |
721422 CONCEPT_HDL CHECKPLUS Checkplus fails if "\\" character is used in the parameter list/ Z7 J1 h8 @, X" u0 ^$ z
721788 SCM OTHER SCM unresponsive while closing out a Block without Saving( l' V, `# G( ~' H) ~7 |7 c
721801 CONCEPT_HDL CORE Save As crashes DE HDL if an existing page is selected in the design( T5 ?3 \- D6 Y; O# w
722653 F2B PACKAGERXL Packaging does not complete4 |4 w" \2 U4 x! d4 e- o
725285 CONCEPT_HDL CORE nconcepthdl does not work same as concepthdl for same script.
0 S7 D0 I, K4 C6 ?( v725719 CONCEPT_HDL CORE wire pettern of Publish PDF3 B( w* D# _7 D6 i: P6 L5 G1 W
727062 CONCEPT_HDL CREFER Custom properties not visible for TOC symbol in schref_1 view
7 T0 [, W0 z. T; R" s, b727194 CAPTURE CORRUPT_DESIGN Random Capture crash
3 o6 O: W- ?. e9 N1 `; Q7 R4 W727704 SCM PACKAGER ASA to PCB getting out of sync
9 F; Q, ~7 w9 U7 }728066 CAPTURE NETLIST_ALLEGRO Allegro PCB Edtior net cannot be generated if PACK_SHORT is used5 A7 y7 Q% S1 J7 o; X
729214 CONCEPT_HDL CORE SHOW_PNN_SIGNAME directive used with Windows Mode gives crash+ Q" s5 A; ]- q" g- @' q
730295 SIG_INTEGRITY OTHER Filled rectangle shapes not extracted properly+ \: Z3 w/ Z9 T$ g) O
731183 CIS QUERY_DATABASE CIS Query fails with ODBC Error for query (Price contains 29): Q7 m D3 T! ~# P7 F
732073 SIP_LAYOUT DXF_IF DXF_OUT generate an incorrect shape& u9 c6 L' F# J1 K Q- H
732138 CONCEPT_HDL CORE Cannot change SI model assignments4 [5 A; x/ S8 p, e5 G' \5 f
732216 ADW DBEDITOR dbeditor crashes doing copy-as-new into lib folder that has partially completed chips.prt file) r) C7 ^* S5 y, t& J) y
732249 SIG_INTEGRITY SIMULATION Probe sim with custom stimulus cause segmentation fault. Linux only.5 R, t) R+ r% J4 G6 b
732847 ALLEGRO_EDITOR DRC_CONSTR Manual Void uses Shape to Pin constraint to void Holes0 W1 }$ K9 w* g: L5 Q& N
733261 FLOWS PROJMGR Project manager does not work with the Restricted User in client server environment
; V5 Y9 W" l0 A" `/ r5 C& x/ w; g733773 CONCEPT_HDL OTHER Syntax issues in DEHDL
: g% b: g1 A! m734260 APD COLOR Why subclasses still remain visible even after global visibility is turned off.
0 H( l$ X6 b+ z* C1 ~734419 CONCEPT_HDL CORE Concept crashes in windows mode when netname is deleted on schematics generated by ASA$ _, ]( T# _6 f
734555 CONSTRAINT_MGR SCHEM_FTB Import Logic does not overwrite the Constraints0 Y% D0 @2 L" M0 l
735290 CONCEPT_HDL OTHER Concept's PDF Publisher has issues.
' B3 x' B6 t- @2 i; b735892 CONCEPT_HDL CORE "Component Modify" changes visiblilty of Key properties, V' k4 O3 j* z% P
735977 ALLEGRO_EDITOR MENTOR Mentor to Allegro translation fails without any error message. K( b7 e2 ?+ e; c2 G) m9 i
736071 CONCEPT_HDL CORE Property visibility is not retained on the schematic instance when we modify the component on sch.
) k- e y h9 G: X5 w736165 SIP_LAYOUT SCHEMATIC_FTB about error message of "schematic to layout"
8 }% |' N) ~4 L' s736167 CONCEPT_HDL CORE HDL crashes when I select BGA symbol in Component Browser
( {7 _. d0 q$ l3 C736911 ALLEGRO_EDITOR SHAPE No DRC displayed when Place Bounds are edge to edge, c+ l$ S# m$ W2 L! I! |7 y
738035 ALLEGRO_EDITOR OTHER Measure function has different result between 15.7 and 16.2 version.
0 x$ |" b* g# m/ a5 p- I0 w9 f/ k, P- {738129 CONSTRAINT_MGR UI_FORMS Need Diffpair Constraints option in Analysis Modes Electrical Options with Performance license
& m+ S* d& S! ?1 n- ^4 V738276 ALLEGRO_EDITOR PLACEMENT No feedback in console window when placing unfound components in Allgero 16.3
F2 Z; Q# F+ I! W5 U2 y738366 ALLEGRO_EDITOR GRAPHICS 3d viewer not showing some connectors with mutliple place bounds correctly
5 L; i. o3 Z* ?* m8 g5 t& D2 y738454 SIG_INTEGRITY FIELD_SOLVERS EMS2D extracts incorrect CPW to Trace spacing) _) W) l: Z% O9 @, s3 g9 J" k8 P
738578 ALLEGRO_EDITOR OTHER scriptmode +w doesnot work on Linux2 \+ r1 V4 {; C+ ^" d) o
738869 ALLEGRO_EDITOR OTHER Error msg when cds.lib contains missing SOFTINCLUDE
+ w/ L6 ^7 H8 D( l# B8 E% Q739116 EMI SIMULATION At EMI simulation on SigXP an extra Sigwave form is launched.
+ _1 Y, G/ k- s. F/ \: G739225 ALLEGRO_EDITOR GRAPHICS Ability to lock the 'Hide Pallette' option
* x& x2 d. Z0 Y9 P H1 B739599 ALLEGRO_EDITOR DRC_CONSTR drc_errchk indic* W. Y/ Z+ U# F* Q
739628 ALLEGRO_EDITOR SYMBOL Opening a symbol file is crashing allegro.
; o+ J( `5 A; v9 h+ q739653 ALLEGRO_EDITOR SHAPE Shape created in 15.X .dra changes geometry when uprev'd to 16.X
B! u( g$ k5 h% p* \% K* _739661 ALLEGRO_EDITOR OTHER Export netlist creates incorrect via_list syntax.
! P* ]' A$ _1 B- a, N4 M/ i739872 ALLEGRO_EDITOR SKILL Crash while performing axlExtractToFile in 16.3
* F8 L- x4 a# ]& @739934 SIG_INTEGRITY OTHER specctraquest crash on changing signal model1 ?5 `# ~4 o4 G. h4 c. A
739937 MODEL_INTEGRIT PARSE zero valued estimated parasitics in ibis models: a/ V8 h2 U+ @! ?, ^
739942 ALLEGRO_EDITOR SHAPE zcopy xhatch shape creates oversize copy) S2 l5 w( {; W% T- w% R! m: j4 z& d: \5 Q
740133 ALLEGRO_EDITOR DRC_CONSTR Same net DRC Update from Analysis Modes runs forever.
. c9 ?6 k4 k- z$ f740281 ALLEGRO_EDITOR OTHER Jumper components where were placed in PCB disappeared, }# h A9 E1 p7 @4 ?" b
740309 SIP_LAYOUT DIE_EDITOR Moving a die pad in DIE EDITOR on G69A_U1 causes the die pads to rotate 90 degrees from the design., u& h& X5 k( b6 B7 i3 f
740399 ALLEGRO_EDITOR COLOR Cannot automatically load custom color palette in 16.2
9 U- Y- d! B# L741210 ALLEGRO_EDITOR DATABASE Edit >Move; spin creates 'connect record not found' message5 F( J( T( b& X+ Z' X8 K
741307 ALLEGRO_EDITOR PADS_IN Shapes on some layers is not getting translated from PADS into Allegro) p: u! a% a- C2 P+ j1 i
741313 ALLEGRO_EDITOR DRC_CONSTR Add connect slow in 16.3
1 Q4 V% [) L& q# P8 u7 {5 Q741778 ALLEGRO_EDITOR COLOR Color pallete in 16.3 is not expanding when maximize dialog
1 L/ r/ j: m1 B5 \! V7 x6 c741910 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd
+ Y& E" H+ Y" |# {6 o8 e& j3 u0 d741939 ALLEGRO_EDITOR PADS_IN PADS to Allegro Translation fails or hangs.( \! P" b' V5 h7 o8 E0 Q+ w
741980 ALLEGRO_EDITOR PARTITION Import of parition does not import etch or vias.
4 S: l+ n. L. M* |& M$ p! I742676 ALLEGRO_EDITOR SKILL Tpoint cannot be moved by using skill.- I: j+ I3 N O- |# M
743161 ALLEGRO_EDITOR SCHEM_FTB Netrev crashing when importing netlist into board file.# W7 E* U" q1 P5 M; m) L+ W; s1 ^
743235 ALLEGRO_EDITOR PLACEMENT Allegro crashes when unmatching comp in placement replicate.! C5 n4 f: t, A& s
743243 CONSTRAINT_MGR TECHFILE Closing CM destroys tcf values when they are set to locked using fObjectNOTReadOnly
! L7 |# k, H' c0 ?+ A+ a0 W. Y* R743301 SIP_LAYOUT DIE_EDITOR Edit die command creates two extra die pads
5 T, z. {5 Q) a q& v743316 CONSTRAINT_MGR DATABASE With Allegro 16.3 Constraint manager takes to long to update( n: ^3 A- e% A1 d3 F8 i$ W
743553 CONSTRAINT_MGR OTHER Net disappears if we cancel the line width edits in CM
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发表于 2012-1-11 21:45
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