|
|
' [7 l" {+ e# g' k5 V4 e9 N1 t
DATE: 12-8-2011 HOTFIX VERSION: 041
' V2 N9 I9 L2 r2 d$ K& t===================================================================================================================================2 y: Z' {6 b% _9 F6 e- x: X
CCRID PRODUCT PRODUCTLEVEL2 TITLE
1 F5 {7 C$ x. g) V# {4 }" M2 e===================================================================================================================================
' P; h1 ~/ b) h5 [6 K! Z6 q875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.( Y* k$ Y0 ~3 M' j6 l* O* ~
944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently
" ]3 w6 c+ f3 X& ?3 N3 r# e& V4 A4 o946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat
3 M! D* p# B$ [' S. h( i$ B& W& h9 O1 [951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original( P8 z" ^3 C+ C. s- H. ^7 s
952057 SCM PACKAGER Export Physical does not works correctly from SCM0 P3 r6 i& J( e5 ~) T6 [
953018 APD REPORTS Shape affects Package Report result.
/ G) s5 V2 {( D2 x% `1 J953279 SIG_INTEGRITY LIBRARY mkdeviceindex is adding dml file listing in env file) J& h+ i+ O# y1 a
953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro
) E o5 T r1 K# x' _2 z953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly- l6 k" w1 [# m8 `$ G
953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "“separate files for plated/nonplatedholes”* f; N4 [7 W' D
954055 CONCEPT_HDL CREFER Crefer fails with UNC install path
; J+ `" j3 l6 u! A' n: n3 I954858 CAPTURE LIBRARY_EDITOR Closed polyline used in pin shape is not appearing while using custom pin in part.
" K0 R: \* q- v$ D4 J$ H& L955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view
5 n+ n+ V" }( @0 E \955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side./ ?! j/ j. m' o1 y+ l& \5 L% ?
955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039
& U+ d$ m5 @! p& x955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME @ J0 W( C2 r2 i M4 x; Y% [" p( L
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly
6 {5 i) j# X; L8 X958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design. S. J# d' J& M$ I! w% s$ t) Z1 m. N) g
958945 CONCEPT_HDL CHECKPLUS Checkplus from 16.3 is not running with our "Allegro Design Entry HDL XL (16.5 licenses)
9 s) w' @$ \9 D$ O, s' U8 G4 w# z T! d
DATE: 10-21-2011 HOTFIX VERSION: 040
! k0 n# V% I) w) w* Y" r. c===================================================================================================================================
- I7 a+ w# C# ZCCRID PRODUCT PRODUCTLEVEL2 TITLE
$ i7 C- V2 z' i, W# Z===================================================================================================================================
' ^+ c: X0 u% {9 X' n' t/ W' _735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape
3 }/ t7 P9 ~0 k2 [935438 CONCEPT_HDL COPY_PROJECT Copy Project changes read-only hierarchical block permissions
% w0 J3 S- c0 Y3 G7 j935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic
- B) _5 p; F9 A& T/ E1 \4 ?1 R937165 SCM SCHGEN Can't generate Schematic7 G! A' d4 G; ?* z
941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!
& w$ m- u7 ?. k6 i; ~( w941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen
( m R# E9 Q" t0 _$ Z# S% A* v n942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel
2 u# P1 V; w" p+ {6 l; f943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.
# [! l. L( D8 W946350 F2B DESIGNVARI Variant Editor rename function removes all components0 C. E! K' Y( W
946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form
4 [& E4 b5 Z2 Z5 y- H4 N947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.
/ k& E- D# W( x
|1 i0 Q' Z$ T. R% r* lDATE: 10-6-2011 HOTFIX VERSION: 039
2 ]1 u' g4 o; c$ x2 h e0 q===================================================================================================================================4 F! D; Z+ D* \4 i$ d( X
CCRID PRODUCT PRODUCTLEVEL2 TITLE
9 p7 i5 b! C7 \3 s% N===================================================================================================================================& t5 B; [2 g8 Y
841096 APD WIREBOND Function required which to check wire not in die pad center.- u1 t: U3 m' z8 L
912942 APD WIREBOND constraint driven wire bonding' ?: u3 @; B2 X1 Z8 m' Y& l
917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors6 Z: h! N7 x7 W: a5 Y' n
923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure9 N1 H' v( f% h6 B7 j8 V1 `5 b6 |
927950 APD DATABASE My customer name their layout cross section subclass name as “wire” in Die type.
0 u" q5 a6 N1 j- _0 Y( ^929348 F2B BOM Warning 007: Invalid output file path name, S* z+ |8 G- l% Z5 J/ S- C" g z
930783 CONCEPT_HDL CORE Painting with groups with default colors$ B7 w- X) n0 N7 Q" B6 b, f0 y
932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property0 T- D) n/ @% j- O
932871 APD GRAPHICS could not see cursor as infinite
7 x" H0 q2 C6 A) n( H* v933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.3 p7 f) J; `" E2 X4 {
933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass% O# c5 u# v8 t2 W0 y
934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values
% \) c5 j2 B6 o ?934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file, ~, H- `2 k* l* h/ F a3 S! g
935911 CONCEPT_HDL CONSTRAINT_MGR Mapping of constraints fails after importing layout constraints
5 b! j1 x' v" ~936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.$ G! G- \+ q. i; {3 t# l2 |
936794 CONCEPT_HDL CORE Unable to select Allegro Design Entry HDL XL
" {- ]; J0 b" l/ ^937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE
& w* u& }7 H/ R; ]' ^937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About" c8 w1 S* ]6 A5 g: r+ L, B6 p
937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.. r; Z2 e4 A3 v6 q, C W4 G) B
937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.: d. W9 A; a E, B2 \
938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR; f8 A5 X2 g: L' I4 s( O% d9 |
938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins! f2 r/ x4 V) h5 _, m
939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.
8 W7 ?3 h) P! q( C$ j9 E) O* \! A940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'4 {8 s& m2 V) d9 p8 L7 @
3 c4 S/ l. R# S4 W( N& u
DATE: 09-21-2011 HOTFIX VERSION: 038, ]+ Y ]$ ]3 }; X+ @5 j' n
===================================================================================================================================: U3 W4 D; L' S5 J5 a& `1 p1 F
CCRID PRODUCT PRODUCTLEVEL2 TITLE! W1 U" [+ o8 v& k4 w) Q, ]
===================================================================================================================================0 P4 z& _2 J. v9 P- X5 K$ e2 b
924448 F2B DESIGNVARI Design does not complete variant annotation! s1 y2 ~, O/ |2 s
927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values' ^; e2 A7 \/ @& B
928738 PSPICE PROBE Y-axis grid settings for multiple plots
2 x6 l/ b- t4 ]$ I929284 CONCEPT_HDL ARCHIVER archive does not create a zip file
" |/ `7 E9 a4 k' Y) [930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape
1 u! S8 w4 u. ?930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation
% B. m$ I1 I9 n930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command3 O* n- P1 d4 W9 l0 p
930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name
( e$ p4 m8 h+ c& N( z6 ^8 D3 S- A' l4 r930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens
$ \5 F( n% n2 v: m! C4 v931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets., m G ?- w$ ], A4 n: V8 z' i3 M1 U
931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.
3 W8 P* P& ?# Y$ y. H% u932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.5 E+ N8 V6 U3 F/ f
933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown
" k S( L) x. b9 r
' m P h) `+ _ v$ }. RDATE: 09-9-2011 HOTFIX VERSION: 0375 Z3 Z& ~5 m6 X) Q
===================================================================================================================================3 ?4 c- o, [: |
CCRID PRODUCT PRODUCTLEVEL2 TITLE, J: w& e; A. K, D8 l
===================================================================================================================================; T6 D- b/ b) `4 F$ v
734687 PCB_LIBRARIAN IMPORT_CSV PDV Generation of entity view fails after CSV Import3 f+ c& g" V& B% n, W. V
734718 PCB_LIBRARIAN IMPORT_CSV PDV Import CSV corrupts parts and generates duplicate $PN on some pins) x, R# h3 s/ r$ N& y
820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.
, Z* {! l% \+ `- }5 L! t' N868712 SCM UI Why can't I modify CAP associated component?% i' ?+ i9 u. P; e- S# {# Q, y; ^3 f
920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus." c5 B+ `, A: r9 _
922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes./ h4 w8 [% X9 ? B# Y
925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way) i: {0 a1 d( \, ^ N
925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?' {! q$ x, ^' {
925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data
# ], L1 J. D2 P+ I- \" z926503 CAPTURE GENERAL Memory leak Capture/Pspice
, _* S9 v+ @6 |: m0 t926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical3 K# o4 o: M4 l# p6 w
927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.6 G# g$ _ V" N" w
928286 CONSTRAINT_MGR INTERACTIV The value of pin-dealy has gone with long match group name.4 C& n! \7 x8 q
928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list
! B& f) J+ K$ ?0 S929174 ALLEGRO_EDITOR OTHER Display mesure get different result between 16.5 and 16.3
/ ^; {3 v: u. p' w0 }3 r929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error) S5 z4 c/ q9 I$ o$ M) Y
7 X, J/ J) {0 u* `' D0 xDATE: 08-26-2011 HOTFIX VERSION: 036
3 Z/ M4 |! D/ O===================================================================================================================================
! c1 J3 ?) K8 O) F% A- y' O2 b6 XCCRID PRODUCT PRODUCTLEVEL2 TITLE( C5 ^6 b* K \2 x3 i
===================================================================================================================================- ?3 j+ L. {. v6 b6 u& K+ Y" p2 w
891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode6 n8 x, e! S; L/ y
909595 APD LOGIC Inconsistency between export die text out and show element after pin swap
1 Q# X* {5 K, ]1 G3 b. j914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity# Q" P. w6 R- E) G% g* s
916321 CAPTURE GEN_BOM letter limitation in include file
' Q4 M8 _" U9 p917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.
( ~$ b0 f, b0 X1 N: ]919976 APD DATABASE Update Padstack to design crashed APD.
0 p- p6 b F- \9 f7 t( r. V& u922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all
2 S! h. Y1 i2 S: O1 J6 _1 b4 ~923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.! M4 ~7 n! G! p
924458 SCM OTHER Project > Export > Schematics crashes& G! I( W* M8 Z4 B
924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.
" r7 F. h0 q% O8 S; C925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect% q1 ^; v$ d/ R; o# O+ {: V" G
926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.. E a% M$ e# R! T; v
( E# p+ \$ ^+ Z) B5 r' B/ Y- aDATE: 08-12-2011 HOTFIX VERSION: 035
0 v* Q) @2 q( R* t===================================================================================================================================+ j0 n g% Z2 k2 y
CCRID PRODUCT PRODUCTLEVEL2 TITLE
/ s' U5 X2 H; D! I! g===================================================================================================================================
$ P+ ^7 ]: L/ X( |2 S861956 CAPTURE IMPORT/EXPORT V16.3 is not respecting if the net names were written in LOWER CASE or UPPER CASE in EXPORT FPGA.
5 t7 b7 L3 j- o* C868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments, t8 z4 m; D' k. C6 P' Z G/ X
870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file
3 T3 k8 L3 r0 O874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.
- S# J; Q0 f: \8 G" S882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.3 |. r( v0 k0 m% V- C
895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1' `% N0 ?# O! A! M! r' l
895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement
+ y) j, k% [, O. [903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly. I( Z E. ^- h1 V$ G/ Z/ x
905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible
5 i& p" b2 w: y. {905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function. @3 M( W0 t9 N: o
905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged5 T' m8 f- A4 I4 b) w2 K# w0 a5 T7 Z
915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models/ c R/ Q2 I: T- }
915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP
* g/ Q' ~4 \+ a5 f1 M5 [# K' \916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor& h" ^9 h' P) _1 Q
916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer
4 P3 N$ ?) d, ^& A5 t( j' }917434 APD OTHER Stream out GDSII has more pads in output data.
) [8 |% C( h7 s3 Z3 n, y6 U918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.
/ }+ X$ q5 N# J: q3 K4 z918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol
3 g3 l5 a$ E8 L* P+ F( n# Y919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file
. x( c8 k& ]7 _/ j) [$ A% C919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working f* A9 S- Q* j, b" ~5 Q
920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork
2 ^0 b/ p+ p" w, L2 S( |7 \$ z7 x
; c W! }; S! C cDATE: 07-29-2011 HOTFIX VERSION: 034
$ ~' Y8 G/ |2 w% }7 s& N===================================================================================================================================$ x7 k9 Z8 O T9 |2 ?) b% E/ `; k
CCRID PRODUCT PRODUCTLEVEL2 TITLE
/ p' G2 f: F6 p( l===================================================================================================================================
$ p; J' ?1 V/ o9 b5 e8 n! o) T# }882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE
8 f3 [, r9 ?1 p% c- G2 g; o8 A6 a897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library' P* J# b, I6 @% F. d1 b8 ^
902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains
; j9 b. O. O, f/ Y* D+ |/ C903719 ALLEGRO_EDITOR INTERACTIV Nets highlighted by netclass cannot be selected on the canvas to dehilight
$ [ W# v0 H; P3 [903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics
4 P! E# a6 \7 X# @/ @904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.6 N) T( g6 u( C2 n* ~ T
905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues6 x( V7 v7 `& d- e; h3 v4 |- w
907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31: a9 \1 P* }, P0 M8 h' Q$ n% L
908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name
( w7 W7 d# k8 x908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.33 p u e1 z! n7 k4 L
908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance' _) a* F: _7 `0 L: O: Z
908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature# ^5 G6 n7 d6 X6 b" c! |1 ~
909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout! Y" T. A; K3 D8 W
910713 F2B DESIGNVARI Variant Editor crashes when you click web link under “ hysical Part Filter” window.( h9 |; e- o, W( P+ d
910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent
' S9 ~) v* n4 y911415 ALLEGRO_EDITOR COLOR assigned color cannot be removed
! q1 H$ X' S. t9 u# |0 |9 x912343 APD OTHER APD crash on trying to modify the padstack( k, D( [( C9 \# q4 J3 M1 Z
912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys% M, f- n: G6 S& U
912459 F2B BOM BOMHDL crashes before getting to a menu
; ]' C$ Z( a6 M; `2 ]0 g( W912853 APD OTHER Fillets lost when open in 16.3.
4 s. t3 U z' Z8 Y6 p( n913359 APD MANUFACTURING Package Report shows incorrect data8 ]( d! ?4 d/ P+ y7 E
913521 ALLEGRO_EDITOR SCHEM_FTB Netrev error “(40) Object not found in database” for a part which is packaged correctly in FE
* v' |3 \' _/ @% ] |6 p913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.
7 m+ s4 r8 z4 Y$ L' H/ Y914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.
1 f; g/ ?& V, L+ z+ X914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape
3 [1 M, r9 J& [5 P, @915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol. F* i/ a# p( q: _& O
916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report6 l! Z/ T2 i V% M3 W, j
' m! \$ }2 y# J7 G) F
DATE: 07-15-2011 HOTFIX VERSION: 033: g( ~! z W; d" C9 n0 S
===================================================================================================================================
- e. B! K8 C1 w. d6 V- fCCRID PRODUCT PRODUCTLEVEL2 TITLE
# M8 n, p" ~& a0 _===================================================================================================================================
, \8 e% ^, u1 o0 U9 w6 N746562 CONCEPT_HDL CORE Deleting attribute causes other property value to move/change @( L( z; @: e: D# I
902349 CAPTURE LIBRARY Capture crashes while closing library0 _; ?4 v' t, \7 f9 a# w2 u- x
903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?
$ F) Z" k4 o$ [# @4 k' n( q903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition }0 z0 ^2 U8 ^% h: f. F
905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.0 @* ~# r4 i4 F) v0 l, g1 ?
906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.6 ?) I- j% [! R) `
906517 PSPICE PROBE PSpice new cursor window shows incorrect result.3 J0 d6 `' x& a( q2 ?% c I( I0 Y1 e
906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.! f% j' q1 L* y$ [
906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation6 ]; ^7 `4 u& l) \' n$ U) U r
906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin
5 e& K$ P* z. t& Y- j907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used8 }! R5 s0 \0 E: ` v% _
908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.' y+ z: |& z' m! w% i# [+ j% S9 y
908595 APD 3D_VIEWER Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b
" A4 S4 u: n/ k9 S3 }3 w0 h908849 CAPTURE ANNOTATE Getting crash while annotating the attached design- n7 W' I# Y5 X! S* \0 z# G8 W
909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack, M$ H |9 F1 S& `. }
909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031! N8 }, ~* |/ N: f/ [3 |
a$ N! e* X8 QDATE: 06-22-2011 HOTFIX VERSION: 032
9 Z, i1 ?7 C1 G1 t===================================================================================================================================
4 m: E% D! J) H! \: w2 W/ ~ VCCRID PRODUCT PRODUCTLEVEL2 TITLE2 C9 j, \, }) Q5 p- p
===================================================================================================================================
' w' T$ I" u. o" V* c774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.; @, [% R. b* D# Y/ N
833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL
# ^' e& r! M8 _$ H% U; b7 \8 _893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.
& ~" g8 C3 M- P893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.. @. Q6 s: B0 q0 F
895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs N! a2 f- ? H) i e( c
897484 SCM CONSTRAINT_MGR No match found for 'fileops.txt' in the search path
`2 K, }( y4 e! m2 H* q! N) {899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.' P1 C: T; N+ G1 f) Z# @
902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design
% r s, V9 U+ q903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.6 P( X3 j$ x; V- ]
904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module
% Q. p. R* l. n904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.1 j. T3 z7 ^+ i
905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM
$ z, l- C) J+ c# u905273 ALLEGRO_EDITOR MANUFACT Drill legend creates more tables than nclegend creates tapes6 Y$ m) G: D' v/ ~* P4 C8 Z
905314 F2B PACKAGERXL Import physical causes csb corruption
' C1 G$ Z* t! L9 ~4 o9 h% R& B" D7 t5 C$ ?: N
DATE: 05-28-2011 HOTFIX VERSION: 031. R3 B, b5 X1 R% _* A) u
===================================================================================================================================
% v, g& y: [0 c. \: x8 _CCRID PRODUCT PRODUCTLEVEL2 TITLE9 a! Z3 a* Y4 G2 m% k
===================================================================================================================================
# ?* H( `& Z- d! |606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart
5 u- n" l! [- b& N) c P4 m. P644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor
6 O7 ~3 {4 m$ z/ J799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write5 U) T1 Z$ ~8 [# M" y; I3 v
866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line$ f8 w1 u" }$ @
866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF
; W8 z- [- k h2 g# v* L* ~' ]/ B2 R868618 SCM IMPORTS Block re-import does not update the docsch and sch view
+ {0 |# o. m2 D' @$ k869971 SCM OTHER Lower level hierarchical block schematics missing $LOCATION values$ d }& Y+ I: b M; |! m
877091 CAPTURE SCHEMATICS DSN file size becomes very large after placing picture and not change after deleting it
5 {7 F( g* [. b; r e L% T Q879361 SCM UI SCM crashes when opening project
) b! Q& n1 X7 Y; T5 ^, e5 t879496 CONCEPT_HDL OTHER Customer wants to have “the tabulation” key as separator in HDL BOM.3 A1 n$ o. w, d( G/ h# }' y
883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder
' i) W1 e+ Z) d$ ?" n+ m885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.( Y# n9 o6 N/ B# W. F! T
886007 CONCEPT_HDL CORE All the read only pages are called PAGE1 in our hierarchical design
3 R/ t" _6 {; ^! X( d9 W1 E889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net
$ D1 A7 V+ v' M" e, I4 O* n; s# |0 J892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.
$ {, j: a3 p( Q9 f9 `9 o) V892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness/ Q8 e5 x- e: o: j) R, `
893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.
U) M. l N' S2 n. Z5 q894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.& }" i2 o& ?/ @! B
894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.
+ _6 } [' u( y) f2 Q2 g( Q3 [895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON
, c1 U8 \) ~# q$ E895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers
+ k/ V7 B7 l, [" s; Z1 [' _895757 APD ARTWORK Import Gerber command could not be imported Gerber data2 g. N) \. H) v' y
895964 CONCEPT_HDL CHECKPLUS The CheckPlus command “getFileSubstrings” is not working correctly
9 Y- \2 @$ g6 \. g% R* ~0 i896302 CAPTURE LIBRARY Pin spacing option in Generate Part from spreadsheet- x1 H: a8 a! B* q# l
896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced/ D/ Y0 r! H' m. _
897362 CONSTRAINT_MGR TDD Unable to create Region Class in Constraint Manager
+ {6 r, R7 S& `: @4 Q) A3 V# M897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.
: v: n6 y) K# z1 q9 _898941 ALLEGRO_EDITOR REFRESH update symbol moves refdes location of component placed on bottom side* g3 E0 w2 ]8 z2 A$ `" j
899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing: S; {* F- C) K; m( ^
900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.
0 E# T+ P9 X/ D9 }+ E: q900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration; P; m6 c5 U9 o# S9 Z
900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.
$ V& r" f1 |# z$ t900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.
; m L1 D" i2 l0 P/ E: [901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong
$ A; b6 z+ a2 Q1 w902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic: U' D* e! D; b: `6 E5 m4 p4 ~% K
902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file
2 E, f* }# d# {902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization
( A+ p& R; v: r3 F902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components8 S: n2 d( p, J. Z2 T/ u
902909 APD WIREBOND die to die wirebond crash
/ c9 C5 n4 |( a, V! [: k902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body. [; b/ ?7 H5 s4 |( l& q# e) v
+ k/ f Q" I2 o* S7 ~DATE: 05-14-2011 HOTFIX VERSION: 030# N) \1 z6 \ o, q
===================================================================================================================================
# F- r8 E y8 F8 Z4 q# pCCRID PRODUCT PRODUCTLEVEL2 TITLE
2 w8 g- R$ E) J0 I) }. y4 P===================================================================================================================================8 T- ~3 {: b! O- c7 h {
738247 CONCEPT_HDL HDLDIRECT Generate View hangs
$ j& h. [7 A: D% o \9 B803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part
5 U: \; ^8 R* n+ U837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version5 Z0 o# w% j$ P1 l! r
838763 CAPTURE GENERAL Deadlock situation is reached while opening BOM reports ("<something>.BOM" cannot be opened)
6 q; m% k/ O. \2 c7 g858245 CAPTURE IMPORT/EXPORT PCAD import does not work in 16.3. I' g" y0 q1 f
860905 SCM UI Part cannot be replaced after it's added
/ o- E+ v' F9 o" j6 `869528 CAPTURE SCHEMATIC_EDITOR Refdes increment on copying part is not with respect to occurence value.* A) [5 J* |3 _! Y, [% S
873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP8 p8 O4 t" M: I5 ]# s6 y
877994 CONCEPT_HDL CONSTRAINT_MGR Assigning ESpice model to active component with Class; k3 H; z1 @5 }! d$ }; W! ^
883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component
4 N o0 G+ c3 Q* g `! u887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.
. l0 g/ S! B; X/ G4 O887477 CAPTURE NETLIST_OTHER Other netlist is missing some nets and components after refdes changes in the design
, N7 D9 ~0 x: l2 C @5 P887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message
" D+ u# ~: m! y4 d. q( G887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.
; o$ I) u* r! P1 J( L888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.
6 H: D! j% }7 Z" b6 K2 v; S888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic1 N4 _9 k' V4 X$ y, Z
888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.# p$ t7 C4 J, k& Z
888945 CONCEPT_HDL OTHER unplaced component after placing module5 X% o- U5 ?; T$ o% E
889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3
) U: f& n! ]1 F+ |889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.
2 u- [/ X$ g& M. O- A4 H889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form) {8 S' j7 `9 H" `
891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file
$ [9 G; _4 i# l6 H( g, r: \" _5 I891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs" i2 U. r% m. O+ S3 r, }$ \! E
892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?
$ U/ _- l4 p+ L% J' r/ l892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode: C7 S6 \ c* `
892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations; Q3 }# |5 a5 u+ A$ G4 G
892991 APD BGA_GENERATOR BGA Text In Wizard creating two refdes text at the same location.* p) I# x# Y `
893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.
3 K4 {* Z& i# W' p% M
. J0 d& U. m2 t. TDATE: 04-22-2011 HOTFIX VERSION: 029
: P' H) S* y+ S0 ]2 X. Z2 `: P===================================================================================================================================3 B3 p: v: F! M; M$ X. R
CCRID PRODUCT PRODUCTLEVEL2 TITLE6 m; [6 ^4 f: E# T& K* @
===================================================================================================================================
+ I7 r" o8 }5 v V5 I. K( M789198 CAPTURE PROPERTY_EDITOR Newly added user property to a symbol can not be moved on the schematic page.
; Q, Q( s c* q" {7 X812501 CAPTURE NETLIST_OTHER Extension of PADS netlist is .NET in V16.3. It should be .ASC.$ W+ k6 C1 ^7 a/ p. ]
842161 CIS GEN_BOM CIS standard BOM taking long time
# R C/ g% P, ]" e @3 {844125 CAPTURE NETLISTS Normal and convert view placed in same design don't get netlisted due to duplicate power pin names.) m! v+ C8 [! r& Y4 O8 l
847688 CAPTURE PROPERTY_EDITOR Property Editor changes selection on Display# g$ f$ ~! O. y& l9 X! ?
851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.' Z2 h' C, e1 w3 o
862785 CAPTURE NETLISTS RINF netlist with net attributes generetaed by capture 16.3 is not getting loaded in CADSTAR tool9 S/ c" G5 x! Q/ `9 O% `
868118 CAPTURE NETLIST_ALLEGRO Differential pairs not getting netlisted in hierarchical design.
6 o+ K4 n2 d9 L# E5 }1 e: Q880219 CIS GEN_BOM Standard CIS BOM does not viewed properly if underscore presents in Part_Number property
4 J2 q8 Y& b. R! f5 F881792 ALLEGRO_EDITOR SHAPE Cannot Delete the Islands on the shape. No Error reported., Z: \- g4 `5 C6 A3 ]- v, h2 z7 o2 i
882128 SPECCTRA HIGHSPEED Difference in length report between Allegro and SPECCTRA
1 e6 z/ x% K! @5 |5 r# E883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager0 j/ C4 T6 v8 E# {
883291 SIG_INTEGRITY OTHER Z-axis delay causes incorrect actual values for delay
2 e+ ], m6 o! x8 C& F7 n8 C% z883971 APD EDIT_ETCH APD crashed when I tried to add cline in (-6674.79 -7506.74) via.$ _% i+ V/ Y3 J* ~: k
884061 CAPTURE SCHEMATIC_EDITOR multi-line text zoom doesn't work correctly7 S; d5 x+ v! p! k+ `
884181 ADW DBEDITOR Parts get released anyway without any errors flagged.
/ `/ F$ s" f' x& z Y885019 CAPTURE GEN_BOM Create BOM causes Capture crash with include file
7 T2 F* X/ j1 w8 K+ J! O v886437 ALLEGRO_EDITOR SHAPE Change of behavior of NET_SHORT between 16.2 and 16.3
! P/ V$ Z" L' W" G: z3 m& \887190 ALLEGRO_EDITOR PADS_IN getting parse error during PADS to Allegro Import
" R2 b: c- y. \887348 ALLEGRO_EDITOR MENTOR mbs2brd translator crashing without any error message in attached testcase -v16.3s027) x# ~' _$ \1 [( d4 b9 p9 X
& D2 i/ |+ u4 n" ?$ `
DATE: 04-8-2011 HOTFIX VERSION: 028
3 y) }$ P2 i J8 Z2 o2 k===================================================================================================================================
; n) l) _9 |, V! m8 r; LCCRID PRODUCT PRODUCTLEVEL2 TITLE
4 w% t% j8 D4 c% ]===================================================================================================================================, _/ s) S h0 r/ }4 J2 ~1 y; n9 s
704398 CONCEPT_HDL CORE In Windows mode basic shortcuts do not work when in German language4 {" K' H6 s( w, M& ^
771137 ADW LRM LRM reports 'Injected Mismatch' for a value based on capitalization of ptf value9 k0 g/ q7 V# v* E* r% @) b' u/ c
872547 CONCEPT_HDL CORE Document schematic - Published PDF is missing Bookmarks& h" k1 o7 [! N1 ~
875001 CONSTRAINT_MGR OTHER Click on the Constraint Manager selected net filter icons crash software.# Q! o& E# V& d* g
875039 CONSTRAINT_MGR ANALYSIS RPD margin is not calculated in 16.3
) c+ E4 ?# A* }2 R- Z3 h& P" l876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net9 z% Z* D. w$ ?% s! L8 e
877912 APD DRC_CONSTRAINTS Shape to Shape DRC seems to be behaving inconsistenly above 90 um spacing on mcm database.
. i; q3 b# _$ g5 k& g7 M. n- u878022 CONCEPT_HDL CONSTRAINT_MGR NO_XNET_CONNECTION is not working unless defined on last discrete before receiver T# w( A2 P$ B2 Y/ \
878519 SIG_EXPLORER OTHER View Trace Parameter - stripline trace model display incorrect distance to the reference plane
. _) q( E% v8 D0 I. t* {879529 CAPTURE NETLISTS Misleading bus/pin ERROR [NET0081] message from PSpice netlist; K- R1 g% G' A+ B9 T+ |2 S! T9 ?& L O
881455 ALLEGRO_EDITOR INTERFACES Some Drill Figures missing while Exporting DXF
5 w4 u1 S7 e0 ~6 F881711 ALLEGRO_EDITOR SCHEM_FTB Spacing constraints(Net Class) from schematic are not transferring correctly to the layout
- d. K* A& c% {& y2 }882277 ALLEGRO_EDITOR DRC_CONSTR Get Bogus (false) "Thru Pin to shape spacing" DRC for Oval slotted pads.
# }8 E# T- n7 V ^882408 SCM SCHGEN Export physical fails due to netlisting error with the ASA exported schematic9 k/ w/ W0 u/ P8 t3 ?
882796 APD OTHER GDS stream import results in a set of bumps misplaced... possibly rotated 90 degrees
, t) t0 y- ~6 T, F
F- `5 M3 m2 T0 U* \1 E2 aDATE: 03-25-2011 HOTFIX VERSION: 027
3 g! |& \3 c% Q$ ?===================================================================================================================================; T D+ v& q& t. e
CCRID PRODUCT PRODUCTLEVEL2 TITLE" Q) n: L+ y* X- h. b6 F+ a" X. e
===================================================================================================================================! _% E- N. j( `: O" o7 w# M! z$ X
820901 EMI SETUP Request EMC system.conf file that can be read from CDS_SITE.+ [# x6 T, g# F! b2 F ]/ |
861999 ALLEGRO_EDITOR DRC_CONSTR DRC hang after padeditdb9 D" m! e* v3 f' J' i. Q
862463 CONCEPT_HDL RF_LAYOUT_DRIVEN Rotating and Mirroring RF components in DE-HDL requires RFFLIPMODE property to be correctly updated
O0 X3 A! _7 s1 l6 Y867223 ALLEGRO_EDITOR SHAPE Shape fill disappears when Negative shape is converted to Positive in Cross Section
6 g" h h% [0 j4 z6 Q$ `868733 CONCEPT_HDL ARCHIVER ASA Archiver not saving the entire design./ ~" R6 b( j7 W+ _' d$ ~3 l! z
871548 ALLEGRO_EDITOR MENTOR Shapes missing after mbs2brd translation8 i, N7 F" X, r6 g4 F9 S/ ]/ K3 a6 |
872003 SIG_EXPLORER SIMULATION TDR simulation results were different between 15.7 and 16.3.
3 K8 e* e _+ r& }, @3 @ a872464 CONCEPT_HDL CORE DEHDL script works in SPB16.2 but not in SPB16.36 F# D( `& S2 d* `) w' E
873772 SCM CONSTRAINT_MGR Importing a block results in subblocks coming in without properties8 | k, z& D9 C* C, N; S7 \7 b' R8 L
874335 SPECCTRA ROUTE Route Custom crashes SPECCTRA after routing for some time during "Running Route Phase".
6 _" m2 J6 c# F874989 CAPTURE SCHEMATICS Schematics jumps to another page after a mouse click. W. l0 }8 G$ n7 V
875161 CAPTURE NETLISTS Creating Allegro netlist hangs Capture# Q! Y4 v: y' T- D! f
875411 ALLEGRO_EDITOR NC NC drill produces Error processing extract . Program terminated.
6 s) n1 W& ]5 g% H' Z" H [876004 ALLEGRO_EDITOR SHAPE Unused pad suppression problem in Allegro v16.3 since S020~S024$ d5 R# e# i5 I9 U/ o
876045 ALLEGRO_EDITOR SHAPE Oval hole drills do not void shape with hole shape drc when the regular pad is smaller than hole4 j; T1 P9 F+ ]- ~2 O
876168 SPECCTRA_MENT_ IMPORT option to have a switch to prevent merging of plane layers during mbs2sp$ k- d! V4 {8 t; m
876210 ALLEGRO_EDITOR SHAPE When updating shapes to Smooth the tool will hang.
% K& z" P$ I m$ p: T t8 y876284 ALLEGRO_EDITOR DATABASE Executing SKILL file crashes Allegro8 P: u q, X! L% B' a- v8 Q2 u+ {
877057 ALLEGRO_EDITOR MENTOR Footprints are shifted when importing from boardstation
1 ^" {) @' l( H5 C877549 SIP_LAYOUT WIREBOND Wirebonds not moving correctly when on an Interposer smaller than the die., i1 {# Y; v5 a g7 V
877862 APD WIREBOND APD crashed when add Wirebond without any dump and cannot record script.
( n3 \" y+ V% Q/ x+ u878199 CIS DERIVE_NEW_DB_PA Change in Regional Setting causing problem in derive database
7 k! j4 \' [2 t( b: W: S9 M. t* d- h878216 APD OTHER stream_in - Stream file scan failed
/ R* r& t" i6 ] t% F! i% K878400 APD WIREBOND unable to add a wire bonding on few die pad/ Y4 {3 l4 n: f
/ j; o( Y6 f# I& j) j, G( ?4 H( @0 Z/ bDATE: 03-11-2011 HOTFIX VERSION: 026
$ A5 C: _. p8 @8 r* W7 T2 z8 }===================================================================================================================================1 D" l8 U6 j7 E9 X4 w* }
CCRID PRODUCT PRODUCTLEVEL2 TITLE
) P! k X& [7 y& U2 g===================================================================================================================================! `. l0 A* J( D" W( h- E- W
851882 SCM SCHGEN Multiple issues with the ASA generated schematic in preserve mode while using square bracket0 g1 ^+ f9 C) U0 X8 _, w" N
852063 ALLEGRO_EDITOR EDIT_ETCH What is being displayed in the HUD when a percentage is specified as a tolerance?
+ P9 ]. V% V- V) K. }854502 ALLEGRO_EDITOR DRC_CONSTR DRC not detected until DBDoctor is executed. Status form and sum dwg report are incorrect.! ]6 v4 o( d; p5 K& }) l
856797 EMI RULE_CHECK Arc segments were detected as warning by bypass_plane_split.: A4 U8 S+ E6 B/ l! a" l+ s
859213 PCB_LIBRARIAN CORE $LOCATION size in PDV and DEHDL differ" I/ ~9 Z) P' B' p. g' W
860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser
" R& p& }6 ^; b9 ?5 r862259 SIG_INTEGRITY FIELD_SOLVERS EMS2D run twice during View Topology.2 L9 i* A6 n9 v4 V6 N/ Y! D: l
865158 ALLEGRO_EDITOR SHAPE Shapes are not voided with Dynamic Shape Fill modes with Regions
9 G) ^) h0 \" I6 R! u' f865295 PCB_LIBRARIAN CORE Part Developer crashs with symbols having Japanese notes
( |3 R: u; [: u( j. j866095 PCB_LIBRARIAN EXPORT_OTHER Export DE HDL part to Capture Part Crashed
7 k7 Z4 t" x. v+ g7 i866835 SCM UI User arguments not used over project arguments for new tool
7 x* U; n7 z) t f! S5 `867102 CAPTURE LIBRARY Incorrect pin number gets assigned to pin if a PDF is opened before writng the pin number.* g( ~1 x+ J5 g; T* C i
868092 CAPTURE GEN_BOM Capture BOM in V16.3 is different than that of V16.2 for attached test case.- y7 E* e$ o( C. Q2 ~, B
868517 ALLEGRO_EDITOR ARTWORK A pinhole was made in the artwork file.' m" }' P3 Q- r# j; R
868646 ALLEGRO_EDITOR SCHEM_FTB Change in the PIN_GROUP at the chips level not propagated to the board file does not allow the swap/ j3 ]( t& \8 D8 F @3 E
868844 PCB_LIBRARIAN CORE BUBBLE_GROUP with no value causes problematic symbol: F- X) k- }1 Z5 X
869326 CIS DESIGN_VARIANT View Variant is not showing part as Do Not Stuff4 B8 a$ z$ q! S1 ?. p
869547 ALLEGRO_EDITOR SCHEM_FTB Error while parsing the alternate symbol
! T' [: s. n! E4 E869931 SIG_INTEGRITY OTHER DML Library Management rewrites library longer then 512 characters into multiple lines." J$ p' |) \. D" W) {- J
869960 F2B PACKAGERXL PART_NAME property added to Export Packageable schematic parts
0 a+ O6 S- g, x4 }) |870392 APD EDIT_ETCH Route > Slide not performing as expected in 16.3* k8 }- Q2 k! T. F
870704 ALLEGRO_EDITOR PARTITION 2nd import of parttiotion unplace components in master% o# c& e+ s! D3 s4 u
871177 CAPTURE LIBRARY Keyboard shortcut for closing the Place Part window* g: o5 f& V- C% j! k2 q/ V
871552 PSPICE SIMULATOR Pspice tool crash
* c* Q8 o3 a* u871643 ALLEGRO_EDITOR INTERFACES IDF in batch and GUI for dra files fails to calculate extents correctly5 ~% {# e7 S6 A6 Q; G
871968 ALLEGRO_EDITOR COLOR After using Clear All Nets, Color Dialog box needs to be reopened for adding custom colors.
G. K! f/ }7 X) c; c! J872352 APD WIREBOND Move Guide paths crashed APD.& _5 l% I! E& d2 Q! k% S; T( e
872380 CONCEPT_HDL COMP_BROWSER DEHDL crash when editing the ppt_optionset.dat file from Part Manager.
: S$ u# Z. J( k8 K! s9 u. S9 P872450 APD WIREBOND Wire to die edge angle remains highlighted in red for wire bond status window in v16.3
, F- V6 Q: g* @0 k/ s2 m7 g+ Q1 U2 h' u872787 APD WIREBOND Some Unused Wire profiles be purged but still existing in Bond Wire Profile of Color Visibility?+ z# @! ~1 |- Z% m1 W' {8 l
873217 ALLEGRO_EDITOR TESTPREP Testpoint generation not working correctly1 h5 u, K( y, N* ~" Z; p" v3 Z4 x
873500 APD REPORTS Total Plating value is 0
# ^8 c( S! {% A6 `1 S873505 APD MANUFACTURING fillet size changed when recreate Plating Bar! r% Y7 z O1 G% H
873600 APD OTHER When attempting to Display Pin Names the tool takes a very long time.
9 H* R6 E1 T' E8 S/ @, M- J874341 ALLEGRO_EDITOR OTHER "Gloss>Convert corner to arc" command made an unnecessary circular arc.
0 ? R' {; z6 R' J& x8 q: }0 y+ ` m) g: m
DATE: 02-26-2011 HOTFIX VERSION: 0259 c( H6 B. W/ e
===================================================================================================================================0 m% e0 ]# E( n- E6 w& W# V
CCRID PRODUCT PRODUCTLEVEL2 TITLE
, k* F: `$ S. T n===================================================================================================================================7 u3 g R( s! S6 G# M# t6 `
746063 CIS OTHER CIS Query Does not display initial search results7 v% Z6 H: ?: C; H( n. {
779588 ALLEGRO_EDITOR PLACEMENT Symbol outline not rotated with component.
2 i4 u* s, @6 c1 s! S7 [805616 ALLEGRO_EDITOR ARTWORK Allegro produces warning about database extents exceed film size
3 e: N) w! f3 G9 ]* x$ `* }843145 CONCEPT_HDL CORE Cannot copy grayed out properties in the Attributes form to the buffer6 {3 q$ r" S9 e" A6 k( s* W& \
845607 ALLEGRO_EDITOR EDIT_ETCH Sliding with arc gridless enabled leaves extra segments behind and 45 degree segment.3 D/ L2 v1 ?) Q* a8 n4 t
850428 SIG_EXPLORER SIMULATION SigXP failed to simulate the topology with designlink.
" x) P2 [" b. m7 r853665 SPECCTRA CHECK Scheduling violations reported incorrectly.
! n J6 |* s6 M! ?. v; D+ B2 p855534 CONSTRAINT_MGR OTHER formula result does not update when length changed
, d( D. {' }9 E; c# j% `855793 CONCEPT_HDL CORE Rename Pin on Block is not working in DE HDL with HF 21
! s- P2 L# Q" E% t# s856306 ALLEGRO_EDITOR INTERACTIV Modifying pad instance corrupts db
6 @+ H( Z7 q2 X3 r3 Q* G9 }859437 SIG_INTEGRITY GUI Log Scale setting of EMS2D was cleared by re-open design.( E3 D) q! Q" q
859850 SIG_INTEGRITY GEOMETRY_EXTRACT Allegro freeze during topology extraction with EMS2D.
' {- r6 D. u6 B9 l# j860366 CAPTURE CONNECTIVITY Netlist is different in V16.3 than in V16.2! u D0 A6 w- ^/ o
860809 F2B BOM Bomhdl failed to create the design view check for existance of the packaged directory5 D5 g+ [: z' H. G$ Q
861027 CONSTRAINT_MGR CONCEPT_HDL Unable to synchronize the constraints0 A& T8 c( k$ l+ \( V/ H
862137 SIP_LAYOUT OTHER SPB 16.3 SiP Logic - Derive assignment is unable to resolve connectivity of shapes
" u7 ?0 o2 v0 I: f. h7 S) {; s' A862980 ALLEGRO_EDITOR EDIT_ETCH When sliding a via the potential DRC behaviour is inconsistent.& D3 G6 _+ O3 Q% S. {3 a
863400 SPIF OTHER SPIF does not translate the oblong pads correctly
. }! ^. l. S. _* \ l864363 APD REPORTS The Wirebond report is failing because there are Non-standard Bond wires present.% N; [/ D, t, F5 s! y
864621 ALLEGRO_EDITOR DATABASE Database corrupted after adding layers in Cross Section and trying to save the board file.
a, h' M1 ?, K7 w' a865875 ALLEGRO_EDITOR MENTOR mbs2brd translator results in broken/unrouted nets even though the BoardStation design is fully routed
# s% O; C. f) H866202 CONSTRAINT_MGR OTHER Worksheet File import fails with error message due to character limit) A7 z. w# j1 j! U0 |% o& M2 Z0 K( U
866726 CONCEPT_HDL CREFER TOC (table of content) not generated in schcref_1 schematic (CREFER flattened output).2 d4 l5 l' u, |, M
867238 CONSTRAINT_MGR INTERACTIV Split Xnet for diff pair crashes PCB editor
, @. I7 N- M( w0 o867696 SIP_LAYOUT DIE_STACK_EDITOR When doing an Info on this design it will crash.1 p& y) f: _& ^" D* o6 D
867742 ALLEGRO_EDITOR DATABASE Thermal Pad view for shapefillet on Negative layer% v' C+ |0 T8 c: n' f! `" k
867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location": ^; _$ r$ q! K! Q/ E6 d# c; s
868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets
! B+ A6 p# m# g1 K5 o) G869758 CAPTURE GENERATE_PART Generate Part option "Copy schematic to library" does not copy schematic page attributes
3 V6 y0 Y1 H$ l) D( E9 [' ]9 A) r869941 ALLEGRO_EDITOR PADS_IN PADS_IN unable to import Power PCB 2005.0 file in 16.3 but works with 16.24 ^! P3 v2 O( ~
870301 SIP_LAYOUT SHOW_ELEM When selecting Info and then a rectangle shape, the tool will crash.+ k" ^4 `! g4 g* m' ^. U# N! u
, W+ n) d: Q3 f0 c. h; y
DATE: 02-11-2011 HOTFIX VERSION: 024
! [3 ~" {0 D" u4 S5 f6 [) J===================================================================================================================================
* o9 _) U+ P+ `+ a8 @6 tCCRID PRODUCT PRODUCTLEVEL2 TITLE6 D0 P1 b% f8 `
===================================================================================================================================& i! M2 J) ^- `+ _0 A) i
858051 ALLEGRO_EDITOR OTHER Allegro's Help>About... System Info... doesn't work on Win7
. i. c4 X; K- e8 E8 s; A( Q862703 ALLEGRO_EDITOR DATABASE crash when doing a save_as
) t# E' _0 d) b3 t: j866288 ALLEGRO_EDITOR NC Drill customization table won’t let you add characters in lower case
* m: \3 j. ?: L4 x- `866310 ALLEGRO_EDITOR DRC_CONSTR Testprep doesn't create a DRC for Testpoint > Component$ i' {+ |) [# U6 g# {
866652 ALLEGRO_EDITOR SCHEM_FTB Allegro Spacing net class not updated with new logic
- E: Z( e2 G& P* P% T$ i
, V! G: \/ x2 H0 A9 [! K+ nDATE: 01-28-2011 HOTFIX VERSION: 023
% N8 q# X( `0 ^8 }- Z* Y' B# s& A===================================================================================================================================. F3 w9 s% K- w) m! V: |: V
CCRID PRODUCT PRODUCTLEVEL2 TITLE F7 N6 }' N: ^) c: Y
===================================================================================================================================% c6 L) P5 e ]- M6 H5 t
739067 SIG_INTEGRITY SIMULATION about modal delay of diff pair net
3 u% N; j6 \% L& f' B6 V! A) O) i: _742237 CIS FOOTPRINT_VIEW 3D Footprint view in CIS Explorer
+ j" J5 b, m5 @$ q* t6 }762702 CONCEPT_HDL CORE Unable to change color settings, y' Z) n L, l8 Q
800333 CONCEPT_HDL CORE Text change cursor not working on Solaris and Linux: X% {9 @2 r& e2 [
837479 CONSTRAINT_MGR DATABASE Import dcf with custom column cuases a problem# s2 j* R, g, A3 G9 @# A
846679 ALLEGRO_EDITOR SHAPE Through Pin can not be voided correctly in dynamic shape.
/ r$ ~7 S1 w3 c7 H; ^852255 CONCEPT_HDL COMP_BROWSER DEHDL crashes when adding part from cat file
& P. o) O' A) j" Y5 u: M* t855553 ALLEGRO_EDITOR DRC_CONSTR Multithreaded DRC shows different DRC counts
5 ?7 Y0 V+ u. q9 M, ^! j856459 SIG_INTEGRITY GEOMETRY_EXTRACT No waveform was output if users set the Via type to Analytical type# X* d4 N: D* H
857030 SIG_INTEGRITY OTHER Inconsistency when signal model has "legal" spaces within it.
6 {6 f# O- D* Z/ \7 O857120 APD WIREBOND Enhancement for Redistribute Fingers./ u# c4 Q3 @# y a% S' @
857165 SIG_INTEGRITY OTHER Model Name Changed Warning appears every time after Export Physical% Q: V8 h$ z& a7 f) H
857237 ALLEGRO_EDITOR SCHEM_FTB UserDefined mapping mode
# l5 M1 `9 Z) U5 }857650 ALLEGRO_EDITOR DRC_CONSTR Hole to line DRC unavailable on inner layers for mechanical pin with no regular pad definition.6 ?+ v; f9 x6 ~ C3 U# ]! C
858046 MODEL_INTEGRIT TRANSLATION Ibis2signoise fails translation when the unit of Pin section is "ohms".2 U% f. d5 @1 o& t/ u3 ?( R
858154 GRE DETAIL Net not following the plan during Plan Topological
l% e5 l9 T/ E4 A& b [/ K858192 SIP_LAYOUT SHAPE Program crashes when attempting to add polygon shape.- G; Y7 w! R5 G3 N" t
858307 CIS DESIGN_VARIANT Homogenous part not showing correct DNI on schematic
4 v1 E! `7 F0 a858624 ALLEGRO_EDITOR PAD_EDITOR "Save Padstack to 16.2" command is needed in 16.3 pad_designer.
4 O! p! N, m1 ^( p+ v1 g7 V858814 ALLEGRO_EDITOR MODULES place module not placing figures present in mdd
. p( V- p! |, D9 i* F859514 APD IMPORT_DATA Die Text-in cannot change unnamed Begin Layer to selected pad layer in step 45 s) n2 }; S) ?) G: R8 G' |' z0 [
859640 ALLEGRO_EDITOR PLOTTING Shape based pads not output as polygon in IPF
1 [ z/ {" E) z, i) @& h859680 ALLEGRO_EDITOR DRC_CONSTR Multithreaded DRC shows different DRC counts9 L6 U' M& L: C! p
860069 ALLEGRO_EDITOR OTHER Import Logic hangs then crashes and displays Netrev warnings.( y7 q0 ?8 g1 a
860535 APD DXF_IF a2dxf got an error message+ C' ?* y1 G4 _6 ]! s* a
860860 CONCEPT_HDL COMP_BROWSER Component Browser freezes
5 X2 c, F# K6 B* I6 W2 Z5 `861295 CONSTRAINT_MGR ECS_APPLY Diff pair PCSet value overrides ECSet values in constraint manager spreadsheet." f# I! G/ g9 C& z; u8 Z
862279 SPIF OTHER running 'Allegro PCB Router' Crashes
2 m& W: w# \- X _ v+ u2 o
3 S% Q% `0 k( @$ a0 gDATE: 01-14-2011 HOTFIX VERSION: 022- h4 E3 j- u9 w L4 U$ F; V
===================================================================================================================================& L, s- N5 ^' [; e7 l( w
CCRID PRODUCT PRODUCTLEVEL2 TITLE
6 _5 O2 P2 {$ l, m! z3 Y8 o===================================================================================================================================% {' U, i I) o- ~( Q! ?
372240 CAPTURE SCHEMATIC_EDITOR Allow component move with connectivity change should be checked by default
4 M+ u, d2 ]0 s769139 SIP_LAYOUT DRC_CONSTRAINTS Wire to Bond finger rule in the CM needs profile to profile constraint capability4 u/ y% C- Q5 a: n9 N7 l* s; I" s: @
772299 ALLEGRO_EDITOR GRAPHICS Via doesn't get highlighted properly with OpenGL disabled
7 E% q$ l. n `0 ?830519 ALLEGRO_EDITOR GRAPHICS Disabling openGL causes highlihting problems.8 C' o5 j% u2 n; n* B
833981 RF_PCB FE_IFF_IMPORT DE HDL Import IFF unit conversion and unit display in RF schematic. Z# Y8 c& D7 M, z6 G
835698 RF_PCB FE_IFF_IMPORT DE HDL Import IFF to assign simple sig_names like RF001 RF002 etc$ M3 Y! r* O6 [7 Q. Y
840094 RF_PCB OTHER dlibx2iff does not translate complex polygon pad! x) C1 ?! t2 L$ B6 L
844504 SIG_EXPLORER INTERACTIV EMI Regulation setting of the board is not reflected correctly when the net is extracted into SigXP; e4 u$ ]4 O: K2 i3 b& p" P1 \4 [% \
846210 PDN_ANALYSIS PCB_STATICIRDROP IR Drop mesh is not correct.( F1 r1 p. v ?8 P& n% q) r5 a
846228 SIG_INTEGRITY OTHER ZAll and Wirebond calculation in the Prop Delay formula
- G/ y; x( n i5 B( _* o846259 CONSTRAINT_MGR CONCEPT_HDL Why dont I see the P1_8V_DIG net in CM ?: o0 E, K$ v& Z
847278 CAPTURE TCL_INTERFACE TCL/TK PDF Export Change Page Size
& b# n* L; J6 a: K8 U7 t9 p* v847942 SIG_EXPLORER OTHER The solder resist layer was not included in Interconnect Model of SigXP. {, ?0 k$ D) y5 z
848181 PSPICE DEHDL Model association for concept symbols with a chips view doesnt work6 r" t9 x8 ~$ D$ M# s C4 B
849707 ALLEGRO_EDITOR MANUFACT Thieving creates unwanted thermal reliefs in this design.
$ D2 T: I! X+ l: E7 m m& w( p851070 CONSTRAINT_MGR CONCEPT_HDL The Match Groups are not visible in the CM% L: u, a, k: n ]
851171 F2B PACKAGERXL Design will not package with exclude_cdsNotOnSym
+ L& w3 E( R9 N6 s- y c2 M& [1 `4 H851290 APD PADSTACK_EDITOR APD/SiP crashes when the user defined mask layer is edited with padeditdb.5 P2 |% P; V- z3 |+ _
851477 SPECCTRA ROUTE Allegro Router runs out of memory during route passes
' _3 h8 a- i O; h2 q) f851658 APD EDIT_ETCH bunceback behavior while slideing cline' P. V1 l" {/ _/ z. E2 X2 C
851725 ALLEGRO_EDITOR DATABASE Number of DRC is not consistent on each DRC update.$ B9 |3 T# h# J; m- E% c
851789 ALLEGRO_EDITOR SKILL Skill axlAirGap for Via & Text causes Allegro to crash
1 l4 e4 T% I% ?7 {* }- E+ p852325 ALLEGRO_EDITOR DATABASE Perf advisor doesn't check high pincount devices for RATSNEST_SCHEDULE
( v% p; G$ V2 B7 W; ]6 i852360 SIG_INTEGRITY OTHER Appling toplogy template to a diff pair object reports UserDefined in CM
2 w4 o9 Q, C- g' \+ ^. a0 A* S852395 ALLEGRO_EDITOR DRC_CONSTR Same net via spacing broken drc shows up to date
9 I/ F7 |* m7 \. U, p2 _( p852764 ALLEGRO_EDITOR SKILL axlHttp beeps and gives error E - http 42+ S% s5 ~1 u+ y5 s
852787 CAPTURE ANNOTATE Tool is crashing during annotation if Ref Control is set8 x2 C, B+ [5 \3 c! E
853110 ALLEGRO_EDITOR ARTWORK Allegro Crash on selecting Mfg > Artwork if any Parameter syntax is wrong in art_param.txt
. I' f/ h4 |4 o854031 ALLEGRO_EDITOR MANUFACT The stream out data xxx.scf seems to be incorrect.3 i2 x; ?7 h6 a. P% C! b' {
854246 ALLEGRO_EDITOR MANUFACT Stream out data of Oblong pad is strange.
8 _; |( t, C8 J7 N! Z854293 APD OTHER dynamic fillets were disappeared when open in 16.3.+ ]. @6 D( V* ]# |, `7 ?; k, w+ a
854356 ALLEGRO_EDITOR OTHER Fillet adding doesn’t check same net spacing rule in both static and dynamic mode.4 K; Q+ D% j/ ~7 j
855101 ALLEGRO_EDITOR OTHER Drill figures now smaller than expected
+ }) K) m: Q6 J$ u" I/ _855124 APD PLOTTING The "load plot" command did not import Drill symbols(Figure) and Characters in APD.
2 D7 v" M9 Y: O. W0 u855348 ALLEGRO_EDITOR EDIT_ETCH Differential Pairs do not slide to correct geometry7 L' Q9 u; G: K3 @. ?" e$ m6 y3 y
856220 ALLEGRO_EDITOR INTERFACES Export DXF in the 16.3 S021 build rotates some pin locations- e+ f% W$ ?; y, ~' W4 M
856256 SIP_LAYOUT WIREBOND When editing a single Wirebond all wirebonds attached to the finger get highlighted.0 x O2 }2 j6 @( f7 {
856674 ALLEGRO_EDITOR AUTOVOID drill hole to shape autovoiding clearence is wrong for Same Net Spacing: x9 Y6 B) b) _9 M3 w3 Z1 T% p
% t% B9 @$ `7 d" V- YDATE: 12-10-2010 HOTFIX VERSION: 021
T+ `$ T9 p7 T5 y& D! H) V! p7 E===================================================================================================================================
% `4 _+ v# z: Z4 xCCRID PRODUCT PRODUCTLEVEL2 TITLE) V& o. E( }1 o. C! N( \2 s
===================================================================================================================================% {5 _* k$ ^. z( s. ~
708992 ALLEGRO_EDITOR SCHEM_FTB Design Differences fails with Error #534 z& z$ [, x9 s1 h& @* G
748982 CIS FOOTPRINT_VIEW Respective pin number from schematic does not get highlighted on 3-D footprint viewer.
% `! ?( }: }0 a) `3 [$ {5 X& E; [775788 CONCEPT_HDL COMP_BROWSER Component Browser search is too slow) o+ F/ R& {+ K. y# i
802152 PCB_LIBRARIAN IMPORT_EXPORT cap2cond design translator is also looking for Capture feature string in license - this is break from 16.2
$ X1 O9 V6 H6 E% u803910 ALLEGRO_EDITOR GRAPHICS Request Rat like display for REFDES text to component.3 A& W& L! @& R1 }
823599 SCM REPORTS Ability to generate DEHDL style BOM report7 Q8 O! h5 n* U. k$ B' n
826558 CONCEPT_HDL LWB-HDL Module definitions for cells is not included in the simulation verilog netlsit on LINUX% p$ v/ l2 T6 z: s3 u) {2 p. [
828689 CONSTRAINT_MGR OTHER formula constraint lost when Constraint Manager closed1 p j$ s2 a! X& Q6 d" o
831192 SIG_INTEGRITY GUI Cannot close Analysis Preferences window.
& s% [! \1 S0 P; T- [* m+ o) \$ @831229 ALLEGRO_EDITOR INTERACTIV When mirroring sym PLACE_BOUND shape does not mirror til placed
# y) M' P1 b* o832315 ALLEGRO_EDITOR SCHEM_FTB ECO.txt file should not list net names if schematic and board files are synchronized.
x7 i. b a& w" u5 f832644 ALLEGRO_EDITOR DRC_CONSTR DRC error disappears when the size of Constraint region is changed.
4 V( x* S/ k4 T+ m1 k833061 MODEL_INTEGRIT TRANSLATION Model Integrity IBIS2DML fails to convert data correctly for pre-emphasis using Driver Schedule
: k5 R% ~& T7 k }6 N- J: F9 u7 R833487 SIG_INTEGRITY GEOMETRY_EXTRACT Probe sim failed if VARIANT_TO_IGNORE was set.
8 U7 j# J2 W! v2 B4 w3 j" M- S833922 CONCEPT_HDL CORE Move pin on blocksymbol using Block -> Move Pin command change the Pinname textsize) }1 @ h5 _+ c7 k& x8 Z+ x6 @; `
834103 ALLEGRO_EDITOR DRC_CONSTR dynamic diff phase highlight not showing* |9 F# R% n4 T+ X: n. t+ n
834868 SIG_EXPLORER OTHER View Trace Param crash if sweep param was set for loss tangent.
- d% J; y4 v0 t! U835006 CONCEPT_HDL OTHER Locked BACKGROUND directive is changed in DEHDL session
: G* n' n; `3 M5 ~# \835326 APD SPECCTRA_IF Specctra does not open from APD using Allegro Package Designer XL (Legacy) license C! K2 l. G5 }9 P; U( J
835622 CONCEPT_HDL CORE DE-HDL crashes when selecting wire having global sig_name in opened block schematic
5 s: v# V# ~: x8 C& O1 p8 g836962 CONSTRAINT_MGR ANALYSIS Simulation will crash0 U* m; X {" b& r
837216 CONSTRAINT_MGR OTHER Custom measurement Rslt lines being duplicated in a different worksheet.' j" q# i9 d: [
837322 CAPTURE LIBRARY Library is not getting freed even when user has closed it.9 |7 W, V2 q7 \+ |! A# Y
839517 CAPTURE MACRO Macros (for place part) created on 16.2 version works differently on 16.3* ?8 n2 _& t7 T8 M, r
839749 ALLEGRO_EDITOR MANUFACT Drill entries are repeated in .drl files: P e* {/ \! V. p7 Q
840738 ALLEGRO_EDITOR ARTWORK Shape symbol in padstack moves when Artwork is generated - Break again after fix in 16.0
* y2 T0 N( N9 `7 g841176 CAPTURE ANNOTATE Homogenous parts are not getting packaged correctly in annotation in 16.3
$ `; p, d5 D1 y y% F; G0 `# {/ i841355 SIG_EXPLORER OTHER Trace model parameter does not update when linear Range are entered.
3 G6 Z/ I2 V: A+ Z" Q841730 CONSTRAINT_MGR OTHER Allegro Crashes while working with MGs in CM
$ [5 L& p4 N& t' h: P D4 C841759 F2B BOM BOM creates an incomplete output when design packages without errors
) |& ^& @) `6 K* g. z# E841928 CONCEPT_HDL CHECKPLUS CheckPlus fails when pin name contains _N in the middle of the pin name' q, \+ Z" Z8 t* C' s, D
841991 ALLEGRO_EDITOR PLOTTING Offset of text and line on importing a plt file
* r& t& p# {+ E# y842204 ALLEGRO_EDITOR DRC_CONSTR Arc creates false DRC on edge of Constraint Area: U; C' C2 \ w# A
843114 SPECCTRA ROUTE Specctra rules file taking very long time to load
" s0 r- I; g+ F: S843254 CONCEPT_HDL CONSTRAINT_MGR Unable to invoke CM from DEHDL CM Crashes with an error Olecs.exe The application has quite unexpectedly
/ H7 U5 W! B) l) @1 X843518 F2B DESIGNVARI Variant with FAIL_OPEN
0 {1 j8 g1 u& e$ d, e2 o7 N843933 ALLEGRO_EDITOR DRC_CONSTR Cancelling drcupdate will either hang or crash Allegro
2 y* N7 W: T, y/ l( R& V9 J844074 APD SPECCTRA_IF Export Router fails with memory errors.
: ^; n+ b, N- \% f6 C* Y1 m2 c' b844246 ALLEGRO_EDITOR SHAPE Long Thermal_Relief connecting to XHatch shape4 M3 {, ]2 \, n! l" P+ O3 o
844355 CONCEPT_HDL COMP_BROWSER User seeing CDS_NA appear when placing component$ B2 z8 U5 _8 u% Q8 H
844381 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin - Pin is connected to net <netname> not reconnected.7 [5 N7 ^& t' F9 e
844662 SIG_INTEGRITY OTHER Cannot uncheck options in analysis preferences.
4 V* l' F' m7 D# ^( X' v* k U844796 SIG_INTEGRITY OTHER Get an error E- Illegal model name. Cannot add model RE_RES_0402-16570580,when doing Auto Setup during Model assignment
4 q( y, o, q1 L! [( l846172 APD OTHER Cannot generate the dxf file from this database
* i* f V- `& R6 I6 l3 k846270 SPECCTRA GUI SIGNAL_15 layer missing from the color pallete in Specctra! [. x" `- u+ h
846352 ALLEGRO_EDITOR DRC_CONSTR Route connect does not select the pin-pair width for routing.
+ T. g5 m6 Q8 p' k% W846420 F2B DESIGNSYNC Design Sync failes due to FUNC_VIEW_FILE missing messages
! t% C. w1 L Q846918 ALLEGRO_EDITOR PADS_IN Pads_in crashes when importing ASCII file, Runtime Error* M8 ?; }7 T' v7 w* I
847079 ALLEGRO_EDITOR DATABASE Allegro Crash while trying to unlock the board file/ v+ p! m2 Q6 l' ]/ I8 D; ^) v8 Y; q
848143 F2B DDBPI Adding part crashes DEHDL
! J2 ?; r8 A/ l) x2 B s0 w848415 CAPTURE STABILITY Crash on Mirror Horizontally
B: f) j3 T7 I/ J2 Z. N& X
0 |8 N7 Y- h5 l& X2 NDATE: 11-11-2010 HOTFIX VERSION: 0206 K: P: t6 S0 h0 Y* y% d# c
===================================================================================================================================
$ C1 o) O$ d& BCCRID PRODUCT PRODUCTLEVEL2 TITLE L- E9 ?! m- S( E* j
===================================================================================================================================: j- q4 t3 [( }" r" f8 L7 W
501606 CAPTURE OTHER Descend Hierachy does not open first page
6 h9 ?- q* @2 l. S764482 SPECCTRA CHECK Allegro router same net checking different then PCB Editor.
1 y! e9 K( _+ _. A" E809055 APD EDIT_ETCH Shove Preferred changes trace widths of shoved traces during routing
6 h" H8 A% A5 ]$ W# I$ U0 i$ N A: |816920 ALLEGRO_EDITOR PLACEMENT Update symbols causing Allegro to crash0 q$ g# O# ^. L+ L# l0 L2 v& S
826762 SIG_EXPLORER OTHER The rotation of element are different between pre 16.2 and 16.3." _8 A' M; p/ O
827769 CIS FOOTPRINT_VIEW 3D footrpint viewer doesn't shows circular geometry on footprints7 l8 _: {. q0 e3 g% L0 M
828830 F2B DDBPI LRM does not update Parts which have a ALT_SYMBOLS value Added1 ?2 e; l d0 B, m- I) @
830319 SIG_INTEGRITY SIGWAVE Sigwave load errors out with "Requested resource was not available" after large bus simulation
9 V( o# A Y1 l1 Y830359 CAPTURE GENERAL Crash on link Database Part5 x) V" ?* g X* r0 a7 K( r
830627 ALLEGRO_EDITOR DRC_CONSTR Incorrect thru pin to shape SPACING error
8 o! T4 D0 x0 [0 P7 ?. H; z3 O830716 CAPTURE PRINT/PLOT/OUTPU Capture crashes while printing a Capture CIS Standard BoM with ISR s0017.
# F# D* l+ M& w: g9 S+ l830791 SIP_LAYOUT LEFDEF_IF Improve the LEF Library Manager to import passivation layers
8 P$ U! U/ _, ~: K831210 CAPTURE OTHER Users get an error message everytime While running Update Cache with V16.3 and V16.2 with latest ISR3 C/ d# i0 J% ]# W8 C7 M* p
831231 PSPICE SCHEMATICS pspice com wrapper error
7 t' R4 F/ Q: ]2 l/ X" H831692 ALLEGRO_EDITOR PLACEMENT Application becomes sluggish to nonresponsive when trying to place mechanical symbol. d+ t* s$ U4 g% i2 b
831704 CONCEPT_HDL CORE ASA stuck in an error condition.$ P# |+ ?' Z3 } o- y
833116 PCB_LIBRARIAN IMPORT_EXPORT Getting LMF-02018 Error while Importing Capture Parts
6 s" y( N9 e1 p/ e833433 ALLEGRO_EDITOR TECHFILE techfile in/out round-off a value of Conductivity(Xsection).7 P# [/ ~, p9 y0 m5 B- Z
833921 ALLEGRO_EDITOR ARTWORK Gerber filled lines stick out from filled area on Fillets
8 h) m( ^. e7 U3 r+ }! m. J0 w833950 ALLEGRO_EDITOR ARTWORK Artwork process create recrementitious circle for AutoSilk data.& I( T% L& K. ^- i
833975 SIP_LAYOUT DATABASE pad not on subclass
1 b; ~8 e/ d& `8 _& l834152 APD EDIT_ETCH Route Slide of a Diff_pair section moves all of the cline instead of just the segment that you want.
0 K/ x4 {0 `' W6 p9 B9 ?- O* W' Z834861 APD OTHER package integrity runs for hours. results in no more room in database0 ~) W3 e: {+ S4 f
835367 CONCEPT_HDL SECTION Packager-XL reverses the pin numbers of connectors' U' p) |' i5 s3 U8 [
837805 ALLEGRO_EDITOR EDIT_ETCH Add Connect crashes Allegro when routing from a cline (not on a net) through a region.
' r/ R: R& b* g4 @ N* q838057 CONCEPT_HDL CHECKPLUS CheckPlus crashes with long parameter.
. j1 R/ m9 i; x) L$ z& h; K838356 SPIF OTHER File > Export > Router Crashes Allegro and dsn file creation stops
; H3 L3 e& h2 O; A838521 APD MANUFACTURING When creating pbar some clines are gone.1 E7 |$ a3 g8 U3 i
838766 ALLEGRO_EDITOR EDIT_ETCH Sliding with arcs making sharp corners instead of arcs.7 y% o# S) G& L& T
838830 SIP_LAYOUT ASSY_RULE_CHECK Assembly rule check flagging a DRC for item not near edge border" d2 v" Q o: _# h3 [. Q
838836 ALLEGRO_EDITOR SKILL Pb to check license with skill core function
$ S7 X' j, i6 I' X, N839218 APD 3D_VIEWER 3D view of this mcm file is not getting rendered and the 3D GUI screen shows up blank in APD% G- \$ U6 F7 c9 o8 {$ u: s# M5 M; T# \
839362 ALLEGRO_EDITOR EDIT_ETCH trying to slide a bbVia crashes Allegro
- b: x, G: v$ w& H V6 S6 F6 a: H839984 ALLEGRO_EDITOR ARTWORK Some pinholes were made in the artwork file.4 w# r0 h+ R/ ] [0 y; n% f: R
840016 CONSTRAINT_MGR INTERACTIV Cannot manually create pin pair for unspec pins of Xnet. u8 I" E2 W9 S4 |% ~
840455 ALLEGRO_EDITOR INTERFACES IDF exported/imported from symbol have no drill information for pad.0 d1 g8 n7 V1 r- z1 t
841431 CAPTURE NETLIST_ALLEGRO Upgrading from Capture V16.2 to V16.3 some nets get shorted on the schematic page.
6 \& b4 N5 `, Q( a3 p1 a0 H
' W4 b, j3 E e& Y; C/ s0 BDATE: 10-20-2010 HOTFIX VERSION: 019
' c# W. N4 c( c0 P" h5 G) S& _===================================================================================================================================/ z7 D* d5 r* k9 u L# G
CCRID PRODUCT PRODUCTLEVEL2 TITLE7 D& i6 E1 X6 {% f: ]
===================================================================================================================================
- {/ h$ i; Q- I5 ?: M717365 SCM SCHGEN Option for Schematic Block to have the defined Sheet symbol/Page Border
6 ~% L/ `$ t7 U: f' Y: _+ N3 a751477 ADW COMPONENT_BROWSE UCB in DB mode does not read local worklib for block symbols3 `# r3 O/ n- O' F. O
792545 APD PADSTACK_EDITOR Can not rename user defined Mask Layer in APD/SiP.: G. m7 d3 `8 q. h
813436 SCM OTHER Option to have a directive in the cpm file to distinguish an SCM project from a DE HDL Project
% b, d, N3 f( r- G/ I% [820640 SIG_EXPLORER OTHER SigXP Crash after doing Transform For Constraint Manager* ^- L! R9 P2 `& X/ L
824527 CAPTURE PRINT/PLOT/OUTPU Part ref-des resets when trying to take variant print from Part Manager$ E9 L* D* b4 ?1 Z0 m2 p/ p) W* A3 B
824688 SIG_INTEGRITY GEOMETRY_EXTRACT PCB-SI crashes when running more than 2 simulations" Z6 }1 T! C, J" Q: a3 e. ~
826571 CONSTRAINT_MGR OTHER Import of .dcf crashes in 16.2 but not 16.3
V9 n, C3 N$ `8 \826626 CONSTRAINT_MGR OTHER Creating a Netclass from a custom worksheet breaks the Netclass object upon the next invocation of Constraint Manager.
4 q- r/ G1 e1 z3 I, n7 p+ q826799 SIG_EXPLORER SETUP_ADV can not close Analysis Preferences form when Advanced Setting button is opened and closed once1 }$ }; k# J$ x' j
827375 ALLEGRO_EDITOR DATABASE Need to check why Net class assigned on the Net are not visible in CM
- K! e$ j) `4 V2 W+ E827521 CONSTRAINT_MGR OTHER Allegro crashes when trying to open Constraint Manager.
2 t; o, z0 n+ q9 q8 N% q; A827713 SIG_EXPLORER INTERACTIV Cannot move object by click and drag after RMB>Note.
4 W4 ^' a: Q( N! l' e- _" D828803 CIS UPDATE_PART_STAT Crash on update part status from Part Manager- c( `" |6 x5 W& C: X+ M/ r
829005 SIG_INTEGRITY FIELD_SOLVERS SigXP crash when RMB click on the Trace Model with EMS2D.4 ^' Q. m: m( i1 ?7 m7 h9 }
829008 SIG_INTEGRITY FIELD_SOLVERS SigXP crash when RMB click on the Trace Model with BEM2D.$ e6 |; g3 o _8 p; T$ P
829233 CONSTRAINT_MGR UI_FORMS Physical Csets applied on a diffpair is not followed while routing, though visible in CM.3 k5 r; f" ?* x$ Z: d: C0 w
829340 CAPTURE LIBRARY_EDITOR propertries are shifting after being placed
& N# I0 f4 }# S$ [829747 SIP_LAYOUT DIE_EDITOR Move pin incremental coordinate
2 Z# s" V9 j+ b9 |4 J829991 SIP_LAYOUT OTHER The "axlAddAutoAssignNetAlgorithm" function is missing from the Allegro SKILL documentation.
' `7 ^( v" U5 R! f; C/ x830509 APD ARTWORK The measured airgap aren't between features in the design aren't consistent in Import > Artwork.
0 h1 c; a9 S" R830809 ALLEGRO_EDITOR TESTPREP In the testprep report the Pin type is getting appended with net name7 i+ o. h! u5 k. i
830907 SIP_LAYOUT DIE_GENERATOR SiP will crash when adding a Standard DIE using the Die Generator.% r2 E! d) h# q% s
831176 ALLEGRO_EDITOR MANUFACT Testprep Resequence crashes this design.
) C4 T4 g7 d, R8 W- n831199 SIG_EXPLORER OTHER error in _sxUtilGetAllegroPart message was displayed.
1 U) m+ d( c- x. O9 y2 E4 J831610 ALLEGRO_EDITOR EDIT_ETCH Sliding with Diagonal Entry (45 Degree) is sliding the the adjacent vertical segment when Constraint region is present
. {% b W7 {0 l2 s" {831946 ALLEGRO_EDITOR OTHER Cannot re-open Command Browser if it was closed by Undo.. a! P: |( g( @, u7 i" m
831998 ALLEGRO_EDITOR SHAPE Allegro crash when user execute shape vertex add command.
. `% t9 W9 ]4 n9 _; t832059 APD SHAPE Shape does not keep Shape-Via(w/ Fillet) spacing.
+ L) }: s* b8 e! j# l9 E832169 ALLEGRO_EDITOR EDIT_ETCH Sliding with Diagonal Entry (45 Degree) is sliding the the adjacent vertical segment when Constraint region is present( J7 M- J3 }! M- m
832197 ALLEGRO_EDITOR EDIT_ETCH Sliding diffpair slides adjacent segment
) l9 m+ w) d/ }& ~ T% Z0 S832613 ALLEGRO_EDITOR EDIT_ETCH Adding microvia and bbvia crashes allegro at location where overlapping shapes exist on other layer
) G0 N& Y8 W" l5 ^: l832922 ALLEGRO_EDITOR PARTITION Import partition board crashes Allegro.7 e2 ?( B3 i3 B: @+ C I6 v$ b
833127 ALLEGRO_EDITOR SYMBOL With 'unused pads suppression' the padstack (clearance) does not get rotated in the internal layer/ g; E) V3 r* d9 a
833251 ALLEGRO_EDITOR SCHEM_FTB Power planes on Layer E3 and E18 change to dummy net after Refresh Module.+ g5 x' I( e3 j# T
833586 ALLEGRO_EDITOR PLACEMENT Allegro crashes while placing jumper2 |$ _' C% m) ~7 q/ u
. J- M( \0 x# JDATE: 10-7-2010 HOTFIX VERSION: 018! w* U1 T* [! r3 u$ _4 M4 g
===================================================================================================================================% ^/ u; f. L! h
CCRID PRODUCT PRODUCTLEVEL2 TITLE
$ v8 K' s8 t0 Y& O8 U1 n===================================================================================================================================- @$ @$ c, b! E# h
398114 ALLEGRO_EDITOR INTERACTIV Need to differentiate between tracks and shapes on an etch layer.; D9 ^* {. v' w7 s; r
530659 ALLEGRO_EDITOR UI_FORMS Allegro Place Manually and Update Symbols GUI missing checkboxes on Windows Vista
- \ w0 F. \% A3 u3 Q770576 ALLEGRO_EDITOR INTERACTIV Design Partition - Place replication not working correctly
0 u5 ? z) q k1 [777925 CAPTURE OTHER Capture crash immediately after invoking
8 J7 ]2 ~# P9 H c807089 FLOORPLANNER INTERACTIV Logic > Net Logic hangs tool in Linux6 a4 r* z9 V9 \7 s! s5 O+ z
809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs
' h) K+ ^& }9 t, b812046 CAPTURE NETLIST_ALLEGRO Design not getting netlisted in V16.3 due to illegal characters in pin nmaes
. o: I1 a+ C4 l' n6 i814607 SIP_LAYOUT IO_PLANNER update genfeed to add options to dumbp all chips files from design$ ^0 N6 l& ^; h) m
814750 ALLEGRO_EDITOR DRC_CONSTR BBvia and Microvia overlap DRC issue0 T( o* e) _; [8 [$ P3 [
815621 SCM OTHER Enhance time shown in session log to support DST* V W% M/ e7 _% ?* b% _
815681 CONCEPT_HDL CORE The TOC symbol shows multiple entries for the pages
$ ~6 L( M8 Q& j6 z+ }817380 ALLEGRO_EDITOR DRC_CONSTR Incorrect or bogus line to line DRC errors are appearing between the nets of a diffpair( |1 [6 w$ F8 T
817881 APD ETCH_BACK Create Etch Back Mask failed
% s: K% ?7 {- |, U- ]+ M820771 ALLEGRO_EDITOR PLOTTING axlLayerPrioritySet does not provide the same capability than the 15.7 Color Priority system
4 S+ z2 c0 ^' h0 b, y6 K2 ?: n820773 ALLEGRO_EDITOR INTERFACES Import 3rd Party Logic $SCHEDULE removes visible ratsnest from database when using T-Points
+ g* t+ b) Q- O# H) L: H0 k1 G820792 ALLEGRO_EDITOR INTERFACES Import $Schedule command is returning illegal loop error for pin-pair based rules
; |: j2 b* w- B& r# M! m* k* p821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format
# m1 N" F5 L! G9 j7 h4 h821504 MODEL_INTEGRIT TRANSLATION dmlcheck failed when .dml translated from .mod was opened by MI.
) s) e/ f; s& U2 H: N. K821827 ALLEGRO_EDITOR EDIT_ETCH Allegro Crash on routing Diff Pairs
6 q" p A* n' p821836 CONSTRAINT_MGR OTHER Why the min/max propagation delay analysis is failing for one of the pin pair in this design!9 G: v3 n! P: q( n- x
822090 CONCEPT_HDL CONSTRAINT_MGR Crashed the Constriant Manager and SigXplorer from DE HDL- @/ k3 B! @. b
822744 CONSTRAINT_MGR DATABASE Xnet lost after DCF file imported into Constraint Manager
: `: H5 f4 [9 K D$ S5 V1 m3 C822827 PSPICE SIMULATOR Simsrvr crash upon running simulation
7 p4 h& b7 t/ y1 x# |: [. a) g3 R822844 ALLEGRO_EDITOR SCHEM_FTB Constraints are not updated in the brd file when working with Library defined diff pairs2 C' q+ u) [. @# H! {
822942 F2B DESIGNVARI Variant view does not show DNI on functions
7 E" _! h( b3 C/ Z823177 SCM BROWSER PPT_OPTIONSET_PATH defined using environment variable is not recognized by ASA/ l9 y* I! S3 F( W+ x5 N
823200 ALLEGRO_EDITOR OTHER Import Logic hangs when dynamic phase control set$ k- {% B6 r; {" m1 ~" P; O
823589 CONCEPT_HDL CORE The operation could not be performed because no object on the drawing was selected- u$ E, ?+ I$ g; ]8 o
823821 ALLEGRO_EDITOR MANUFACT Allegro crash when trying to Gloss -
& J% g# W4 g* m8 P8 R823833 CONCEPT_HDL CORE show vectors command
5 l3 p' z, x. r824902 ALLEGRO_EDITOR DATABASE Lose connectivity when copied via and cline structure# c" v( a, v5 N* i
825289 ALLEGRO_EDITOR DRC_CONSTR duplicated drc and waive drc- x3 j6 r, c. m0 |% D: h: T
825969 CAPTURE SCHEMATIC_EDITOR Refdes are getting reset after doing a replace cache/update cache for a generated pat' w- E5 d, M. \; g" p
826068 ALLEGRO_EDITOR MANUFACT Adding Thieving on the negative plane layer doesn't show up
; \- P3 C/ r8 l! s' Y9 w [826266 ALLEGRO_EDITOR DRAFTING Datum Dimensioning Crashing Allegro in Linux
0 W% Y C4 b, j& w. x* F827032 SIP_LAYOUT ASSY_RULE_CHECK SiP Layout crashes when running Assembly Rules checks F- U& ~7 ?( ?" b" S+ N. o3 m5 K
827494 CAPTURE GEN_BOM Include file is overwritten for the STD Capture BOM if .txt file used as include file
/ p' \! S7 W* L/ L: [* R- Q4 u7 K827575 CONCEPT_HDL CONSTRAINT_MGR PINUSE
7 E2 k2 b+ {, o- X O2 _5 q9 g827708 APD 3D_VIEWER 3D viewer assign black color for all layer
( C( F6 e4 [1 Y* G8 f828263 APD DXF_IF When the DXF out is executed, offset of the padstack is not correct.
7 x3 N% a9 ?, n$ {4 W8 \# K3 P828788 ALLEGRO_EDITOR DRC_CONSTR Soldermask Waived DRCs reappear in 16.30 |0 ~- M/ M8 W7 \: L' C, ~
829046 APD MANUFACTURING create plating bar makes net name changed to dummy net
6 D$ a1 V; Z8 Q# V829331 SIP_LAYOUT PLATING_BAR Create Plating Bar is deleting existing fillets.& I2 ?' i1 X4 Q
829336 APD OTHER Request the ability to merge two nets together into a new net.
! h( q9 n! O t, Z3 J0 R2 T* Z4 ^# ]
DATE: 09-23-2010 HOTFIX VERSION: 017
2 B- e! U- A; [4 a: Z1 A===================================================================================================================================( _( S. T M/ a0 [1 b1 H. {5 s2 l+ v
CCRID PRODUCT PRODUCTLEVEL2 TITLE8 s: x u% M, E0 Q3 Y! h l/ p6 J
===================================================================================================================================9 |# l. \# @' I7 U+ C W: Y
676210 CAPTURE PRINT/PLOT/OUTPU Enhancement for correlate lower level pages with H blockes in PDF
% i) J, _7 L) n736942 ALLEGRO_EDITOR INTERACTIV Autosave is not working with every application mode.
% u9 x7 Q: ]2 r746256 CAPTURE ANNOTATE Intersheet refernces change their position in V16.3 even on unchecking ‘reset position’.( }, A/ I5 ]. A- \ o
785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error
2 B/ O% v) D5 m791549 PSPICE PROBE PSpice cursor does not remember value outside zoom area
. B6 R7 `; ]7 @( O, m. S- Y802639 F2B DESIGNSYNC BOMHDL crashes if colon is used as a sub design suffix separator0 f- l- S4 V& k1 `1 G# X
804475 CONCEPT_HDL OTHER RMB+MMW doesn't zoom in/out anymore with ISR0127 D6 B8 P" g3 h9 s! H; C
807025 PSPICE PROBE Loading dat file slower in 16.3 as compared to 16.2
$ ~: r3 @; Y# e, w808550 CONCEPT_HDL OTHER On Linux Import design does not obey umask or setgid settings3 u0 J& k3 T' d! F4 q
810568 ALLEGRO_EDITOR PADS_IN Can PowerPCB 9.2 - Basic file be converted to Allegro?, N" z; L9 U: p2 Q; O
812089 CONCEPT_HDL OTHER The colors on the Options form dont seem to match the colors displayed on the schematic canvas3 X6 g( J; c" L& f9 C
812475 ALLEGRO_EDITOR INTERACTIV Saving .mdd always results in working directory! M. z( V4 N! x, z: c( d
812836 CONSTRAINT_MGR DATABASE CM Custom Fomula -Handling of Pin_Delay is inconsistent in Analyze
0 Y0 I* u2 S4 V: B812994 SPECCTRA ROUTE Max_total_vias constraint not working correctly when wiring option is set to "starburst".
/ f% e* n: X( o6 l: S: o0 s816561 CONCEPT_HDL CONSTRAINT_MGR OLECS.exe Runtime Error occures when attempting to launch SigXP from a net in CM
6 g f2 f5 l% W' e5 G7 r& m$ a816879 SIG_INTEGRITY SIGNOISE Program has encountered a problem and must exit in 16.3 S014(v16-3-85AT).4 V( _/ d- W2 T, r
817006 SCM UI SCM copy signal changes existing signal names3 ^) k: B3 i! d0 |
817896 APD ETCH_BACK Etch back - improper use model
4 V; `8 Q* t* n* d* `) N818242 ALLEGRO_EDITOR SHAPE Thermal relief connections not orthoganal and creating acute angles.
1 B6 v1 @, k: P; g' p3 d% N! x818429 ALLEGRO_EDITOR PLOTTING Pins created from shapes do not plot solid.
! K' X3 H7 P* o6 W* u) S818513 F2B BOM Alphanumeric BOM not placing REF DES in proper order
/ n0 k( w- n( ]818818 ALLEGRO_EDITOR INTERACTIV Place replication does not recognize mixed case characters in file path4 M# {) Y4 U& g g, u
818910 CAPTURE FPGA NC simulation flow is not working with 16.3 release8 b4 n' C z$ S" d, u. A" Q9 h
819108 SIP_LAYOUT DATABASE Wirebond profile constraints lost after saving and re-open sip
4 [ E( t; k5 O819151 SIP_LAYOUT ASSY_RULE_CHECK ADRC is showing X-D DRC markers on good Soldermask Shapes when doing a min. shape check.5 i v" A: v. C3 @% Y& t
819183 ALLEGRO_EDITOR MANUFACT NC Drill file generated for Backdrill layers show wrong Quantity of the drills4 \* S# F! w" S* G; R# _
819269 SPIF OTHER File > Export > Router Crashes Allegro and dsn file creation stops+ M" W; y+ h9 w
819463 ALLEGRO_EDITOR DATABASE VIA has illegal connections.
( ~% {; V- S' R819842 ALLEGRO_EDITOR INTERFACES File Import Logic fails on syntax check when following documentation for $schedule command/ d+ G0 g% e. H- }6 t! f/ F
820177 CONSTRAINT_MGR CONCEPT_HDL Net_class objects that are changed in CM at Front End are missing after Import Logic
; g1 U5 e: x4 U+ F820231 ALLEGRO_EDITOR DRC_CONSTR Allegro hangs when multi thread DRC is performed after updating padstacks
+ a, y" u V/ e3 t- v" M820373 SIP_LAYOUT OTHER Update symbol flags the "edited pins" error but still updates the symbol and then crashes.
" ]# O3 @' p% K$ { C: b( P820381 SIP_LAYOUT WIREBOND When opening a new design, with a design already open, the tool will use the first designs profile settiings9 [# S% E6 {: A3 X4 `
820634 CONSTRAINT_MGR OTHER Netrev fails without any useful message when importing ECO netlist
! x$ I# B n+ N' F. {820665 ALLEGRO_EDITOR REFRESH Qvupdate is not working in 16.3
( T5 P) z3 I. A2 }820849 ALLEGRO_EDITOR MANUFACT NC Drill has wrong quantity and also a drill is missing
5 W4 s" O; [. B) Q821154 CONSTRAINT_MGR CONCEPT_HDL DE-HDL CM Import Analysis Results fails without any feedback
% Y& r6 n7 L% D4 ]" s7 t821195 CAPTURE OTHER Updating Cache generates errors including CAP0027 on Capture DE CIS with ISR s0014 and onwards.
" K+ ?$ I& |/ C' k. [821856 APD MANUFACTURING Create Bond finger Solder Mask issue
/ u8 J# d+ V1 O! u821936 SIP_LAYOUT COLOR Can not clear custom color of bondwire profiles
* G6 m0 f: a2 g8 W# d- V; s822841 ALLEGRO_EDITOR ARTWORK An issue about Gerber6X00
# z/ q0 ?7 g6 f0 H1 y8 T822842 SIG_INTEGRITY OTHER CM and Show element report different lengths0 p! z b3 X1 {9 Q& r
823559 SIP_LAYOUT BGA_EDITOR When doing an Edit > BGA the tool will shift the BGA's position when at 90 or 270 rotation.
9 r, I4 v' |$ j1 \3 ]7 Z7 N; ^) k+ q823688 SCM SCHGEN Schgen changing the physicals bus name in the preserve mode for some of the bus
5 ~5 j4 ^- T) T# w823792 CIS OTHER Capture CIS performance over WAN for bulk operations are slow, q4 c) d0 m) |7 w8 S! J
6 s9 V2 N: a) h$ m( {
DATE: 09-10-2010 HOTFIX VERSION: 016# B4 E5 _% A% Y4 J9 _
===================================================================================================================================
/ q8 f. x* P$ U" ~. F" pCCRID PRODUCT PRODUCTLEVEL2 TITLE
' D& A" G+ J& s===================================================================================================================================' C& K1 w! o8 a, m! T/ i
604662 VLS-L VIA When changing Rows/Columns values in Edit Via Properties form, different value are assigned.8 r- Z( ?$ X8 ^9 D* j3 \: @. O
747191 PSPICE AA_SENS Pspice crashes when starting Advance Analysis
1 ]" O$ G$ |7 s1 p756103 CONCEPT_HDL ARCHIVER Archiver does not include all the Parts when design blocks are copied from one location to another
& P9 V! ` y% s0 A7 E# @0 W5 {' C758487 APD 3D_VIEWER package substrate (BGA) outline should be on a separate layer, not on bottom conductor layer.
+ h: k" e, o5 j6 d# s8 D7 a; |2 S; M764417 APD EDIT_ETCH Routing with Diagonal entry (45 degree) to Constraint Regions does not work4 k7 a: T* C C4 e
766409 PSPICE PROBE Copy to Clipboard changes the label text colors, t- u! ~: O# x' o5 i
784577 CONCEPT_HDL COMP_BROWSER SingleclickAdd 'true' places does not pick the correct version3 |1 c( _9 V) W9 }
784814 SIP_LAYOUT ASSY_RULE_CHECK accuracy of acute angle DRC
# s" R9 Z, S- D' m d0 ]* i792039 CONSTRAINT_MGR OTHER Doing a File->Import->Worksheet Customization from Constraint Manager will change the working directory.
Y' C; G+ U$ U& ?9 D; A z796517 CONCEPT_HDL COMP_BROWSER Component Browser showing wrong symbol
, ~) y% S( J7 W# e801944 SCM UI SCM dropping terminators and pull-ups when renaming signals (copy - paste special)
2 ^. \) ~( m1 E) j: C" S" [1 d804627 PSPICE PROBE Printet text labels have wrong location
+ d! A; g. g0 ^) h0 ]9 W0 T810479 FSP DESIGN_SETTINGS Not able to connect some peripheral signals to FPGA manually3 z! F3 V- ^- D+ _( K' y8 A# R- X8 A
810814 CONSTRAINT_MGR OTHER T-point does not create when import DCF file./ ?5 w. t2 v- k& n/ V9 |% F
811032 ALLEGRO_EDITOR EDIT_ETCH Enable enhanced pad entry to support pads as shapes, r- T, ~- C0 N/ n1 }7 K! V! L
812643 SIP_FLOW CONSTRAINT_MGR Physical Constraint values disappear after entering constraint mode: V0 G* h8 o8 [
812835 CONSTRAINT_MGR INTERACTIV CM Custom Fomula - "Analyze" on the header of Actual does not analyze pinpairs7 ?# ~7 L: Y+ {1 B N$ o) J' C
813435 SIP_LAYOUT DIE_ABSTRACT_IF Invalid parameter passed to ICP utility API8 A5 r0 I0 s6 I9 w0 Y- a
814060 CONCEPT_HDL CORE Read only library becomes writeable when updated
& ^' {6 ~6 C% N3 V# X$ y: l1 w814347 ALLEGRO_EDITOR ARTWORK It seems like not work ”detailed text checking” on 16.3.- `, d5 \7 t1 l2 [) c
814451 ALLEGRO_EDITOR DATABASE Allegro get crash when run dbdoctor
" X2 y1 f, @1 S3 g9 @$ a* v. z814496 CAPTURE ANNOTATE Lower level part refdes resets to ?6 G3 j l; l% F8 o) _, n7 U
815150 SIP_RF OTHER sip layout export chips output is not correct
: C" p# z9 F* j816034 ALLEGRO_EDITOR MANUFACT Backdrill Passes not work from bottom5 O# \: B1 l! I; {* F5 s
816065 APD DATABASE Export Libraries with no library dependencies selected creates package symbol without pins.
% w k% x9 e8 v816426 ALLEGRO_EDITOR SHAPE Dynamic shape not updated when component is unplaced7 d; Z1 M* r% T% ?$ j
816616 SCM SYSTEM_OBJECT codesign incorrectly maps primary and secondary codesign object8 n2 x( R6 R$ \/ @
816686 ALLEGRO_EDITOR TESTPREP Probe Spacing rounds off 3 place decimal to 2 places
- ^- h7 ~& [: P# N$ W3 a, g816917 SIG_INTEGRITY LIBRARY Issue for loading interconn.iml
, h7 E0 t' c2 O" W$ r816986 ALLEGRO_EDITOR MANUFACT Mfg>NC>Backdrill analysis with passes set at Bottom layer is automatically switching to top, hence failing!
3 H( ^ ^+ S. t, c; y; }817473 CAPTURE NETLIST_ALLEGRO Backslash (\) is considered as illegal character for netname but it was allow in SPB 16.30.010
: h3 `5 A1 ^5 q6 k% Y. ]817606 SIP_LAYOUT WIREBOND When moving Bondfingers the Via's are sliding too when they should not.
, r0 @# t7 Z# O: g5 x* d4 h1 r! u% L( k& L
DATE: 08-27-2010 HOTFIX VERSION: 015/ k5 g% g( x1 q: `' B" A! C
===================================================================================================================================
. O' ]4 J3 O5 I9 n* aCCRID PRODUCT PRODUCTLEVEL2 TITLE
* H' K, e# |! \9 I& ~* k- ?===================================================================================================================================
) H1 I, n- X; K& U7 V664821 CAPTURE NETLIST_ALLEGRO Improve error messages when netlister finds illegal characters in the pin names
. b# z0 q) @! |6 z: p753867 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV crash when graphics from one symbol to another
& Y' d9 A. M/ Y/ \$ E777559 CAPTURE OTHER Why the Reference designators get lost in project with external references.
9 i- _2 n5 ~/ z9 E4 ]6 [1 B6 ]777657 CAPTURE PROJECT_MANAGER Archive Project causing Capture to crash( X" u- L9 s6 o: [, k
785748 SIG_INTEGRITY OTHER 16.3 SI model library path directives behave inconsistently if the ~pcbenv/env file is present* ?' v4 c1 {, z
789529 ALLEGRO_EDITOR EDIT_ETCH Neck Gap changed to Primary Gap when executing Delay Tune command.% M: `% d2 o8 M- P- ?3 v
791853 SIP_LAYOUT EDIT_ETCH via slide clips to 45 angles near BGA3 d. r6 R. |" Y& U1 C
796604 MODEL_INTEGRIT TRANSLATION ibis2signoise replace V_fixture_min with V_fixture_max based on the value.
5 @. \4 h7 r$ r! y797657 CONSTRAINT_MGR CONCEPT_HDL constraints from the brd file are not passed on to the schematic.- w/ ^' T2 ?2 W: _+ @
802760 ALLEGRO_EDITOR NC nc route not generating the circle correctly
$ n+ M9 [/ n d; L6 `803572 MODEL_INTEGRIT TRANSLATION quad2signoise fail if MODEL name include backquote.% _1 Q1 i( s1 f% P1 H- o
803869 SIG_EXPLORER OTHER Trace parameters form does not update with correct stackup data
$ ]. W. _, N" ?$ E7 t2 a804070 ALLEGRO_EDITOR SKILL The skill setting objects not match to all items in CM.! V" @( S/ \/ ~
805641 ALLEGRO_EDITOR COLOR Clear all nets fails to remove the custom color on the Color Dialog form
6 J2 f7 n0 y1 [7 j5 `+ o* s ~9 ?806115 PSPICE MODELEDITOR Cannot generate a Capture symbol from Model Editor because no Capture license.
- W% @, _/ o) p4 X L4 o& W. E806196 CONSTRAINT_MGR OTHER Netrev fails with warnings.8 x( p3 \' h8 t+ n! R0 [: {7 d
806864 CONSTRAINT_MGR CONCEPT_HDL "Selected nets/xnets only" option in CM connected to DE-HDL
* U" M( c. ]" l9 R9 u807960 ALLEGRO_EDITOR COLOR Click OK to Color Dialog box and Shadow Mode ON/OFF setting will be lost.0 C5 _5 S# i5 r. K; X! y# f0 z
808155 F2B DESIGNVARI Variant Editor variant.lst and BOMCompare not the showing the same data: e4 o7 P" J) g( a
808392 SIG_INTEGRITY OTHER Cross section impedence not calculating for SPB 16.3 with single license for OrCAD PCB Editor
5 Q; T; d- s0 @/ k$ d/ E+ v2 i808978 CAPTURE STABILITY Unable to Place > OLE object > Visio drawing file. Capture crashes as well
- U/ _. S) ]4 u4 P6 h809163 SCM PACKAGER scm crashing when running export physical
" A* L! Q8 R7 `809526 ALLEGRO_EDITOR DRC_CONSTR multi-thread DRC hangs when replacing padstacks
) L9 l" p- {5 u8 A9 {( S! A4 S809587 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV crashes during Text Cut/Paste operation in Symbol Editor: K% d9 U5 c- s" b6 p% s
809636 ALLEGRO_EDITOR DRC_CONSTR drc update reports incorrect DRC count when run after deleting unused region in constraint manager.
9 N$ ]: |, O# G809847 PCB_LIBRARIAN CORE "Auto add SWAP_INFO to chips" problem+ h0 e' M0 W; T- M- i+ z" y
810024 ALLEGRO_EDITOR SKILL axlGRPDrwText does not work for left justification* s4 {; p. ^! Y# h9 S4 n$ P
810530 ALLEGRO_EDITOR EDIT_ETCH Sliding vias on differential pair is not selecting both nets
4 ~( \* X, p9 d0 H9 ?810860 ALLEGRO_EDITOR DRC_CONSTR Improve Update DRC efficiency0 u( l$ M$ N) f' Z9 ~3 g# I
811506 CIS ICA Using Capture V16.3 ISR0013 “Save Schematic Part” option is missing in "New Database Part Wizard".
! [0 i$ _% `; f812259 ALLEGRO_EDITOR SCHEM_FTB scm crashing when running export physical- AGAIN
3 U/ \$ r1 ~; h( c; o. W* E812269 APD WIREBOND Wire diameter and wire profile automatically is changed when executing wirebond add command
# h% V5 o, r7 y812597 PSPICE SIMULATOR Pspice crash.) V* j3 [3 D. p/ q- O
812655 SIP_LAYOUT IMPORT_DATA Importing Stream data multiple times into a .dra will have inconsistent results, each import is different.9 x8 d6 t) J6 }) O! G
813253 ALLEGRO_EDITOR DRAFTING Datum Dimensioning Crashing Allegro
7 [4 Y$ |' A; h8 N813265 APD WIREBOND Wire Bond Report fails with wires present that were added with the "Add/Edit Non standard" option.
+ V% B) S% f$ Z& |" F1 @# P5 e% w
DATE: 08-13-2010 HOTFIX VERSION: 014
, a B( X \" ]; y===================================================================================================================================
+ z) V9 a& O p _9 rCCRID PRODUCT PRODUCTLEVEL2 TITLE" T$ Y K! Z7 C5 s* N
===================================================================================================================================
2 e5 x; m& ]4 g+ V+ f1 c4 O792354 CONCEPT_HDL CONSTRAINT_MGR Viewing a second net in SigXP from Design Entry HDL constraint manager generates an error8 L2 c) O' }% k; v- f9 F
800336 GRE CORE GRE's Plan Spatial crashes Allegro.
1 V, K% v! x% W: }801116 SIP_LAYOUT WIREBOND Wirebond -> change characteristics with only wires selected should not modify connected fingers' placement at all.
8 C7 Z. ^* { `' ~801463 ALLEGRO_EDITOR EDIT_ETCH The Allegro axlShoveItems SKILL function behaves differently in 16.3 than it does in 16.2.9 W$ P( I* F S0 r6 n/ c& u% h% ]
803049 MODEL_INTEGRIT TRANSLATION quad2signoise cannot translate OpenDrain Model correctly.3 }" h. _* _( h" X( Z
803878 ALLEGRO_EDITOR DRC_CONSTR 'Via_At_Smd_Fit' not working correctly when the via fully covers the pin.$ {% y' z5 z" A8 f6 e
804273 ALLEGRO_EDITOR DATABASE Running update DRC gives different number of DRC.
3 [5 @- c# m1 O4 V7 a6 c) S804330 F2B PACKAGERXL Packager is changing the refdes in preserve mode for components in hierarchical block- @- n. X* `9 _ f% i
805335 F2B PACKAGERXL Packager fails reporting empty location values when the location values do exist
. M, n8 U+ r* J5 p& ]' O805676 ALLEGRO_EDITOR DRC_CONSTR Update DRC hangs while updating differential pair checks with dynamic
4 n1 l4 s& T* Q4 A* b% b+ [805747 SIP_LAYOUT EXTRACT Extracta crashes with this testcase and command file.1 {0 I- W7 N3 O& m2 j4 R9 {0 S
806028 ALLEGRO_EDITOR TESTPREP Allegro testprep parameters causes crash* a c1 _8 L \* [
806120 PSPICE NETLISTER “Enable PSpice AA Support for legacy" option results to undefined errors9 E8 i( E u+ h% E' K# z& x
806182 ALLEGRO_EDITOR SKILL axlPolyFromDB will crash if object is a pin on an unplaced component
2 G. G# z# f, E b L8 w807543 ALLEGRO_EDITOR DRC_CONSTR Via at SMD Thru DRC not working correctly in Solaris: K5 N* [: c/ [/ G) K; C# b
808047 SCM SETUP scm not loading all parts from pcb after running brd2asa7 R+ H+ C8 |. H# E5 X! B$ y+ I5 @
808831 ALLEGRO_EDITOR DRAFTING "Oops" command(in dimension angular command) crashes Allegro.
/ e& H- q% n. H3 h
/ i9 v3 k0 L* D. KDATE: 07-31-2010 HOTFIX VERSION: 013+ |: e2 `( V" [
===================================================================================================================================
( i+ K" L. E( \( }9 E! NCCRID PRODUCT PRODUCTLEVEL2 TITLE6 h. k* q9 t" e% I* Y w
===================================================================================================================================
l4 K) w/ O! ~/ ^ ] R576133 CAPTURE ANNOTATE Annotations in the design getting reset to ?
" F2 Q9 r+ x# I" |688692 CONCEPT_HDL GLOBALCHANGE Global Change does not respond to RMB> Done$ a6 } ^/ m8 M) M; Q
731045 CIS EXPLORER Double click in CIS explorer places two components
& t; B5 |: B$ n$ L763550 CONCEPT_HDL SKILL nconcepthdl in 16.3 no longer recognizes skill functions that worked in 16.2
) Z" m( J, y: |4 b" _# W764130 CONSTRAINT_MGR OTHER Export Excel from CM hangs/crashes Allegro on attached design
2 y/ m* M8 A: P. G% A) @766750 ALLEGRO_EDITOR INTERACTIV Request to enable datatips when constraint manager is open and a command is active, z# `% {( F: R$ t2 y1 l7 n
774466 CAPTURE CORRUPT_DESIGN DSM0008 - Unable to open design in 16.3
2 n( d% I" X4 j, D+ l777862 CIS PLACE_DATABASE_P Absolute path in field Schematic_Path causing incorrect display property
& c) s; M) i: ]7 `4 V782370 CONCEPT_HDL OTHER CreferHDL $XR hyperlinks do not work in PDF Publisher - they did in SPB16.2
! W% i% N1 z* Q+ V- F4 h' [783036 SIG_INTEGRITY SIGNOISE Problem for Waveform saving with -w option in signoise command.
( N1 u8 {3 c8 x9 S/ {9 b784205 CONCEPT_HDL CORE Schematic block generated from SCM needs to have DIFFERENTIAL_PAIR property on the ports1 ^ m: z% k; [+ X
786387 CAPTURE OTHER Update cache does not update the parts on schematic
! L: ]# h1 j5 t7 u, q) ~$ M786560 CAPTURE NETLISTS Sqare bracket [] is not allowed in PADS netlist.+ u& ]" Y8 V8 _8 y8 S
786808 SIG_EXPLORER OTHER RMB > Via_Model_Name doesn't display the generation param of the via.9 R' Y6 s7 s W& T
787414 CAPTURE PROPERTY_EDITOR Part value can’t be moved on schematic if a part has been copied to a new design and not saved yet.& |7 I% m" z; y4 C( n
791965 CONCEPT_HDL CORE group move should not snap to center of group
; ?% O5 b; o( J3 ^9 }( j3 q( [792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets
6 R5 D' `! {. l8 Y& B, |794900 CAPTURE NETLISTS Attached design is not getting netlisted in V16.3. It works fine in V16.2: }2 n7 J# w2 f# Q( |: E
795914 PSPICE SIMULATOR Getting RPC Server Unavailable Error) X9 L, G8 A' \. h+ E- L B t
795997 ALLEGRO_EDITOR TECHFILE crash when importing dcf file1 b, D8 Y- F% P" p$ a1 O
796124 CONCEPT_HDL CORE Messages overflow console
' y6 q" u+ z. Z6 u: _+ M6 t5 Z796168 CONSTRAINT_MGR CONCEPT_HDL Create ECSet in DEHDL CM moves focus to DEHDL
6 h- k" m& p9 Z0 ~( I* v$ g! Q796378 ALLEGRO_EDITOR PADS_IN Pads_in has error while translating PADS 2007 asc file. s6 }9 e: e$ W' O' N; T
796658 APD OTHER Allegro can not import the property section of 3rd party netlist correctly.9 M; |# S$ i8 b" p
796926 CONSTRAINT_MGR OTHER Importing Custom Worksheet file does not overwrite the Description field.
$ h f! S/ j: z" H4 e* e797387 SCM SCHGEN Increasing the grid units from 25 to 100 breaks the bus into bits on the generated schematic.8 N5 }$ H; G- A
797529 SIP_LAYOUT IMPORT_DATA import BRD to SIP fails if database has partitions. even if only silkscreen and documentation exist( @; H7 s n! V2 k" r8 A" o/ ?: U
797634 SIP_LAYOUT DIE_EDITOR rat control buttons in edit die mode are invisible until user selects an action
: o& V8 A9 H$ f797663 SIG_EXPLORER OTHER Current probe could not get from sigxp left symbol panel.
, a6 A! y3 C e5 O798118 SCM REPORTS SCM report not resolved with CCR 697709- |/ q$ k$ o& k5 {$ G+ {7 U e& C
798464 ALLEGRO_EDITOR SKILL axlDetailLoad not filling shapes in 16.3 s10
* P3 Y [# F1 w3 f1 c# D! \ i798980 ALLEGRO_EDITOR DATABASE Unable to open board file as it fails with a error message Found bad data pointer, run dbdoctor.2 W4 b, V7 {0 @; |0 H, r& K* F
799445 PSPICE MAG_DESIGNER Magnetic Parts Editor crashes while saving newly created Magnetic component
5 h7 T% j$ ~' f: y( v799539 CONCEPT_HDL COMP_BROWSER PPT Options settings lost when cancel done in PPT Options form. o, V; @) C# i# _) O1 s
799957 CAPTURE CORRUPT_DESIGN Capture crashes while doing save as in 16.36 u7 r% F! t% ?- Y6 d2 p
800280 SIP_LAYOUT WIREBOND Swappoing Dies in the die Stack will cause the bondfingers to move and create DRCs
; m0 ]) w; c, s, u800542 POWER_INTEGRIT SIMULATION Multi Node Simulation does show actuall waveform, s" V, I9 I7 {
800695 CONCEPT_HDL CORE Genview changed behavior in 16.3 HF 11 breaking the design hierarchy
/ n3 p, j4 c$ `0 m800751 ALLEGRO_EDITOR DFA DFA placement does not understand package keepout+ V2 B/ s# C$ ?& s
801017 ALLEGRO_EDITOR REPORTS APD Crash when creating Unused BB Via Report, l! V: h: ?8 a2 c* J6 n# g
801043 SIG_INTEGRITY OTHER SigNoise Case Update seems to check ActiveDesignLink value incorrectly.
& ]+ ]% s/ x' f3 L801433 ALLEGRO_EDITOR MODULES selected figures do not end up in the module
2 r! o f. @ f' x5 @7 ?7 A. b" ~801705 ALLEGRO_EDITOR SYMBOL Shape symbol was specified with RegularPAD of the PAD stack become "Null".) w" I! D; Z* F7 _" e
802319 ALLEGRO_EDITOR SHAPE Shape status cannot be changed to smooth using suppress pads.& ~' D. F; { N M' b; H! p
802474 CONCEPT_HDL LWB-HDL Testbench generator not working in Linux0 [) x1 q- j3 h' d
802887 ALLEGRO_EDITOR OTHER Adding the No_Shape_Connect property to via causes the application to crash.- |: x, P$ E! K7 G: ~$ S/ O
803393 SIP_LAYOUT DXF_IF Cannot generate a dxf file
( K# R3 h4 }- w, b P- m& i) {. L9 H5 \) v' W6 w9 i: |
DATE: 07-16-2010 HOTFIX VERSION: 012
! ^6 U3 u8 w9 e& q7 x B6 _===================================================================================================================================
/ C+ ~$ ]2 @5 ^% l6 z5 c& qCCRID PRODUCT PRODUCTLEVEL2 TITLE
6 D) V# t" ~: ?- s0 g, _===================================================================================================================================
: s. h) c. d6 y$ d757157 CONCEPT_HDL CORE Zoom (using SHIFT + mouse wheel) to work such that the tool zooms based on cursor location
9 w" B8 O/ R6 o- ?: c+ `* G766639 ALLEGRO_EDITOR EDIT_ETCH via structure disappearing after selecting place manual hide icon.
9 |8 w" t% I$ \% I3 J% x% H) k770910 PSPICE PROBE Printing from probe yields text label with too small size* g* K/ L5 [! d9 S t$ u5 p8 F
773603 SIG_INTEGRITY SIMULATION The characteristic of S-parameter model is different.) o7 F2 h+ y5 J5 o
774363 CONCEPT_HDL CORE hier_write didn't report error.# M% `+ z# q3 q' i% S3 {2 c' \! e/ g
776991 CONCEPT_HDL CORE The Wire> Bus Name command does not use the Net Name font setting0 n" \. @' [) Z2 C7 N* s
781965 PSPICE PROBE Unable to add trace expression with small letters# q' M; Z" L, t! f8 T
782847 SCM PACKAGER PKG-10002 - Cannot associate a logical part from chips.prt. t+ \$ [6 W) o+ D3 a
783245 SIG_EXPLORER EXTRACTTOP extracting net with trace on plane layer giving unconnected topology6 J' r( W0 k0 e0 B/ \7 n
785320 LAYOUT TRANSLATORS L2A translation fails with error "output directory is not writable".
% {, c' N& { Z785401 SIG_INTEGRITY OTHER The "View Geometry" or sigxsect command is not working in SQ 16.27 F% V9 q4 G4 n8 F }3 N
785715 ALLEGRO_EDITOR PADS_IN PADS_IN fails to convert some components on Bottom Layer and adds two components at same location
l; ?6 m2 t1 o3 `, v7 C$ }785868 SIG_INTEGRITY OTHER Unable to generate Parallelism report as the report seems to have hung the SQ Session.
0 l& v9 e# I+ @; i( j788523 CONCEPT_HDL CORE selecting QuickPick toolbar button should not reset canvas zoom
' U) L5 U% K5 |789333 CONCEPT_HDL CORE Font colors not being used as set in the SITE .cpm file1 T5 \! k2 \& G
789348 ALLEGRO_EDITOR EDIT_ETCH Via Structures removed from database when switching to any App mode from Placement App mode
1 O4 o1 D$ p4 ^/ e789473 SIG_INTEGRITY OTHER Via delay is not included when t-point is at the via
$ R% I; X! N/ b/ \' w789744 ALLEGRO_EDITOR SHAPE Update Symbol with cline at symbol level do not connect clines properly: S1 s: p% _. L
790170 F2B DESIGNVARI Function of Variant Editor and Annotate schematics+ I! ]4 b0 ]" ], b' u
790811 APD ARTWORK Some Void shifts by the artwork output.
7 ]2 y3 e9 l+ R: @0 D) F% F" ~791371 ALLEGRO_EDITOR REPORTS Dangling line with cpoint not reported in the dangling lines report.
+ ^$ N i) B3 h+ w$ q9 P2 g0 ^791486 CAPTURE PLUGIN_INTFACE Unable to open a PSpice Project by double clicking the .opj file, if Capture is already open& b0 r" N) y2 S* e, T
791663 CIS RELATIONAL_DB Relational view doesn't appear when capture opens second time! _9 x, P2 Z& a7 _ U6 `
791690 ALLEGRO_EDITOR EDIT_ETCH etch editing/routing in placement mode, allegro looks for all libraries adding delay in routing.% {" x$ d$ W: }/ j' z2 s4 h& _2 T2 z
791720 ALLEGRO_EDITOR DATABASE Color Net param file does not have some nets with special characters in the Net name.
9 E( d# w: _' G. G' G% L" u% Y791987 ALLEGRO_EDITOR PADS_IN PADS Translation fails with no error message
3 T- R9 r* f0 s( Q792232 ALLEGRO_VIEWER OTHER Import parameters not bringing in plane colors in allegro viewer
1 W9 X7 n/ t$ v8 l5 n8 y! M8 j792559 ALLEGRO_EDITOR DATABASE Error when executing refresh symbol command" V( O V& n& R q
792923 ALLEGRO_EDITOR OTHER sted fails Can't open STED stroke file ~pcbenv/allegro.strokes/ Z% O. R* ~! |+ \
793358 SPECCTRA PARSER When I try to invoke Allegro PCB Router it fails to invoke with errors.9 N' I; m/ f! q% |; ]2 F
793605 CONSTRAINT_MGR OTHER Importing custom consmgr.wcf file crashes Allegro.
* k! E, t6 R0 f8 b793955 ALLEGRO_EDITOR DRC_CONSTR add connect launch signoise even so electrical drc are all at off: x: A0 \. @' G/ F8 D
794748 LAYOUT TRANSLATORS import fails with message not valid Allegro subcls
* I F; ~( k; d+ {794775 ALLEGRO_EDITOR SCHEM_FTB Import logic runs forever or get a netrev error without any explanation
2 Q0 b% V- _) z7 g795261 CAPTURE NETLISTS Create netlist hangs in SPB16.3/ k9 Z, a4 ]: l, U4 z& b' b
795364 CONSTRAINT_MGR OTHER bookmarks are not getting saved in CM- t/ J% ]& h0 o: J& f. E1 u
795410 APD BGA_EDITOR Using the Edit > BGA tool I cannot get it to modify the pin numbering of a BGA
" @) ]1 v. U9 ?+ o' F! s$ X795501 PSPICE PROBE Unable to see the Multiple Mark-Labels in Probe) N- }) u& r2 R. w# ?# m
795761 ALLEGRO_EDITOR DRC_CONSTR Design is crashing while executing Tools > Update DRC
) L& T% M4 z) g8 T, Q) l795770 ALLEGRO_EDITOR DATABASE void moves when upreving from 15.7 to 16.3
' w3 N l, B: p9 O) M- v g h796026 CONCEPT_HDL CHECKPLUS CheckPlus reports text overlaps inccorectly on Linux
' s2 D# k) G$ \796092 MODEL_INTEGRIT TRANSLATION ibis2signoise crash if Submodel section exist next to Component section." t. ^9 O8 D/ Q; E
796361 SIG_EXPLORER OTHER When dml file is loaded "Illegal format in device file" is outputted. L& f% L6 B5 T+ V, n! J6 T
796366 CONCEPT_HDL CORE UI windows in DEHDL are scattered) C# ]3 l* d |* ~/ R
796590 APD DRC_CONSTRAINTS CM Hole Spacing rule always set to 1905 in a new design./ N* Q6 j, X5 c. ]
796858 ALLEGRO_EDITOR DATABASE Deleting layers that has only vias moves etch from other layer on it and prevents the layer from being deleted.
; V! Z( I5 E/ }7 r7 T2 E
' L9 f( u; `& t% @: ?DATE: 06-25-2010 HOTFIX VERSION: 011
2 _* \2 ?& N# I7 r* g/ [===================================================================================================================================
! \5 o, W0 w1 [ ^9 i BCCRID PRODUCT PRODUCTLEVEL2 TITLE! }7 J* W: k; [1 `
===================================================================================================================================
4 V9 d5 j" `) c644128 ALLEGRO_EDITOR MANUFACT Enhance Backdrill for HDI Buried Vias! P1 [0 P% F# p4 }$ A
743746 ALLEGRO_EDITOR MANUFACT Sub-laminate back drilling -Arbitrary from-to layer drill capability needed
- o# i7 \, Z! v; S1 J% G773066 CAPTURE EDIF PinSwap information written in EDIF does not back to Capture schematic
. e8 F8 f# G7 _3 e9 u775690 CAPTURE STABILITY Design is not properly translated in 16.3- z$ U1 c: D1 C& G* j
782854 ALLEGRO_EDITOR COLOR Component Keep Out for the Top & Bottom layers not showin in the Color Dialog box, only ALL shows.
9 e2 Q" c e w+ D# N: h784439 SIG_INTEGRITY OTHER CM of 16.2 recognizes the differential pair nets as Xnet./ f4 M2 m' G& \; X- ~* U) u
785135 CONCEPT_HDL CONSTRAINT_MGR Applying an ECSet to a diff pair crashes Constraint Manager' J/ Z: m! m" L$ R5 z- M
785179 SCM OTHER Changing a differential interface signal to local corrupts the con file and ASA is not able to load% ]8 Q4 B5 ?3 P$ T: O
785332 SIP_LAYOUT LEFDEF_IF unable to def in to sip layout, f2 o ^0 j- B3 n
785423 SCM SCHGEN Schematic having incorrect connectivity8 Y: O& P" D7 W8 Z! v# B* k% H' X
786858 SIG_INTEGRITY SIGWAVE want to select license at launching sigwave! B1 M% {. B0 a; H
786871 ALLEGRO_EDITOR SHAPE Allegro dynamic shape not updating2 v3 i* s) q# v, h5 {6 V
786957 CAPTURE MACRO If an off page connector is renamed using macro the net name attached to it is not getting changed
- k' Y0 _# `3 x h, L( O787003 CONCEPT_HDL CONSTRAINT_MGR olecs crash in CM when rename librray defined diffpairs on this design.
" R, B% J# i K9 `787087 ALLEGRO_EDITOR DRC_CONSTR Diff pair Static Phase tolerance Error
) m( s5 Y9 b7 `1 o* {6 j6 e787174 ALLEGRO_EDITOR MANUFACT Reading filmsetup.txt file crashes Allegro6 K3 W& w, B4 I5 E7 t. t
788521 ALLEGRO_EDITOR DRC_CONSTR There is a difference of DRC between SPB16.2 and SPB16.3.
; l) O, T% E; f0 R9 B- Y0 b788652 F2B DESIGNVARI Variant Editor cross highlights incorrectly to Concept
1 v- W+ X; Y$ y, ?. O/ h' u788658 CAPTURE NETLIST_OTHER OrIntegra.dll netlist has inconsistent behavior
$ l) G8 y& n) M788718 ALLEGRO_EDITOR DATABASE Board crashes upon deleting Cline segments within BGA using Allegro PCB Design XL License.2 N2 m/ T, I$ W8 m% X! q5 V
789206 ALLEGRO_EDITOR SYMBOL Merge shape option causes attached *.dra file to crash
, |# N C- R @. l789324 CONCEPT_HDL CHECKPLUS CheckPlus output producing wrong values
3 d" i! @( b' ?2 ?- z' d790049 SIP_LAYOUT EXPORT_DATA Offset wire tack points disables wire in AIF Output
0 a% K+ t, z' f* w790503 ALLEGRO_EDITOR SHAPE Shape Void not correct8 o4 Y0 R: \: G5 {, G
790567 SIP_LAYOUT TILING unable to run the ndw tile die generator# C0 G$ L z) F! T2 w/ m
790622 ALLEGRO_EDITOR SKILL line width of internal segments within hatched shapes not correct when created using SKILL
) @- T; f# [" j+ Y" ?2 k5 D791075 SIP_LAYOUT EXPORT_DATA The shape that connects Merged Bond Fingers is missing in the DXF output.5 ?7 W2 N7 C& h* ~+ Z7 @
, T* ^" ]1 F( r: N5 H
DATE: 06-11-2010 HOTFIX VERSION: 0105 w7 R1 K' a( P# H- t
===================================================================================================================================) A4 R0 ^: G, j! h8 b( d& Q* ]9 e
CCRID PRODUCT PRODUCTLEVEL2 TITLE; D( n! O; l2 O, k4 |
===================================================================================================================================
. m7 K7 m H: X1 p9 a" ]4 \& q4 Q; |701724 CONCEPT_HDL CORE Page Down (PgDn key) Key is unresponsive* b5 M* D# N7 ]5 ]5 I9 F
722773 ALLEGRO_EDITOR DATABASE How can i add DUMMY NETS to a Net Class ?: A& K1 \2 q- v! ]
767874 ALLEGRO_EDITOR OTHER Component Geometry/Pin number not imported./ T) G# k( r2 n0 c5 [, d
769644 ALLEGRO_EDITOR SCRIPTS Why Command line script in non graphical mode prints everything to the screen when working with Windows?
H& U8 V: G) K* I778086 SIG_INTEGRITY SIMULATION extracted net yields unrealistic resuts +/- 100v swings
" \5 q1 i) Q' h5 F# e+ M3 D778915 ALLEGRO_EDITOR OTHER Export library dumps symbols with mechanical pins instead of connect pins
, `( \ ^: V1 o7 @779119 PSPICE ENVIRONMENT MC Analysis does not seem to honor Custom Distribution
) i) i! k! }# U# G- H, `779161 ALLEGRO_EDITOR OTHER Getting error-"illegal arguments passed to a dba routine" when connecting CLine to via/ s |) C9 Y6 c6 a4 k) _
779335 SIG_INTEGRITY SIMULATION HSPICE sim from PCB SI caused netlist error.5 ^# a* K @& i2 b4 I9 c) I
780314 SCM UI ASA crashes on paste special.% o8 p1 o6 p# Y2 }; |- |! I. p3 `
780345 CONCEPT_HDL CORE Pins look garbled when part is vertically mirrored1 X; m' m9 f) M& h; j9 A1 [
780811 ALLEGRO_EDITOR SKILL Request 1k limit of SKILL API be removed.
. c) I. ]0 F# ]7 _3 u. [781111 SIP_LAYOUT IMPORT_DATA Import Brd to SiP failed
% x: D# m3 C) w6 g; z; C781259 CONSTRAINT_MGR TECHFILE Import tech file crashes Allegro; I5 N7 p( k# m7 G- q) z* r! L0 w' M
781287 ALLEGRO_EDITOR DATABASE dbdoctor removes tespoints from odd angle clines leaving V/L drc
: u5 U H$ P" Z7 _4 e0 `781331 ALLEGRO_EDITOR SCRIPTS Script executed by command redirection operators is giving different o/p for v16.01 and 16.3. Q4 f: z. f7 g) m8 x
781647 ALLEGRO_EDITOR MENTOR mbs2brd is defining extra additional testpoint that is not present in Mentor database- T! N- e- I7 G/ e
781650 ALLEGRO_EDITOR DRC_CONSTR Update DRC hangs while updating differential pair checks with dynamic phase tolerance added from the logic import
1 g/ |; @$ M' x+ B# B781665 PSPICE DEHDL_NETLISTER Error simulating delay component1 M% e5 Q& B' J8 ~1 h' R
781688 CONSTRAINT_MGR ANALYSIS Application hangs on Solaris when executing DRC update
# h$ J' W' ?% ~6 f- q/ ]( d' a781799 ALLEGRO_EDITOR OTHER Unexpected results when exporting and importing text parameters
( _9 J; X% _" d781922 ALLEGRO_EDITOR SHAPE Pin doesn't connect as a thermal.
* z3 N5 K0 v4 ~3 s @0 K782124 CAPTURE PLUGIN_INTFACE Bias point display not getting updated for projects on network* |) m: O) O5 x" l# }
782415 SPIF OTHER File > Export > Router takes 5 hours to create a .dsn in windows....1.25 hours in Linux.- j7 S" n) R) V/ k
782566 ALLEGRO_EDITOR PLOTTING It seems like not work PLOT parameter "Auto Center" on tight paper size.7 L5 x' _$ `% Z' V" C; K+ H, C/ g
782628 SCM NETLISTER Connection change not updated in the Verilog Netlist. ^6 E0 B( L! M+ L
783059 ALLEGRO_EDITOR DRAFTING Create Detail with "filled pads disabled" doesn't work with irregular shape pad.
. j( u1 ]6 \4 `/ \: T/ n& t783142 SIP_LAYOUT IMPORT_DATA import bga text in on connector crashing sip layout0 b/ n( Q6 R" h& B( H
783222 FLOWS PROJMGR Edit Physical and Spacing constraints0 c6 Q% J( [! |) {
783241 ALLEGRO_EDITOR PAD_EDITOR Pad Designer hangs when attempting to save to file.
3 \( H z; w$ {% k/ }* r783283 SCM IMPORTS scm crashing with import physical
8 D2 x9 E5 i1 O% j! a) X783301 SIP_LAYOUT WIREBOND All Bondfingers not sliding along path.
R' R7 u/ o* f1 a- k$ T3 z4 |7 P783496 ALLEGRO_EDITOR MODULES Problem of module placement.
1 w( ?0 J# K4 \! M783813 SIP_LAYOUT BGA_GENERATOR Request to add new JEDEC BGA sizes to the BGA wizards standard JEDEC pulldown menu.
$ Z, f9 ?7 L0 o) T5 p784441 APD OTHER Users cannot delete layer even everything was deleted
) Y7 h* Z/ a/ V) W) b$ _% Q784639 ALLEGRO_EDITOR DATABASE both dbdoctor and allegro are crashing while opening this database
9 u0 i6 n$ L* v T9 B& a785100 CONCEPT_HDL CREFER Cross Referencer must not call Unix command on Windows platform. C$ a7 b; |. U4 [' x2 `
785385 ALLEGRO_EDITOR MANUFACT Allegro Crashes when using Datum Dim with Shapes.
- ^9 Z+ ~0 N# M# K, G+ [$ ~. _" n% u4 ~. f" Y0 d: `' G
DATE: 05-28-2010 HOTFIX VERSION: 009( R6 R# z- l1 k
===================================================================================================================================; L+ R0 t% k1 ?$ F! f4 K* B, w
CCRID PRODUCT PRODUCTLEVEL2 TITLE
: c6 {7 E6 V1 T+ h- @===================================================================================================================================
1 ?$ v% v9 ?9 r758913 APD OTHER uncheck default check buttons through options/preferences
% K% g3 m M' [. W1 _9 }, ?* j+ `763566 PCB_LIBRARIAN PTF_EDITOR The ptf command in batch mode always returns "abort"
. q& ?/ V/ p7 b$ _* d763662 ALLEGRO_EDITOR INTERACTIV Place replicate update creates numerous DRC on win platform r6 @! A6 w, ?2 r4 l) N
771088 CONCEPT_HDL COMP_BROWSER QuickPick adds incorrect property value when ppt optionset file is used. N& m8 a6 ?! ]% n4 f% s+ G
772285 MODEL_INTEGRIT GUI Model contains recursive calls fater port rename reorder funtion is performed on it.) ~7 c! O5 ^: m) u
774070 ALLEGRO_EDITOR DRC_CONSTR Allegro crash when sliding connections.+ _6 E$ @3 V3 y% C# D
774880 ALLEGRO_EDITOR INTERACTIV Place replicate stops with No available buffer identifiers.
& \* {/ |$ `) V9 a775443 APD EDIT_ETCH The routing of DIff Pairs when transitioning from a region needs to be smoother.
" g2 ^& u6 `" E7 S6 V" b776022 ALLEGRO_EDITOR INTERACTIV Allegro crashes when we use Ctrl+Click in Etch Edit mode for selecting a Cline Segment in Allegro PCB Design L
7 s: J2 I; w) i9 T776151 ALLEGRO_EDITOR REPORTS Shape report incorrectly lists thermal connections for SMD,Via and Through all as Through.* g: C; O7 N* `4 ?% p' e
776190 ALLEGRO_EDITOR INTERACTIV place replicate crash; select polygon zoom points9 z( J: v* R! c4 t2 Q4 p
776284 PSPICE STABILITY 16.3 design crash while simulating the design
$ C. L3 ^% }% E2 \" o0 @777556 SPECCTRA CHECK interlayer clearance output drc even so layers are separated by a power layer
+ U- [) U9 V) |, c777689 ALLEGRO_EDITOR SHAPE Shape do not void if Curved Fillets are used
! A% [* A0 G0 O$ ?7 a% p5 n777698 CIS RELATIONAL_DB CIS 16.3 ISR s007 - Relational feature doesn't work
1 J; u9 S# }* w7 C778042 CAPTURE PRINT/PLOT/OUTPU Some text are not searchable in Capture generated pdf
% }% I8 x# g2 F: _778350 ALLEGRO_EDITOR SHAPE Multiple Drill on pad gets round void instead of rectangular" T( `$ I9 s. H& j/ l& d [
778356 ALLEGRO_EDITOR SKILL Duplicate Vias with axlDBCreateModuleDef
% s- a8 g- D- B778782 ALLEGRO_EDITOR OTHER Display-measure and axlAirGap incorrectly report no air gap for multiple drill pin
- b: k1 I8 V( @8 \) A' b) [, x779146 ALLEGRO_EDITOR OTHER Moving component crashes Allegro. R: T; N' D: B6 G4 _
780213 ALLEGRO_EDITOR DATABASE Design saved in GXL when opened in XL gives misleading message.8 ~6 _) z- w5 W+ \0 G
780773 ALLEGRO_EDITOR SHAPE No DRC displayed when Place Bounds are edge to edge
# \& g* l9 z; D- `- a* n9 k, Z" \! n
6 w, Q' j) _1 \/ ?+ u1 Q/ s( U% f8 G/ uDATE: 05-14-2010 HOTFIX VERSION: 008; ?7 G* l) x- Q |; n& ]
===================================================================================================================================8 `( n9 ?% X$ H0 I% ]5 n. l6 ?0 B
CCRID PRODUCT PRODUCTLEVEL2 TITLE9 O9 }7 j: X- u, S2 e6 m
===================================================================================================================================
* V1 n# Q& R- t7 R; ^, r x$ ?697699 CONCEPT_HDL HDLDIRECT SCM Verilog output contains the line “defparam <instance number>.SIZE6 H. X' r5 F' g8 i
734169 ALLEGRO_EDITOR PLACEMENT Wildcard asterisk character giving "illegal char(s) in refdes entry." error in quickplace.1 \, G& B9 i: ~+ ?' Y, l
738970 SIG_INTEGRITY GEOMETRY_EXTRACT power bus issue with SSN simulation when device is on bottom) k7 z' }" f. J" W- l5 M6 B5 E- q
744762 CONCEPT_HDL OTHER Connection dot sizes do not match on printout vs. screen
: {; G/ Q/ M) t+ u$ D% _750371 MODEL_INTEGRIT GUI Model name in physical view cann't match the model in right workspace
! a+ ?6 f& K7 A% U, t: z2 b) G757024 CAPTURE STABILITY Capture crashes while exporting to EDIF
. K \7 O# L- F n1 g3 O759094 CONSTRAINT_MGR INTERACTIV One member of a diff pair will show Analysis Failed when analyzing the design.; v8 R2 g! D' Q- b: O
760178 ALLEGRO_EDITOR EXTRACT Crash Allegro when executing extracta command for big size design(size of .brd
J3 E0 C# V& k, s2 G761391 SIG_EXPLORER OTHER Incorrect rise time( {' _3 d4 ^% S8 l5 U! N
762402 ALLEGRO_EDITOR MANUFACT When photoplot(RS274X) of MM unit was loaded, shape was broken.
) F: Y/ H- y7 V0 C2 K2 O/ `762783 SIG_EXPLORER INTERACTIV sigxp - coupled tline on stackup layer should show solved impedance
' i: R4 i0 b6 Y; _! v763150 ALLEGRO_EDITOR OTHER Request - IPC356 output truncate the padstack size to fit into the columns 59-62 and 64-67 `$ X O; R" g3 ~
763556 SIP_LAYOUT ASSY_RULE_CHECK Assembly Rules Checker is displaying an array of confusing DRC's on a Soldermask shape.0 I- M( |9 v0 z- K5 a
764399 SPECCTRA ROUTE Manually routed trace in Allegro are ripped OFF after routing in SPECCTRA using Route > Route Editor.
8 H6 S! Q6 y% ^) d9 T" l0 Z764475 SIG_EXPLORER INTERACTIV topologies from earlier versions cannot be opened in 16.2 on a machine
1 Q, Q" J8 I! z o765287 ALLEGRO_EDITOR PAD_EDITOR attempting to open padstack fails with - database has a non-recoverable corruption.& L+ D% f, m% Q5 J% D8 S6 D
766041 ALLEGRO_EDITOR OTHER Auto B/B via generator incorrectly defines some BB vias
' ~+ f; X( R+ ?9 `; \4 F766153 ALLEGRO_EDITOR SKILL Allegro crashes when trying to extract padstack information% m' Z9 G, P( ]% H
766611 ALLEGRO_EDITOR EDIT_ETCH slide creates DRCs in ARK area" Y4 o/ b) ~! ]( l
767041 CONCEPT_HDL CORE The tap command failed because the specified tap body CTAP is invalid. }6 S* X, e+ a$ @
767146 FLOWS PROJMGR Project manager open last open .cpm in 15.7 version not in 16.3
$ w6 `! I) b' y767526 FLOWS PROJMGR Project Manager customization does not work8 p( O8 E# ?" f/ _) W3 u
767671 APD DATABASE Crash creating cline with axlDBCreatePath() on this database.
0 m; L7 E( [3 B3 T9 w767951 ALLEGRO_EDITOR DATABASE color net param file omits nets with bus brackets in the name; c3 M6 j; t8 L& p0 A6 M
768168 CONCEPT_HDL CORE Fontsize on instances changes when doing backannotation% I$ w! ^3 E* W0 L2 g- w
768207 CAPTURE STABILITY Capture crash while editing properties
) G7 W0 S% b: ?; o' B) Q* `; h* S768734 CAPTURE PROPERTY_EDITOR Properties of title block are not getting editted through spread sheet., b7 r! ^7 w1 A" C! h% t
768832 APD DRC_CONSTRAINTS Following Performance Advisor instructions results in much longer DRC check time.
+ X4 j' w% X2 v0 W* K6 F768990 F2B PACKAGERXL RFSIP architect 16.3 85Y Schematic to SiP fails due to softinclude in cds.lib file this problem does not occur on 16.2& c/ X+ U- @# e3 l/ N
769097 SIG_INTEGRITY GEOMETRY_EXTRACT Sip Digital SI-Bus Simulation function will shut down auomatically when it is running1 [. ?+ b( O( O
769235 SPIF OTHER need to be able to remove mbs_spif* properties added by mbs2brd, n9 g% m: p) J" E9 ?$ o# U1 U0 ]
769326 CONSTRAINT_MGR DATABASE Length by Layer crashing$ ?) {4 P9 y v$ c
769336 ALLEGRO_EDITOR TESTPREP testprep density - returns Unable to add the PROBE_DENSITY subclasses.
3 ^+ X# M1 c; ~# H/ N769458 ALLEGRO_EDITOR OTHER SMD Jumper has a problem about the connection point when using the Add Jumper% S: b1 y# ] l" L. X
769845 ALLEGRO_EDITOR EDIT_ETCH Diffpair routing out affected by line to line spacing rule.
$ A7 I7 s( z4 c+ W769934 SIP_LAYOUT WIREBOND Duplicate Finger Name.
1 H( U2 d+ h: |$ W% W. ^7 P4 Z770006 ALLEGRO_EDITOR OTHER Ratsnest_schedule[Power_AND_Ground] can not show figure without move symbol.: t# U a4 b q+ t8 P6 l
770125 ALLEGRO_EDITOR DATABASE PCB SI GXL Via Labels grayed out on formand labels not visible on the canvas4 u* q2 v( ]- i! n: l. n
770212 ALLEGRO_EDITOR DRC_CONSTR Incorrect Etch Turn under SMD pad DRC error on this board- n9 G5 h4 K( i
770230 ALLEGRO_EDITOR ARTWORK Artwork fails to suppress unconnected pads on pins with the net_short property.1 P' J. K1 f6 J3 ~2 a
770233 ALLEGRO_EDITOR MANUFACT Fillets are not behaving as intended./ H) F6 w' B; \: z" q! Z
770442 SCM PACKAGER Error during Export Physical - The subdesign block instances ares not updated with reuse properties
/ [! q2 V7 E, ]% e770556 CONSTRAINT_MGR ANALYSIS PCB Editor's Constraint Manager not updating custom constraint cell., b, z/ Q8 i) Z4 r0 I
770861 ALLEGRO_EDITOR PADS_IN PADS translation fails with no error message
) r1 c6 s; Q4 x1 K7 q/ b) s770872 SIG_INTEGRITY OTHER Opening Orcad PCB Editor for this board takes Performance License as well
' ? j; ~! `9 |+ B3 ]771117 ALLEGRO_EDITOR DRC_CONSTR Allegro PCB Editor crashes on Update DRC-16.3/hotfix006
, I0 o# Z' R9 \1 E% n771181 ALLEGRO_EDITOR PLACEMENT Component deleted completely from board file after we Mirror and rotate them while moving them.: U+ B4 ~$ R' h0 Y9 d$ u: O
771256 ALLEGRO_EDITOR DRC_CONSTR Update DRC consumes system memory and crashes allegro after approx 30 minutes
! b0 B# _! {: m: t771423 ALLEGRO_EDITOR SHAPE Shapes - Update to Smooth - Low on available memory please exit the program.
6 a# o* r! j! \' K771456 ALLEGRO_EDITOR EDIT_ETCH Allegro 16.3 crashes when using arrow keys g% j4 h8 u) ~; M
771719 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license.
' l! N/ S- t" n+ S& h/ ]771765 ALLEGRO_EDITOR PADS_IN PADS translation fails to translate symbol
& ?+ W! c! i G% V2 e% T771766 ALLEGRO_EDITOR DRC_CONSTR Moving certain components takes a long time on this board database.; |# i* X. i, X/ ^8 Q4 Q& Z& I
771815 SIP_LAYOUT IO_PLANNER SiP OA co-design flow does not allow a save to the .sip file after modifications in IOP
4 r4 b* r. E4 {" H7 s- e773072 SIP_LAYOUT ASSY_RULE_CHECK wire to wire same profile
- Y& _+ f) L; M6 p; W0 Y773126 CONSTRAINT_MGR UI_FORMS Constraint Manager "Value Filtering" for Topology Schedule is missing TEMPLATE and "UserDefined"5 l3 m/ J5 B8 S+ B
773179 ALLEGRO_EDITOR PAD_EDITOR pad_designer crashed when attemting to delete internal name layer.
$ c/ X& m- z: o9 b; H) ~# s773229 ALLEGRO_EDITOR OTHER Netrev never end importing netlist generated from Capture CIS
) c, v. ~# a7 \8 } p773329 ALLEGRO_EDITOR MANUFACT Allegro closes when performing a Linear dimensioning and then selecting the undo icon./ `% ^- H2 B7 R8 o% D0 o
773483 ALLEGRO_EDITOR MODULES place module problem
: ]5 Q0 g! Q. J+ L774036 ALLEGRO_EDITOR INTERACTIV Rats not shown after move->mirror command4 @7 o9 T& H. J# u
774170 ALLEGRO_EDITOR DATABASE DBDOCTOR fixes Error but it reappears and Artwork fails1 P' W, E* l q% j, I
774602 SCM OTHER ASA crash while working with hierarchy
4 ?$ r" k) }# q# d0 F' _, S774643 CONCEPT_HDL CORE DEHDL crash on edit of attributes/ t6 K5 H: B1 y, d" D
775201 ALLEGRO_EDITOR SKILL Color palette can only be changed one time using skill commands
' L0 B; t" H8 f# R; ]3 m' u775815 SIP_LAYOUT WIREBOND Unused wire profile once purged using wire profile editor are still available in CM and Color dialog
! P2 u; o3 E1 M, F/ L( D775826 SIP_LAYOUT WIREBOND Cannot change the Wire Profiles on the wirebonds in this design
; w+ q& D/ z( H5 Q775842 SIP_LAYOUT WIZARDS Die text in wizard is changing DIE location when origin set in DIE text file is other than 0, 0 |2 C, y% a, x* H5 R4 T1 x
d: g. @# [2 i: q. ]DATE: 04-23-2010 HOTFIX VERSION: 007
1 @( X( i4 P @5 f2 Y0 K===================================================================================================================================
$ r$ V9 c- E2 K' Y! q# kCCRID PRODUCT PRODUCTLEVEL2 TITLE
! d6 @7 Z0 U' Y H/ r. X===================================================================================================================================" u/ E% u: D3 e P
721859 ALLEGRO_EDITOR OTHER update shape to smooth creates tmp file on remote file server working dir why?
% G. W8 A" g! l' V740201 SPECCTRA_MENT_ IMPORT Wrong stackup order after translating from mbs2sp
! V6 R! M N& {$ Z744797 SIP_LAYOUT OTHER Cannot Copy a connector (IO) symbol in APD and SiP tools
' O) N3 F* I. C$ V) |747831 CIS CONFIGURATION There is a delay of 5 to 10 mins in opening SQL database in V16.2 and V16.3. It is fine in V16.0.2 O+ l4 q1 Z2 T
747848 CIS CONFIGURATION Unable to configure CIS with Oracle database due to Capture crash.9 t' M1 m0 L. i* A b' M
751372 CAPTURE OTHER Copy / Paste Issue in capture 16.3
5 P# d6 W( a1 f2 k7 `757434 ALLEGRO_EDITOR MODULES Allegro hangs the board file after creating Placement Replicate circuit.. u6 G7 j; H6 B, m; |* t+ B
759906 CIS PART_MANAGER Property copy from one to several parts doesn't work
/ x7 l) ?$ [! l! r8 {; i: \760154 PSPICE NETLISTER Model parameter (Tj) is not affecting Smoke Analysis result8 ?( F, B8 x l" S; X
761177 CIS OTHER Error Message - Memory exhausted
. k( ]# B h2 T; c7 x, g6 |0 Q762602 CIS EXPLORE_DATABASE CIS doesn't open datasheet for parts if it is not stored at default Capture location.
9 A% c% @: K: c' o$ k2 b( N763677 APD EDIT_ETCH The "Via to Via Line Fattening" tool is inconsistent in which clines are changed.8 l# M; T2 Z: X) P& _2 v" c) E9 U
763715 CAPTURE NETLIST_OTHER A long pin name gets truncated upto 31 characters when the wirelist is created.
7 q0 K" Q3 R9 \! ~7 y& d' b/ u763878 CONSTRAINT_MGR DATABASE Why Pinpairs disappear after closing Constraint Manager?
' r9 x# ?" C2 S& h( `764020 CAPTURE NETLISTS Usernetl.dll has changed between 16.2 and 16.30 J/ M, @8 G k3 V
764101 APD EDIT_ETCH Perpendicular routing through a Region does not work when the region segment is drawn at an angle.
# L# f# S, i7 F5 i% Q0 ^764200 ALLEGRO_EDITOR DRC_CONSTR Via at smd fit drc on a via that is placed fully inside the padstack having custom pad
+ X q+ ^8 }, W% i( @764903 PSPICE ENVIRONMENT 'Run in Resume Mode' does not work in SPB 16.3 ^" X2 q5 \) e' p' I3 b5 v3 H
765206 F2B PACKAGERXL Unable to feedback subsequent pin swaps from Allegro2 N, t0 ^$ e" P i8 N( q) ]
765319 APD DRC_CONSTRAINTS Identical Constraints in Performance Advisor question
5 h; v( t1 n H1 ~/ d$ B8 c765541 SIP_LAYOUT SHAPE Set via oversize value to 3 in dynamic shape instance parameters will make overlap shape.' M. W: U+ X: x3 r
766147 APD EDIT_ETCH Resize/Respace Diff Pairs does not work on 45 and off angle
% K/ F8 u& B$ H( d766337 SIG_INTEGRITY GEOMETRY_EXTRACT Geometry of Via model Extracted from board file is not identical to Original Via geometry design" `7 j* y. w/ o4 x0 ?6 P0 M
766443 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd in 16.3
' Y3 T. ]( o8 y0 [9 g8 C5 k766581 CIS CONFIGURATION In 16.3 capture.exe remains memory-resident after exit3 [$ ~, `. f, [( e
767161 ALLEGRO_EDITOR SHAPE The behavior of Add Fillet command is different by Hotfix version.2 t! n0 X) q; `; ]+ `) s3 z' r
767217 SIP_LAYOUT IMPORT_DATA The Die-Text In wizard and it is crashing on the "Finish" step.
% b. B! s) b) W7 | X767598 SIP_LAYOUT WIREBOND Can't wirebond SIP designs as it just hangs.
5 B. D) b, ^$ _767832 ALLEGRO_EDITOR DRC_CONSTR Reducing Design Accuracy updates Physical Diffpair constraints wrongly
" i1 s4 o2 B7 L$ z9 {/ z; C768822 ALLEGRO_EDITOR SKILL axlSetParam return value is divided by 10 to the power of the design accuracy.: D9 b, Z4 U! ]+ L1 a. R6 x
769150 CIS PART_MANAGER Update All part Status on a group changes “Do Not Stuff” status to “Stuffed” in V61.3_ISR_5.9 F) G$ e; R# f0 R2 K
0 E. r$ _1 G* P$ e4 V+ ]: J+ ?1 P
DATE: 04-09-2010 HOTFIX VERSION: 006
5 G" ]4 F J- ]6 f8 [/ _===================================================================================================================================
7 Y) ~' ~4 z e: O) m: ICCRID PRODUCT PRODUCTLEVEL2 TITLE
; E0 n3 H" {4 g" p8 w V===================================================================================================================================
2 R+ b- S+ b+ g5 G, F( Q745241 CONSTRAINT_MGR TECHFILE Importing a tcf file automatically enables On-Line DRC.; _% E- }) u1 g# A$ E$ M; B) W) U
752587 ALLEGRO_EDITOR PLACEMENT Uppercase File name(XX.mdd) for Placement replicate update on Linux.' L' F& a% n0 f7 e
753626 CONCEPT_HDL CORE newgenasym error while saving the hierarchical block symbol- y5 v3 V$ \! o% k* f9 K
753894 CAPTURE OTHER Case sensitive version control S/W# H9 `$ u/ C1 A. t
754487 RF_PCB OTHER Various asymmetrical clearance problems uncovered - calculation issues?) e O q/ {1 v a' I8 Z
758272 CONSTRAINT_MGR UI_FORMS Entering values on the Min/Max Propagation Delays worksheet hangs the application.
2 X5 c( \5 S) ~% g7 \0 i758911 PSPICE PROBE Pspice crashes while exporting probe data using our sample project
0 \( n p0 J3 |7 Y0 h% J9 n) [) t759871 CAPTURE PROPERTY_EDITOR Save option in Right Mouse Click on property editor of nets doesn't saves all the changes.$ m1 z; [% o4 y
759890 SPECCTRA ROUTE Specctra autorouter ignoring prerouted nets9 c# B- l F" R& ?' _- |
760067 ALLEGRO_EDITOR SHAPE Dynamic Shape not getting filled on board with odd angle placement and routing
: m4 |1 P" x0 X5 E" n( V) F5 z760284 CONCEPT_HDL CORE Update Sheet Variables turns of the grid
" s& \+ v( J" C: z0 {0 M D9 l' k760480 MODEL_INTEGRIT OTHER Message open clipboard failed when trying to open the rename/reorder dialog in Model Integrity$ R4 U+ \0 ]1 s7 `
760667 ALLEGRO_EDITOR PADS_IN The pads_in.exe translate incorrect drill shape from PADS 2005 ascii database.& E+ Z4 Y$ o% u6 ^) O& R3 t
760741 ALLEGRO_EDITOR MENTOR mbs2brd does not work in 16.3 but works in 16.2
' c. p k! Z" m7 Q! @. B: e% c760810 CONSTRAINT_MGR INTERACTIV Deleting Region Deletes NCCs
' T7 D6 V+ N( S- \. h/ Y" R761114 PSPICE PROBE Refresh issue in Display > Cursor window4 M1 P! m. Z% U
761180 ALLEGRO_EDITOR DRC_CONSTR Via_at_smd not working for custom shaped padstacks.$ W/ D2 x" Q- b% [
761305 SPIF OTHER Allegro crash when seleting any of the Route - PCB Router - submenu items.
5 n7 M. E1 P) I0 f/ a& F! R6 s761376 ALLEGRO_EDITOR PAD_EDITOR Wizard_Template_Path is not considered for symbol template look-up ?
: A; c2 t* o" T0 a; I. C2 U, p4 F761416 ALLEGRO_EDITOR DATABASE Allegro crash on chaning the subclass for group of clines
! f6 i. S% u& u$ q- r) E% g761492 ALLEGRO_EDITOR SKILL about axlTransformObject function4 ^: Y" F% \, ]. M' p( B! s
761518 F2B PACKAGERXL about mismatch library path between cds.lib and actual
& s, K; [2 m" T- P, N. M1 m$ I761737 ALLEGRO_EDITOR OTHER Running Dbdoctor after executing Skill is giving symbol fit error for the .dra file5 o# G" `( |! [# R
762155 ALLEGRO_EDITOR SYMBOL Updating a symbol changes the netname of the cline resulting in drcs.
. }8 U( _1 L3 i762181 ALLEGRO_EDITOR OTHER Allegro netrev crashes for long device name in PST* files
2 i0 K' c1 \0 i) z762316 ALLEGRO_EDITOR MANUFACT Allegro disappears on Adding dimensions for the symbol file: D" y! t; m& |, I ?' h: y( N
762792 ALLEGRO_EDITOR PADS_IN PADS_IN fails for SPB 16.3
s7 ~9 F, }% `9 e763108 ALLEGRO_EDITOR SHAPE Z-copy shape create an error like VOID boundary may not cross itself4 E/ k& Y1 N1 B
763134 SIG_INTEGRITY SIMULATION Bit 7 of a simulation is out of sync with rest of bus. It should be the same for all bus values.
* s+ A0 |( y6 d763149 CIS GEN_BOM CIS BOM in V16.3 is not correct if database has Quantity field and its value is 0.
/ R) h+ I: }" t763296 ALLEGRO_EDITOR REFRESH The error was happened while doing the SUM* N7 d! {( K! @
763303 ALLEGRO_EDITOR OTHER SMD Jumper has a problem while using the Add Jumper) Q* c3 P" T0 L9 Y( l
763315 ALLEGRO_EDITOR PADS_IN pads_in got error message WARNING ERROR(SPMHDB-205)
. m; O" q1 K& N' }) k763354 ALLEGRO_EDITOR PADS_IN Auto suppress redundant shape while using pads_in translator0 e3 [, X# h' L* {' n% B; O
763428 ALLEGRO_EDITOR PADS_IN enhance pads_in.exe translate spacing and physical rule into Allegro.9 _: B4 E: K" W+ d. O
763446 ALLEGRO_EDITOR REPORTS missing fillet is reporting pad without drill
5 g' q' k8 [, W0 s" [* t763448 ALLEGRO_EDITOR DRC_CONSTR Performance advisor shows Cset as unused nets when it is assigned to Diff pairs or xnets.8 E, u7 ^( i V
763586 ALLEGRO_EDITOR DATABASE Allegro rounds off the value after decimal in CM
" D% M9 e: e9 ~/ } D" e& N+ \764077 CONCEPT_HDL CHECKPLUS The output predicate in the Graphical environment is not always returning the pin object for an output pin.3 p# S! A3 j! i0 {5 e8 H" ^
, |' X) Q% `1 y: K
DATE: 03-26-2010 HOTFIX VERSION: 005
* P. r% M2 [! y2 s+ S===================================================================================================================================
8 D5 d1 s3 C9 U+ DCCRID PRODUCT PRODUCTLEVEL2 TITLE
$ B! ~/ d' }) ]) g3 Z- K0 g===================================================================================================================================
5 T5 W2 l! h3 y599819 SIP_LAYOUT 3D_VIEWER display soldermask by default in the 3d viewer2 ^) J5 r, ]7 f- s/ f
735992 CONCEPT_HDL CORE Create Test Schematic does not use the correct package type4 I& J3 j2 ?9 K& k" L Y/ _
743787 SIG_EXPLORER OTHER 16.3 SigXP crash if sigxp.run created by previous version exist.; {& B$ q/ T4 c$ u4 D8 ]
746320 CAPTURE NETLIST_ALLEGRO Remove Semi-colon from invalid pin-name check during netlisting. Q0 i% s: ^0 l( _ p0 I
746444 ALLEGRO_EDITOR OTHER show element fails to display info on a via if it is in a module.
# g: R5 U1 P7 ]; n/ j+ W746726 SIG_INTEGRITY SIGWAVE Save As and Open Dialogs open in last saved directory
: ~) t: F5 T& F3 \2 [$ j750080 CAPTURE NETLIST_ALLEGRO Improve error message ERROR(SPCODD-390)
# s5 l( }; K- M. G750606 SIP_LAYOUT ASSY_RULE_CHECK Wire to BF same profile check
. P. `8 ?$ a' u2 y0 E751492 CAPTURE FPGA Option to swap the pin-numbers rather than their locations in the Schematic after back-annotation. r# s5 I) j/ G" t# l
753834 CIS LINK_DATABASE_PA unable to link multiple database part
" G- \) }+ x( p753990 F2B PACKAGERXL Delay in opening the subdesign tab in the Export Physical setup in SPB 16.3; G# {2 a' k z2 x
754328 LAYOUT TRANSLATORS L2A gives error Subclass name TOP not valid Allegro subcls with s029 hotfix! y( O/ M9 @' t; I0 ], W
754434 CONSTRAINT_MGR OTHER allegro crashes when deleting matched group
1 C$ z4 Y; e p* W9 U2 M755111 ALLEGRO_EDITOR INTERACTIV "ALT_SYMBOLS_HARD TRUE" property does not work when I mirrored symbol using move command in 16.3.
8 g0 ^" K9 i% m& R756131 PSPICE SIMULATOR Capture crashes while re-running simulation
8 i; `7 h7 Z$ o4 G) O7 j2 `& _756148 PSPICE PROBE Zoom Area in Probe Window does not work for digital signal in SPB163
+ F4 ]0 P* \3 o9 u1 K4 {4 @756169 SIG_EXPLORER OTHER Signal Explorer crashing due to sigsimcntl.dat, }1 a8 K) o4 o6 q7 Y+ P/ ~
756176 PSPICE PROBE Trace color is wrongly interpreted in PSpice probe window.* F( W, p5 ]" O" \/ Z3 c" m
756224 SIG_INTEGRITY SIMULATION Simulation aborts reporting that VIA models have changed8 |' k1 g9 g, Y7 R6 ?; e! E
756281 ALLEGRO_EDITOR OTHER Why *.sav file cannot be recovered from PCB Editor utilities?
" n# t' v! f' `5 I# k, F756673 SIP_LAYOUT ASSY_RULE_CHECK Running ADRC Metal to metal checks causes false X-D DRCs, cannot clear them and trying crashes the tool
2 c* U7 W; w. G: J5 S756918 ALLEGRO_EDITOR OTHER Allegro angular dimensions working incorrect in 16.33 M" y6 @5 Z# A. V1 c" w9 X
756932 ALLEGRO_EDITOR CREATE_SYM Create symbol fails with error duplicate pin number) K3 |& W1 q' U+ Z, ^' p
756976 ALLEGRO_EDITOR SKILL axlChangeWidth always return nil in Allegro version 16.3
+ ?+ _, J, R% j1 c* v) t( v% p757000 PSPICE NETLISTER Incorrect Hierarchical Format Netlist created9 L! ]/ M# n- ], w: n6 @. h$ U
757406 APD OTHER Implement Segment over void features in APD L% |1 x4 o" o/ C5 Z
757624 SIG_EXPLORER OTHER Sigxp runtime error when simulation is run and exit without saving the topology# M4 v$ [% {6 T. u5 F
757820 ALLEGRO_EDITOR SHAPE Shape does not void to hole if there is no pad( [3 _1 u3 Y: Q( ]5 U, Z
758009 ALLEGRO_EDITOR OTHER Export > Library (MECH_SYM) adds a new subclass NCROUTE_PATH, data moved from one subclass to another.. N7 }- K2 [1 _
758022 CAPTURE DRC Capture crash while running DRC with “Run Physical Rules” checkbox.! Z. w, S F: }) e- I
758190 ALLEGRO_EDITOR PAD_EDITOR PCB Editor crashing on pin move in this design" \6 j/ j! r) @6 y* k
758374 F2B DESIGNVARI Problem with Mechanical part in Variant Editor
, _" K/ W/ U) M, y9 k758471 SIG_INTEGRITY OTHER Differential impedance does not change on changing the etch effect values.
! `8 _, a+ X0 b( z! M A" t758490 CIS CRYSTAL_REPORTS Different crystal report output in 16.3 than from 16.2
2 q- H9 v" W+ s0 Q" K758498 CAPTURE NETLISTS PCB Editor netlister hangs/ E& }" X! l9 Q# Q; `8 Z
758584 APD SHAPE Shape not voiding all elements6 K2 J- I" V! |7 s @& }
758886 ALLEGRO_EDITOR REPORTS Total number of nets is wrong into Testprep Report! L% M# F P3 X, q
759146 ALLEGRO_EDITOR SKILL The title is not displayed in the form by the version.
. ]6 _, W+ i3 }) w8 Q5 S# I759339 ALLEGRO_EDITOR ARTWORK artwork output fails by SPB16.x.
/ }: x3 K% l& l" l759591 ALLEGRO_EDITOR SKILL axlSetParam fails and does not round the value as indicated by the warning message& s2 }% b) u; @! c* ~7 b
759816 CONSTRAINT_MGR OTHER Allegro Hangs when double click on a Bus in CM! P" y5 Q$ c- l+ z0 e7 M% E1 w
759947 APD OTHER Need an a way to convert Lines into Clines9 U5 n% s+ s. L7 i, l
760353 ALLEGRO_EDITOR MANUFACT Allegro crashes and creates a .sav file on running the silkscreen command from Manufacture > Silkscreen
E& h5 G5 r' V8 V760432 ALLEGRO_EDITOR PARTITION Unable to remove fixed property after partition import
: Z- |9 K9 ^: S7 @7 R760638 ALLEGRO_EDITOR PADS_IN pads_in translator can not handle " PINPAIRGROUP ".
' t8 ]" N1 E0 h4 |5 _1 x760734 ALLEGRO_EDITOR SHAPE Different therma contacts on rotated partsl
2 R5 p0 u9 K6 g. {" U, ]761436 CAPTURE NETLIST_ALLEGRO SPCODD-53 Error when creating netlist with PACK_SHORT- s; U" u/ E9 n# W3 U2 N
" D7 V6 w. P0 e! S0 b; R0 P+ N/ u
DATE: 03-12-2010 HOTFIX VERSION: 004
2 h2 b, g8 x8 `1 u$ o# O6 g===================================================================================================================================( H7 B4 u/ G; d
CCRID PRODUCT PRODUCTLEVEL2 TITLE
7 V! i% f& f# o* f4 u( e===================================================================================================================================; n2 B! t# ]2 v7 a& `. j
689495 ALLEGRO_EDITOR DATABASE corrupt database7 x' [1 C& E' q/ l, \, l8 x% j
725944 SIG_INTEGRITY GEOMETRY_EXTRACT xtalk make allegro freeze and never give hands3 F, H) \$ z5 p" m9 y
732604 SIP_LAYOUT SHAPE Shape Issue - added shape will not clear around other elements.
6 Z# d/ Y% v+ i/ d5 N740106 PSPICE NETLISTER The "Enable PSpice AA Support for Legacy" option does not give the Desired Monte Carlo results* Q+ x, Z8 G! c5 f5 L7 i
744259 SCM UI Signal order reversed when a Vectored Signal name is renamed in reverse( o( F3 M+ v7 E( i( S4 \
745554 SIG_INTEGRITY GEOMETRY_EXTRACT Time to get Xtalk simulation result in 16.2 is lower than acceptable by comparing the time in 15.7% Q# s! S- e- y3 c- K7 o
745595 RF_PCB FE_IFF_IMPORT import iff RF_PCB give an empty block$ F9 R' W; @/ h7 _
747133 CAPTURE STABILITY ERROR [DSM0006] Unable to save
6 K8 {& D/ p8 ?& J747679 CAPTURE STABILITY Trying to Save the Design in 16.2 format gives DSM0006 Error and crashes Capture
" |6 E1 ?$ T; m7 Y% P( ~750460 CIS FOOTPRINT_VIEW 3D footprint viewer doesn't shows the footprints" k2 v7 X4 U( @+ C" k
750777 SIG_INTEGRITY OTHER Trace impedance showing wrong- U+ W. `% |, c* @! N
751424 ALLEGRO_EDITOR DRC_CONSTR Unexpacted DRC for Shape to Route Keepout
% g3 t* m% K! ^2 @: C: |751897 SIP_LAYOUT SPECCTRA_IF Radial Router crashing SiP tool
+ j+ Y [* i7 z: f+ u: E6 I752029 SCM OTHER Cross probing not working between SCM and Allegro Editor in Linux Environment
9 z5 J7 A0 `4 _ l752450 APD PADSTACK_EDITOR APD crashes when selecting a User Definable Mask Layers.9 `& s5 F% p% _% j' K1 z0 ^
752581 PSPICE PROBE Pspice probe window crash( D" Q) q" u, R4 ?
752709 ALLEGRO_EDITOR PLOTTING Sheet content doesnot plots title block
4 [* H2 ]% H, [# y, V% T9 E752908 ALLEGRO_EDITOR INTERFACES Output from Export > DXF shows one instance of a via on the wrong layer r5 v* D8 k, y
753226 ALLEGRO_EDITOR OTHER File > Change Editor doesn't shows the default Product Options. s, V; H' O& k8 U u
753622 ALLEGRO_EDITOR GRAPHICS Enahnce capture image command to default the save as location to working dir* h1 f0 _ h4 U( l
753773 APD WIREBOND Requesting the option to set the diameter of the default WB_TACKPOINT power ring pad." x1 A B1 K! A! O
753778 APD IMPORT_DATA Import NA2 displays the design momentarily and then crashes5 R* D* X; r/ _- J$ T+ V5 W0 m
753866 SIG_INTEGRITY OTHER about Select by Polygon after move command9 ], T9 {3 A1 j5 q7 {) \7 O0 k4 L
753958 CAPTURE OTHER Capture V16.3 is extremely slow while edting schematics of design placed on network drive via VPN.
8 e; p' _' w! B2 U" v$ y, z7 X, E754050 ALLEGRO_EDITOR UI_FORMS Why show element window disappears when scriptmode is set invisible
* G' U/ O5 N% q% a E754143 SIP_LAYOUT OTHER SiP Package Design Integrity - running Extra Cline segments generates report without Layer number5 N7 K) a; h0 c3 [0 ~7 w
754327 ALLEGRO_EDITOR OTHER Rename Sub Class is not working as desired." `- n$ ~) ^) b- p
754364 ALLEGRO_EDITOR PLACEMENT Crash when applying placement replication
; G S. ?1 K5 Y! q! a" E754462 ALLEGRO_EDITOR SHAPE Allegro circular dynamic shape fails to fill& h/ L; l- S2 K1 v# c, I- ^) k
754819 ALLEGRO_EDITOR OTHER Create details shows wrong graphics for filled curves
# a/ ?2 V, g; j* r$ V0 `+ k755176 ALLEGRO_EDITOR PADS_IN Pads translation succeeds in v16.2 but fails in v16.3 on this ASCII file" \# Y9 J* e! o3 b O/ g6 D
755256 ALLEGRO_EDITOR OTHER Attached script is crashing the designs in v16.3
6 u6 n) T% S' Y* p( `755610 CONCEPT_HDL CREFER Cref hyper links does not work for signals where number "0" used to define the zone for page border' V: ~% q" T' d- o
755787 ALLEGRO_EDITOR EDIT_ETCH crash using resize_respace_dp command
0 \* J/ w' r! L" C8 c2 |8 t( e755881 ALLEGRO_EDITOR DATABASE Swap component crashes application2 H6 ?/ ~6 {/ Y G; c+ T
756092 CAPTURE PROPERTY_EDITOR property editor flickers and loops on value edits: p6 s# P5 V, Z3 r
1 H6 y2 k6 R8 HDATE: 02-23-2010 HOTFIX VERSION: 0034 U: e0 F2 _! X# c% M
===================================================================================================================================' X4 A' K! M' [ W; U
CCRID PRODUCT PRODUCTLEVEL2 TITLE; n. G$ h( Z. x0 L) t' c
===================================================================================================================================; n0 a ?" d/ L1 s
263504 CONCEPT_HDL CHECKPLUS Checkplus fails to run if crefrpt exists in the design
) _. g c6 A% w726836 ALLEGRO_EDITOR SKILL axlGeo2Str() and axlGeoEqual() return different results e/ e: p6 w5 \3 [& D8 Z
730820 SIP_LAYOUT PADSTACK_EDITOR Changing the Via diameter will cause the SiP tool to crash
5 _( y+ S: [$ v. c! Z8 g735193 CAPTURE FONTS Pin_names and Pin_numbers get convertred into darkened blocks in ‘Zoom to all’ view in V16.2.
" Y5 {' F0 z% x, R* H/ n737307 SIG_INTEGRITY GEOMETRY_EXTRACT differential pair extraction to sigxp fails to extract coupled sparam via models
, s- S- L/ T0 B) X+ R740936 ALLEGRO_EDITOR SYMBOL Confusing error message during Create Symbol
( r9 i% l6 v8 L- H744191 ALLEGRO_EDITOR EDIT_ETCH Arc routing enhancement: K& d: r: c0 ~
744497 ALLEGRO_EDITOR INTERACTIV PCB Editor Crashes with Data Customization Feature$ K, L7 D5 Y. V$ z/ D! a
746572 ALLEGRO_EDITOR DATABASE Reoccuring error in attribute pointer to attribute invalid on dra.% r" b* g f& a6 w! @/ G8 Z
746978 SIG_INTEGRITY SIGWAVE 2 licenses were used for SigXP and SigWave.6 f( H( l# N4 B' U% y- q" \
747219 SIP_LAYOUT SHAPE Dynamic Filleting not working with odd angles' j( d4 o7 I- M5 X G1 {0 m; [& G
747593 ALLEGRO_EDITOR PADS_IN Some RULE_SETS cause the PADS translation to fail. M7 o/ d) [; J: D$ } J
747746 ALLEGRO_EDITOR OTHER Request for more detail in downrev.log file" K6 e: q/ r7 u( L6 a
748033 GRE IFP_INTERACTIVE Enhancement in GRE where Show Element on Bundleshould show the total number of nets that are part of the bundle# i2 T' M8 R- c! k
748333 ALLEGRO_EDITOR OTHER place by schematic page number not showing pages correctly
9 T4 w4 u- l+ k0 v, K" q748375 ALLEGRO_EDITOR MANUFACT gloss - line smoothing causes crash
8 m& K* u5 g$ U5 L2 E3 g748818 ALLEGRO_EDITOR DRC_CONSTR Undesired DRCs shown in allegro 16.3 while moving component and the same are removed by update DRC
5 w. Y; `% K. \6 Y! ]! g' d w6 @748865 CONSTRAINT_MGR OTHER Allegro 16.3 slow to move component with CM open
9 j4 A( v+ l$ Z# D7 B749009 APD WIREBOND a part of function of the finger alinement doesn't work
2 {. B& R/ X8 @& W( h749162 SIG_EXPLORER INTERACTIV Unable to proceed after RMB > Preference > Cancel
; M0 C0 Z9 Y* g9 V+ t749307 ALLEGRO_EDITOR MENTOR mbs2brd fails with error VIF_Allegro_Write
/ a3 }" r" h' V$ V7 I: G. m749435 CIS DESIGN_VARIANT Cannot create variant part in 16.3: c. h4 t& u+ N
749854 APD PADSTACK_EDITOR The value of user-defined mask layer is not retained in the design.& R A8 }8 \" ?- F1 \
749891 ALLEGRO_EDITOR PARTITION Unable to delete existing partitions7 ~" D/ l0 F+ }8 k: o/ H& p+ l
749949 SIG_EXPLORER EXTRACTTOP A Topology extraction fails using APD and SiP series with the latest hotfix(SPB16.30.001).
# c* z8 R* f) o; a- d2 X- A750008 CAPTURE NETLIST_ALLEGRO Netlist different in SPB 16.3 and after installing SPB 16.3 hotfix 1
! d3 e; c: A& {, q750591 ALLEGRO_EDITOR DATABASE Analyze diff pair object fails to display uncopled lenght values.
8 ]- ? w0 G& R* W, U' Y750888 SPECCTRA ROUTE specctra is crashing while routing
6 t. t" q# D6 W1 e Q1 ~751204 F2B DESIGNVARI Design difference crashes while reading funcview9 d! ^% v$ \3 u& c
751398 ALLEGRO_EDITOR OTHER Allegro Crash when Edit is selected in Setup > Outline > Room outline3 b4 D' X& ?" b( P
751578 ALLEGRO_EDITOR PADS_IN pads_in hangs while conversion% a0 ]; Z0 Y# C) l7 h, t
9 k! J9 c: V+ m; V, @5 F
DATE: 02-09-2010 HOTFIX VERSION: 002
9 b* P* }9 @" w" e4 s) u3 L===================================================================================================================================$ P5 q# [/ Q6 K& c" G
CCRID PRODUCT PRODUCTLEVEL2 TITLE
3 a1 j7 m+ G% U1 G d% c===================================================================================================================================
2 _+ S, z$ H* F- I527012 SIG_INTEGRITY IRDROP Severe Memory leak in IRDrop
+ w; U& H t) W* N' n623678 PCB_LIBRARIAN CORE PDV freezes when changing grid
3 S L% V) |2 @/ h1 _) q9 p672592 ALLEGRO_EDITOR SHAPE Shape does not void correctly untill a clearance oversize value is added
/ A5 |2 t7 |& E! z' p; M688062 PCB_LIBRARIAN CORE PDV Strange characters appear when copying text into Bus Arrows ( Text symbols)0 Y# |! n5 R" l8 P$ b
710170 SIG_INTEGRITY IRDROP Run IR Drop even if all components on the net are not placed.
6 c# X9 @8 c7 k& e7 m710174 SIG_INTEGRITY IRDROP Audit function for IR Drop.
$ Q" @2 d! H/ @% A5 E+ k726833 PSPICE DEHDL Modify the methodology for migrating 15.7 and 16.2 users of ConceptPSpice
9 Z7 o5 F( s) z: J. }730717 SCM UI Unable to delete a zero connection signal in SLP which has a pull-up2 `6 t1 \. e( {
731017 ALLEGRO_EDITOR DRC_CONSTR DRC's show out of date when artwork is run
! b S$ a" w G9 e) @; p6 m732145 CONCEPT_HDL OTHER Incorrectly generated VHDL netlist
; N) ?, M" c: i/ G740123 ALLEGRO_EDITOR GRAPHICS Capture Image command fillin missing from jrl and script files9 U7 E) F# @8 p; ?" u
740278 ALLEGRO_EDITOR OTHER Jumper fucntion for Single Side PCB Design
1 ^. c5 e9 P( q: e% V. ~740656 ALLEGRO_EDITOR GRAPHICS Can we place custdatatips.cdt file on a site level for SPB16.3
8 [& c5 V' S0 `& z' s% e741222 CONCEPT_HDL CORE Replace command (in Windows mode) causes crash" i) G$ B6 Z$ s8 O
742389 ALLEGRO_EDITOR EDIT_ETCH Change or add message when using Countour route# J+ K5 x& o6 i5 G8 y# f; _1 t
743275 APD DATABASE With DRC enabled, this design seg faults in axldbid.c (solaris only). DRC update takes orders of magnitude longer on sun4 a) G# Q! S5 r
743623 F2B PACKAGERXL Pxl error when using pack_ignore on reuse blocks% }% \" C$ u( t/ y9 n- R( Y, i
744348 F2B BOM PART_NAME column getting word wrapped inspite of sufficient space in the HTML BOM report.4 P& \8 {, X: T. h3 U
745062 CONSTRAINT_MGR OTHER import techfile does not add new layers in cross section
( R! t) ^6 [5 a8 I# ?0 L3 O745148 ALLEGRO_EDITOR GRAPHICS Allegro ptf driven HEIGHT value not pushed into 3D Viewer
' a8 W' ~3 `) ?$ G4 e& K745301 ALLEGRO_EDITOR DATABASE Allegro 16.3 crsh on moving component
$ P# f4 V- L- Q3 ?% p/ F2 r* V3 o' C745518 ALLEGRO_EDITOR DRC_CONSTR DRCs not shown when "Enable Antipads as Route keepout is checked in"
2 a- Q) C7 n: ?; m! x& y745745 SIP_LAYOUT WIZARDS Die Text In changing the pin names on duplicates
f: B6 D! n& G$ K6 i6 h745785 CONSTRAINT_MGR UI_FORMS Unnecessary window opens when the cell in PCSet By layer worksheet was clicked.3 Z! H) f! W [
746002 CONCEPT_HDL CREFER Could not find pc.db in the root design+ ], ?+ @! O0 h! D; T/ z
746010 CONSTRAINT_MGR SCHEM_FTB Updating the brd file using the "Import Changes Only" option overwrites the modified constraints in
; T, Q: [* E4 G9 N0 f; s! s& I746080 CONSTRAINT_MGR OTHER Click Constraint Manager filter icons crash software( h8 [8 N: E6 C9 _1 J f5 C) O
746137 APD IMPORT_DATA Import > NA2 not transalating certain layers and padstack sizes! J0 x1 [! q2 z/ p x, }1 \
746370 ALLEGRO_EDITOR GRAPHICS Setting infinite_cursor_bug_nt variable flips mouse movement on flip design+ L9 E. V I$ ?* q
746519 CONCEPT_HDL CHECKPLUS CheckPlus the if statement is not seeing the True condition or the output predicate is not returning the True condition., W: z' W- d# r: \2 [4 T
746546 PCB_LIBRARIAN VERIFICATION con2con choosing incorrect PART_NAME in PTF File during verification
U- c {+ `8 `4 q8 d" O7 S, h746865 CONCEPT_HDL CORE Tool generated pspice net names in core concept design cause short with copy all.7 J4 k2 V, m+ v3 `
747636 SIP_RF OTHER RFSIP Layout RF Module Export chips & connectivity is not writing die attach method to chips file8 D- |2 ]- j% q' K
n7 d* g G$ L* r0 O) rDATE: 01-31-2010 HOTFIX VERSION: 0013 G- U$ F) L0 @: N
===================================================================================================================================
# U/ x3 a' [2 E6 ` f6 P' [$ @CCRID PRODUCT PRODUCTLEVEL2 TITLE
2 |2 t! S/ A7 N% d===================================================================================================================================2 C0 E( q* w5 D+ a2 ?
491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute: _/ L0 |/ f& y$ I) U: @
496910 CAPTURE NETLIST_ALLEGRO Inconsistent netlist creation
- `2 ^% O# b9 y/ ^5 L2 {3 m558783 PSPICE NETLISTER Why do Models with "awb*" prefix need wirte permissions to "*.ind" files?
! ?* ]( t7 o4 c643241 CAPTURE SCHEMATIC_EDITOR OrCAD crashed while replacing cache
' J. k7 o. S- A654292 ALLEGRO_EDITOR DATABASE Propagation Delay constraint behaves differently between 16.01 and 16.2& F& p3 ~( W8 N
662829 CONCEPT_HDL GLOBALCHANGE Global Update should honor property visibility settings in ppt_optionset
! ^% K8 e9 }1 b1 u( f0 U" x& N672718 SIP_LAYOUT EXPORT_DATA "Export>Symbol Spreadsheet" should export a .cvf not a .txt
" ?' q8 t$ g* Y `1 M0 S676233 CAPTURE NETLIST_ALLEGRO Cross probing stops working if design name has dots
- W, l; Q. r) m+ a% N678739 CONCEPT_HDL CONSTRAINT_MGR Manually added targets in matchgroups lost when reopen CM
) D5 {! @+ n$ F% P/ F690618 F2B BOM Write protected template.bom fails to write callouts
5 T5 D3 O! m3 ~/ u: \" Z700246 CIS LINK_DATABASE_PA Need option to update symbol always when linking part in CIS
% b/ W- [0 x- i3 `705393 CONCEPT_HDL CORE ConceptHDL crashes while switching to another hierarchy level under File > Plot Preview.
5 @" x: u( o: o5 y3 Z708634 ALLEGRO_EDITOR SHAPE Shapes getting incorrectly displayed in 16.2
2 ? d9 D m# J+ B8 }+ G708950 CONCEPT_HDL CORE Tool crashes while trying to change the text on the schematic using a text editor.2 Z% B% J0 E+ n1 L! s) t
709823 ALLEGRO_EDITOR OTHER Arcs not converted properly when upgrading symbols6 g+ R8 v. q: q8 K
713964 F2B PACKAGERXL Net property Probe_Number is getting changed during the packaging run4 d5 x3 v: o0 F' C& H( z: o
718119 F2B BOM Exclude the callout file name from the template.bom file
0 y" s( Y* Y3 f3 J4 i) {718496 SIG_INTEGRITY SIGWAVE Frequency at smith chart.$ v- O$ {0 i! ~
721422 CONCEPT_HDL CHECKPLUS Checkplus fails if "\\" character is used in the parameter list
4 S' A: {+ D4 K. W721788 SCM OTHER SCM unresponsive while closing out a Block without Saving
" N* D$ m& E; |5 E2 s- q721801 CONCEPT_HDL CORE Save As crashes DE HDL if an existing page is selected in the design! w8 n- U' A; F7 A# A+ _
722653 F2B PACKAGERXL Packaging does not complete/ I, q6 G, l) k n4 Y
725285 CONCEPT_HDL CORE nconcepthdl does not work same as concepthdl for same script.
6 ]0 n% F# _9 [& M( d- _& B: e' m725719 CONCEPT_HDL CORE wire pettern of Publish PDF# N9 I+ c. z6 E7 B
727062 CONCEPT_HDL CREFER Custom properties not visible for TOC symbol in schref_1 view H7 W) Q$ V7 |% r5 d& X2 K
727194 CAPTURE CORRUPT_DESIGN Random Capture crash# U _* i; e/ E; Q. A, y" o
727704 SCM PACKAGER ASA to PCB getting out of sync
; Y0 F, r9 H( x2 c, c9 f4 ~/ c3 Z6 I728066 CAPTURE NETLIST_ALLEGRO Allegro PCB Edtior net cannot be generated if PACK_SHORT is used0 G, R5 ~+ _" p4 d8 }8 j0 L
729214 CONCEPT_HDL CORE SHOW_PNN_SIGNAME directive used with Windows Mode gives crash" V1 B# A% I$ T5 L* |* K# d
730295 SIG_INTEGRITY OTHER Filled rectangle shapes not extracted properly
+ e" V: E) Z' L e2 ?# D731183 CIS QUERY_DATABASE CIS Query fails with ODBC Error for query (Price contains 29), k$ Q; ]' X% S% s; ?
732073 SIP_LAYOUT DXF_IF DXF_OUT generate an incorrect shape# k3 h2 Y/ K" O! d% E
732138 CONCEPT_HDL CORE Cannot change SI model assignments
% y j( P5 i0 }0 Q732216 ADW DBEDITOR dbeditor crashes doing copy-as-new into lib folder that has partially completed chips.prt file! R' X) B2 ]7 x/ |7 S
732249 SIG_INTEGRITY SIMULATION Probe sim with custom stimulus cause segmentation fault. Linux only.7 _0 Y; B' |* ~; j+ L7 i8 M
732847 ALLEGRO_EDITOR DRC_CONSTR Manual Void uses Shape to Pin constraint to void Holes
+ j- \; z2 S. q: Z. w( p# Z733261 FLOWS PROJMGR Project manager does not work with the Restricted User in client server environment
: a+ i/ ]* F# m& S733773 CONCEPT_HDL OTHER Syntax issues in DEHDL
9 A* B/ G, P3 G3 X734260 APD COLOR Why subclasses still remain visible even after global visibility is turned off.
4 F* a3 y+ b# M( d, a. X2 C734419 CONCEPT_HDL CORE Concept crashes in windows mode when netname is deleted on schematics generated by ASA" l3 k3 T3 C6 X1 i; s
734555 CONSTRAINT_MGR SCHEM_FTB Import Logic does not overwrite the Constraints
) J/ W9 O9 R8 r( ?0 A3 g1 a; C735290 CONCEPT_HDL OTHER Concept's PDF Publisher has issues.
" K5 y- E, u {" s. }: @/ |' }735892 CONCEPT_HDL CORE "Component Modify" changes visiblilty of Key properties
) x1 v6 u& M! i u% X" g. Z1 M$ w0 s735977 ALLEGRO_EDITOR MENTOR Mentor to Allegro translation fails without any error message
: s. R5 `% b2 [" B1 Y# Z736071 CONCEPT_HDL CORE Property visibility is not retained on the schematic instance when we modify the component on sch.
0 F& p: s% d) `; Y: ]; R736165 SIP_LAYOUT SCHEMATIC_FTB about error message of "schematic to layout"3 t" N( T+ y& Q! f/ V7 M/ E
736167 CONCEPT_HDL CORE HDL crashes when I select BGA symbol in Component Browser
4 F: O* [" J9 a5 a3 B Q) e736911 ALLEGRO_EDITOR SHAPE No DRC displayed when Place Bounds are edge to edge
c- i3 d! \5 Q) ~738035 ALLEGRO_EDITOR OTHER Measure function has different result between 15.7 and 16.2 version.
. K( [( K2 y, }, u( k) F738129 CONSTRAINT_MGR UI_FORMS Need Diffpair Constraints option in Analysis Modes Electrical Options with Performance license
, N6 Z+ s. D- r; I2 t3 A3 w" q738276 ALLEGRO_EDITOR PLACEMENT No feedback in console window when placing unfound components in Allgero 16.3
% g: r i% G) U) x* L4 W- i738366 ALLEGRO_EDITOR GRAPHICS 3d viewer not showing some connectors with mutliple place bounds correctly
' \* d, v2 ]. R738454 SIG_INTEGRITY FIELD_SOLVERS EMS2D extracts incorrect CPW to Trace spacing$ W' q$ T; Q. x, I( B: L
738578 ALLEGRO_EDITOR OTHER scriptmode +w doesnot work on Linux+ K+ a" T1 r' x4 b
738869 ALLEGRO_EDITOR OTHER Error msg when cds.lib contains missing SOFTINCLUDE; m. e( {9 R# t9 ]8 C3 ^8 b& p* k
739116 EMI SIMULATION At EMI simulation on SigXP an extra Sigwave form is launched.
5 ^% b# y% \5 B- H0 o! k: K739225 ALLEGRO_EDITOR GRAPHICS Ability to lock the 'Hide Pallette' option
; I( l. f/ G# @6 F739599 ALLEGRO_EDITOR DRC_CONSTR drc_errchk indic7 X) o; B0 {4 r1 y, p; C
739628 ALLEGRO_EDITOR SYMBOL Opening a symbol file is crashing allegro.
" }6 H Z6 K- Z5 _7 n739653 ALLEGRO_EDITOR SHAPE Shape created in 15.X .dra changes geometry when uprev'd to 16.X- r) ]' D; q9 q
739661 ALLEGRO_EDITOR OTHER Export netlist creates incorrect via_list syntax.0 y4 H7 d: I4 |, z2 k6 w
739872 ALLEGRO_EDITOR SKILL Crash while performing axlExtractToFile in 16.32 [+ _7 @! b! e% c- w e5 L' d' j
739934 SIG_INTEGRITY OTHER specctraquest crash on changing signal model
0 T4 d5 ?4 p; }+ M739937 MODEL_INTEGRIT PARSE zero valued estimated parasitics in ibis models
2 j0 q( {0 b7 M0 o1 N( B! M739942 ALLEGRO_EDITOR SHAPE zcopy xhatch shape creates oversize copy c9 u: a5 ?4 ~' u6 R
740133 ALLEGRO_EDITOR DRC_CONSTR Same net DRC Update from Analysis Modes runs forever.( i! L7 D0 }$ S" u* K( k
740281 ALLEGRO_EDITOR OTHER Jumper components where were placed in PCB disappeared
4 g7 j' r! V t- {740309 SIP_LAYOUT DIE_EDITOR Moving a die pad in DIE EDITOR on G69A_U1 causes the die pads to rotate 90 degrees from the design.* B% o. l% a' R$ m8 H
740399 ALLEGRO_EDITOR COLOR Cannot automatically load custom color palette in 16.2
$ z3 G7 q4 ]- r1 a: z% _; Y+ K741210 ALLEGRO_EDITOR DATABASE Edit >Move; spin creates 'connect record not found' message
9 e: S" u, @+ S0 E, s* v) a741307 ALLEGRO_EDITOR PADS_IN Shapes on some layers is not getting translated from PADS into Allegro. D1 L+ d3 g' O6 B6 h3 a) V
741313 ALLEGRO_EDITOR DRC_CONSTR Add connect slow in 16.3
K2 g: v9 b1 d$ T3 y* }/ ]741778 ALLEGRO_EDITOR COLOR Color pallete in 16.3 is not expanding when maximize dialog
& M8 M/ |" @ a$ ]1 C" S4 ^) U% D, A$ P/ n741910 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd
: r" L. H! O6 H) E& a: e1 j741939 ALLEGRO_EDITOR PADS_IN PADS to Allegro Translation fails or hangs.
4 ^+ O$ |) b5 Y7 ~3 F7 V741980 ALLEGRO_EDITOR PARTITION Import of parition does not import etch or vias.: w6 s; w G/ D" c3 Y
742676 ALLEGRO_EDITOR SKILL Tpoint cannot be moved by using skill.5 R7 R7 j Y5 {' H8 w) ^
743161 ALLEGRO_EDITOR SCHEM_FTB Netrev crashing when importing netlist into board file., E! z* g4 Y2 _8 u* l1 i! ^( Z8 s
743235 ALLEGRO_EDITOR PLACEMENT Allegro crashes when unmatching comp in placement replicate.
& T# z9 ~% ^4 i3 W- J743243 CONSTRAINT_MGR TECHFILE Closing CM destroys tcf values when they are set to locked using fObjectNOTReadOnly: u# ?( Y& K, V. b
743301 SIP_LAYOUT DIE_EDITOR Edit die command creates two extra die pads5 J2 _# F v4 W
743316 CONSTRAINT_MGR DATABASE With Allegro 16.3 Constraint manager takes to long to update
4 o1 G0 i P, F3 G743553 CONSTRAINT_MGR OTHER Net disappears if we cancel the line width edits in CM
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发表于 2012-1-11 21:45
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