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orcad capture CIS16.3导出网络表的问题

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发表于 2012-3-31 11:28 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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我画好原理图后可以导出网络表,但是在PCB板时我想按页布置元件,所以在原理图中把每一页都加上一个属性PAGE,再来导网络表就报错ERROR:netlist failed.这是什么原因0 t) M% W* p) B* W
session log
4 N! b( |( I+ D5 k9 s5 {Design Name:
& S: |$ ~- [: T2 T1 eE:\orcad BACKUP\MYPROJ\myproj.dsn
2 P. d% R. a" d# ?' O  oNetlist Directory:% N: S& X  R. N9 U' P$ }" u
E:\ORCAD BACKUP\MYPROJ9 L6 U! A, l7 E
Configuration File:
" V) v4 k( g, F; XE:\cadence\SPB_16.2\tools\capture\allegro.cfg
- T# G. L) B& r3 y# i2 L& T
3 S/ C! j" J. A0 i! @Spawning... "E:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\ORCAD BACKUP\MYPROJ\myproj.dsn" -n "E:\ORCAD BACKUP\MYPROJ" -c "E:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"- s9 o2 n: L8 M1 T" S( Q) T
#1 Warning [ALG0051] Pin "GND" is renamed to "GND#1" after substituting illegal characters in Package AUDIO_RJ , J6: SCHEMATIC1, OPA_BUF (360.68, 53.34).
6 w+ v0 d) f# d6 f1 H& {0 g, r#2 Warning [ALG0051] Pin "GND" is renamed to "GND#6" after substituting illegal characters in Package AUDIO_RJ , J6: SCHEMATIC1, OPA_BUF (360.68, 53.34).
" f1 z% S& f7 ?' N' B#3 Warning [ALG0016] Part Name "SW PUSHBUTTON-DPST_RESET_DSP-RESET" is renamed to "SW PUSHBUTTON-DPST_RESET_DSP-RE".
+ o1 B; h+ G- M8 d" e#4 Warning [ALG0016] Part Name "TMS320C6713GDP_BGA272DSP_TMS320C6713GDP" is renamed to "TMS320C6713GDP_BGA272DSP_TMS320".
6 c/ @- w3 p' b( d& s- l9 g#5 Error   [ALG0013] Conflicting values of following Component Instance properties found on different sections of U6.
: c# s# c3 O' S              PAGE
# J7 Y, n& F1 l& n0 w; G# q* i#6 Error   [ALG0013] Conflicting values of following Component Instance properties found on different sections of U6.
1 u( _5 m* s2 o' q, Y( t3 X0 ?              PAGE1 x( K0 y  ~8 M$ W& t; \4 D
#7 Aborting Netlisting... Please correct the above errors and retry.
4 m: r, s- r; {. j
) e" `+ k9 E1 a* T7 Z/ U8 S; |5 YExiting... "E:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\ORCAD BACKUP\MYPROJ\myproj.dsn" -n "E:\ORCAD BACKUP\MYPROJ" -c "E:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"/ v% T# U) @! t7 j) Y5 v" M

+ |/ U4 t  ^0 V1 m
' M1 D& U% p$ {1 x6 R' G( r*** Done ***
8 h7 ^5 ~9 J* d0 t8 b. F3 U
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