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allegro-DRC-错误代码
3 v, d$ e+ g) W; f1 v& N<DIV __1326040128187__="ev_1264270853" js-fs2? ztag nbw-blog fc11 fc05> * A$ F1 ] w& Z' X) `
DRC错误代码5 h6 X* B' z4 C) U% q" s$ J1 w
代码
- v& K& ]: i& g9 r1 [" B相关对象
0 Y2 H5 B' \; T3 v, d, Q说明
; D" I* r% }# C1 j5 x# d9 W单一字符代码
0 @/ S; K$ X3 K4 _* O; wL
( L. o: n O$ P; E7 v, _$ G
, d0 N8 S% {( d, M: O$ [Line 2 }3 n: t) y4 U
走线. w& y- Q4 h5 E) r2 b
P
: P& z& R, w' t % A/ Z P. R! n. ?6 |( h7 x
Pin
# \3 |- }/ [4 c3 R元件脚
; ?# w( ]: k& V, J& C# X0 uV
% P7 t9 z9 V3 a8 a$ K( o5 j
4 t, i" b" B7 g" E/ wVia
`, L/ E) P$ }% ~6 {* a5 T2 ]6 w贯穿孔- W+ W) l% K" d2 q8 g8 \
K
0 K5 s8 s# a _: @: T/ ]
) [4 y2 L( l. H7 w9 o! nKeep in/out
5 {( r, G0 C8 ]( l2 p允许区域/禁止区域
! B0 A5 u/ Q. |" ~8 d" ?9 MC
+ ], C7 b3 h- Y+ y
9 T. R4 H1 S, X& J1 XComponent , m9 m9 `4 {. N( k E0 x5 Z! v
元件层级
8 j4 C/ m& f# g }E5 F7 Q3 c/ s" t" N t& }
3 Q# V/ K3 C1 {- j% q% R) }1 FElectrical Constraint
7 x7 v. ]* O+ s( c! }电气约束+ T% p7 f* P- l3 i) I$ _
J
3 _9 @& k9 h0 ]
1 n; H* P( C5 F& JT-Junction
. P% { {* b4 [0 \, `呈现T形的走线3 i0 s4 _" g9 X" A; e0 [
I
% n9 _* ?7 l- Z' Q- M$ R 1 R5 N& p7 h: f' M3 T" f
Island Form
6 o* j3 s# R, }; ^/ l' i( E被Pin或Via围成的负片孤铜" t1 P* n! U4 x
# {, L: J: C- C" ?4 W
( y9 |' `3 j& N( j1 |错误代码前置码说明
@- T9 l g! A' p; V
4 ^4 Z( G; M1 K( y
2 b1 {- m( n: }$ X8 L/ p+ Z9 LW
+ }* { y! a& c 6 I3 y# K% P/ U
Wire # n8 Z9 \7 A! N Q) ~+ f) O
与走线相关的错误. V+ v/ E/ o9 X1 T
D; S: m8 \" n: a6 V( V9 q
0 X1 \( a+ z' MDesign $ l7 }8 t8 k+ x- P% R K
与整个电路板相关的错误 D" k. n' y* @; i
M# C1 R9 d# n7 Z2 V: O
: }" h4 Z x7 D/ |$ z$ E4 e( bSoldemask
/ |& S& d, C& `! s. o# `与防焊层相关的错误/ H/ I2 ]$ b9 ?9 |- Z2 A
+ T& P% s. g) l9 f/ J
/ W& @! u9 s2 F错误代码后置码说明6 t$ L" z8 |! n5 T" p! O, j
8 L* ^. n( s! k8 z2 M: I0 G 1 h) q, v" k2 N( \% q3 a3 ~8 {
S- u4 ~% @% U, x {6 h) ]
4 \5 C. Y' u' |$ ^Shape/Stub
5 u2 Y, |# B/ `1 g3 n+ }) \2 p+ Y W与走线层的Shape或分支相关的错误: S9 L+ v7 |$ h# g0 _
N: ?" V* E9 q* M x- N, u
* U" q6 b' @) [0 v) `0 }
Not Allowed / R' ~/ N; \2 s8 L# K% R* A
与不允许的设置相关的错误
u. v( V* f8 xW
- {* Y. l3 X, l ! f p5 @& ?. k
Width 8 o# W, Q* T* S& u, d- n
与宽度相关的错误2 y O0 o, j- O1 I1 F$ g' \
, Q# {( O( @# q* S' v 4 J. y3 w+ k( A* Z& X
双字符错误代码1 M5 F( D- v7 ^ ~$ o+ M
' \, x6 N9 Y0 e6 j0 {. b3 r2 q
. f' s8 q* f; l8 V6 S. `BB1 K- v W; d7 ~- O
: `( E- }* H3 @5 P% `
Bondpad to Bondpad ) v1 n' g3 h1 Z* ]
Bondpad之间的错误/ q+ @1 g; S5 k- B
BL
: Y* z' o. ~- C+ r U# {- z! \ 8 \6 g! n. x2 g7 d! B
Bondpad to Line 5 e0 o& r9 H) P% {4 W7 B. o8 V! T
Bondpad与Line之间的错误" @3 [# D7 e7 _+ S
BS' }. O4 Y; j+ F( p+ ]& |3 t
" z% F' _& [* \Bondpad to Shape
$ I, u+ i8 \; i% MBondpad与Shape 之间的错误
% L0 f9 ~) H% c2 p' n: Q) DCC
& e. w! A- w, a+ N8 ]
. b4 ^+ ] e: b# VPackage to Package . A, ^1 [3 C9 G" g# D; n' {
Package之间的 Spacing 错误. I% E6 M7 F7 J+ g3 r
9 w4 v( b" E/ s! BSymbol Soldermask to Symbol
+ V- H/ D/ e" Z. R- r6 GSoldermask零件防焊层之间的Spacing 错误
4 R9 _& W1 c( t& z5 xDF0 g! k5 U: j& Z4 l1 E5 Z& r' |: K
4 L) ?5 Z0 E# WDifferential Pair Length Tolerance $ E3 A# l8 _, ^% `) m! a
差分对走线的长度误差过长2 n0 p! r' g1 P2 `' V
& d- {" `4 w6 t) E0 A FDifferential Pair Primary Max Separation ; T2 o& W3 i) R+ ?
差分对走线的主要距离太大4 X1 W5 b; w @# o7 r; U
- R- T6 |' H8 Q7 j: P
Differential Pair Secondary Max Separation 2 W5 T7 b \' }: @
差分对走线的次要距离太大3 M! @* u9 j, S$ }6 @0 A
" Q J+ A ~& I* p6 J
Differential Pair Secondary Max Length % _5 m$ g3 T6 G
差分对走线的次要距离长度过长$ q" m( K6 a; E" G ]
DI
8 {9 e, G& j3 e) o , G- [; D8 S; [- d9 x
Design Constraint Negative Plane Island
; e3 Y8 ~7 A( N3 N b* Y负片孤铜的错误9 }% k, w" l6 P+ E* R& y$ {9 H
ED/ c9 v0 i) {5 L) f/ q1 e2 f7 ?6 d
) ?8 ~/ Z+ K: _, JPropagation-Delay # l* p+ |* X# A6 r
走线的长度错误% y& S$ d: c- l/ e2 \. z- m
1 E4 T9 b) h4 Z: W/ y" Q6 s4 Z
Relative-Propagation-Delay
; ^! C$ H! i+ c' z% z! `走线的等长错误
, t$ k* R; e* B1 P ~: r# d9 `4 xEL/ `* y# j# }. [1 b
3 p& z- Y+ M( L2 D' o- k1 ~Max Exposed Length
' [+ v/ {7 A4 z; [; k4 o走线在外层（TOP&BOTTOM）的长度过长
* L& [! y u) C$ A% F s# n9 O% dEP" Q- \' w# j% Q/ K# K, ?! Q
0 Z9 {! g# T( | m* ]0 nMax Net Parallelism Length-Distance Pair q- n* G6 X9 m& D5 @) t
已超过Net之间的平行长度
* W* k1 G% N# a1 `7 [( }! |ES3 F o. Y( C9 Q3 i, Q
' X# F+ S' @1 [2 ^& m/ e( {; @) OMax Stub Length # @9 Y' D& C& z: R
走线的分支过长& Z1 G1 O$ c+ i7 }( S5 c' y6 m
ET
/ w+ {' X r7 X" q+ r' k* }: f4 U& u
1 X7 g% m# B+ s# eElectrical Topology 7 `8 Y: O$ W3 z% e
走线连接方式的错误1 n7 f* ?, V' @0 ?# H, p
EV' J; Q- O3 C. B
# P7 w3 m; J$ h6 A2 I8 D$ ^# w) y* H
Max Via Count 1 j. H, q. Z S9 L9 y' S1 a
已超过走线使用的VIA的最大数目; Z) _# A# e8 C5 x$ ]* l
EX
& c1 {" F% g3 H, x' B
! s: y/ K$ z' Q: P2 eMax Crosstalk
, ^$ n# a; i! l- u% `+ z已超过Crosstalk值
, Z- G1 J$ l* E# m
Y5 J8 s* c! z3 L% o. J5 x: S5 X; YMax Peak Crosstalk
: {7 b0 i7 l# T7 L0 R1 ~" @已超过Peak Crosstalk值
& ]5 X( F+ M2 ^2 I9 wHH9 t; F8 q8 M+ \0 u. j9 e
9 U: h1 j- j. @- D. b- l! s" a
Hold to Hold Spacing & c& A8 F0 R; \" h: Y
钻孔之间的距离太近
$ T* Z+ b$ \% mHW
, C2 t7 A" j: n
5 ?. u- ^$ |+ v" d. A4 D6 @# V, zDiagonal Wire to Hold Spacing
. F0 ^/ s( v. j斜线与钻孔之间的距离太近
, K' d6 n! {0 c; \0 I0 o
5 D% P; S2 \; y: Q. q# VHold to Orthogonal Wire Spacing 0 w0 }- g! y. F7 R" r
钻孔与垂直/水平线之间的距离太近2 H' R8 U: } r9 E! @! s. z
IM; r: M6 V) b3 G: }- u. S
' z" O0 f1 o$ X% s+ qImpedance Constraint
' ?' j5 `2 M$ ^: Y6 s走线的阻抗值错误3 @8 v7 o7 X) f5 C: J, ^
JN
7 y& s& T2 R* M& Q; v
, A6 N$ o2 @+ m% v8 QT Junction Not Allowed
8 M1 ^! `6 @4 _* h/ O走线呈T形的错误
# H* i6 o b) p* ]0 x& zKB, ~( `& d* L4 X/ z/ f; E, _0 M
- R) H$ j) b1 \; D
Route Keepin to Bondpad 4 N$ k; L/ b& f) `& ]
Bondpad在Keepin之外
$ r3 e' R" h- @ # d; v8 S5 l! a0 {
Route keepout to Bondpad ) g. Z& @- G m" t3 O" h Z. P i* J
Bondpad在keepout之内
; ?3 |! g4 O; L2 |- A/ o 7 O9 O L9 h4 n' Q- w) i% N
Via Keepout to Bondpad
% _# ~% x. G' s" DBondpad在Via Keepout之内
* m* [2 s2 w t1 \2 \( ?7 x \KC
/ K2 L9 x0 e% R3 F; e6 P( G ' h- C5 d4 Q) }9 W! v4 ~) v
Package to Place Keepin Spacing
% C* B! I* Q8 `* p7 |& q, h& G% t0 x, l元件在Place Keepin之外
" J0 \1 E) a. p7 D4 h2 v
1 p2 X- p) Z8 u0 h- \Package to Place Keepout Spacing
C: i" z- \+ x) n- x$ T$ l元件在Place Keepout之内
( [* w( s, s* g- p5 PKL3 H5 O8 u0 R+ W/ {8 n/ c- r. t% \# I a
. K% T4 Y" R# f' ~
Line to Route Keepin Spacing ; J' \% c2 I- g. e9 e- L$ D# `' o
走线在Route Keepin之外
7 @- k. c$ w, Z5 J $ V2 V+ X& M2 C* F0 I5 m1 r
Line to Route Keepout Spacing / Q- P% u3 ^+ I8 I. x- M3 z- T8 K: t
走线在Route Keepout之内
" b S8 B( Y0 G4 p, _KS
" ~; c0 U* ?3 \" b8 h6 Q 3 @, R; W$ a0 _4 k
Shape to Route Keepin Spacing
+ t8 X! H( t5 P6 PShape在Route Keepin之外
% P3 X$ ^5 ?6 B7 I# T3 ~9 q , |( H" g( R4 H! S* c$ L
Shape to Route Keepout Spacing
9 ^7 M) X. G6 q& {) C' lShape在Route Keepout之内, H, u# r% |) p+ q8 m
KV1 M" G# f8 Y) z
4 L% ?, E/ X/ ^& ^. kBBVia to Route Keepin Spacing
) q$ p+ O) t3 c3 f) V0 FBBVia在Route Keepin之外
* y' h3 N! d' h b+ B
5 I3 \2 h" k1 @7 I* S% b1 U }BBVia to Route Keepout Spacing
5 L3 d7 z; T' w, s9 hBBVia在Route Keepout之内, F, ~3 q2 R- N! s/ g
9 k" n; W6 z+ x! n/ m+ bBBVia to Via Keepout Spacing ; z; U; P3 n$ N/ H8 c' _* J4 }) l
BBVia在Via Keepout之内; w: G( `, V1 I$ O2 L: [% _
' P8 ~% M# J4 B0 h q. p/ W: p) zTest Via to Route Keepin Spacing ) J( n6 `" _* q \0 N# Z. v
Test Via在Route Keepin之外; Y5 i0 I/ n& s/ J5 [# {% F
+ n7 ?$ S F: s, v- Z! w4 e2 p
Test Via to Route Keepout Spacing 9 |+ ~# P' J: N% }5 ]1 D) W
Test Via在Route Keepout之内0 a9 c z. T( Q& D2 ]6 @9 O: b5 B' A. x
7 H1 H- A' e' [; g v8 {- b( Z
Test Via to Via Keepout Spacing 4 u, ~. [3 c$ ?5 r' p2 T
Test Via在Via Keepout之内2 Y( V5 d$ b0 r+ U# r& v+ [
1 R/ S8 y+ ]) C& u% i2 N8 M& G
Through Via to Route Keepin Spacing
3 n9 g3 u M% Z( MThrough Via在Route Keepin之外" v6 a7 w& |3 G2 ?+ `
; I Y# C: z4 E$ ~4 ZThrough Via to Route Keepout Spacing
# P, Z$ G0 S4 e8 D/ CThrough Via在Route Keepout之内3 l) O5 h8 x/ F" \1 O
p6 s1 L" t) Y( e5 t0 E8 \0 EThrough Via to Via Keepout Spacing ) m! S% _7 m1 w( a
Through Via在Via Keepout之内
! ^. z+ X r) Y; ^5 _LB- Q! ?9 N5 ~- w/ k% b2 B& d7 }/ g
* o- R& O5 l) nMin Self Crossing Loopback Length
& B$ W* C, Q. I8 O% ~* C无
1 b% x6 u3 e! xLL' _ G2 f. n. ^
/ l; ?" U+ X9 K3 ~
Line to Line Spacing
* v, z$ D( C. Q) ?- p O走线之间太近% c% V( |" U9 @8 A( V' D7 g
LS' ]( d% ~4 G9 q
: ]3 O F( p. h7 M0 {' s XLine to Shape Spacing # a4 K1 o9 C% [: u2 |3 _
走线与Shape 太近
: Y7 u: |) e. P: f/ ^9 P7 m$ @9 YLW
, S1 j/ H. N4 h9 } , A. V; d# A v6 F
Min Line Width + |6 s: b8 i0 r8 B* P
走线的宽度太细
5 b1 n' q& d# a m9 V |8 Y, p
/ C' o% ~2 ~1 d. o( J" X2 WMin Neck Width & I; B$ x( K8 t
走线变细的宽度太细" i, y# A7 n! d0 a5 p; v
MA+ @% C; X( x: f5 D; F) m
9 B8 q3 T& F& Z' iSoldermask Alignment Error Pad ( D; f8 f7 N* f% M% i& ]
Soldermask Tolerance太小: R& O1 |5 A/ v3 W' r6 G4 [
MC5 ]' P' E# M5 L" Q2 ^% ?
( D" f3 N' S$ t9 W, s. UPin/Via Soldermask to Symbol Soldermask
2 @1 d5 m6 v Z0 F+ IPad与Symbol Soldermask之间的错误) q5 e6 a! E4 p. T1 y
MM
9 q8 l7 w/ i" ]7 J; i2 _6 o
9 {- y1 U1 c8 D* O8 n% S5 GPin/Via Soldermask to Pin/Via Soldermask ' t. o* `& @- A6 ^! w
Pad Soldermask之间的错误
* p! n8 [1 R4 n$ y) r1 IPB$ Z3 I! O- V: Z7 Y2 h. C
9 t- I4 g! J2 q% {& x
Pin to Bondpad 4 {( ]% G- r& ]2 `' ?/ V$ f2 M2 F
Pin与Bondpad之间的错误
& |' P* {: m. }PL$ C! J) _$ l0 d
K$ s" [- X' y+ a
Line to SMD Pin Spacing
# x% l+ l1 ^# w6 Z( Z走线与SMD元件脚太近
2 K; e6 V2 M E( C( j: J0 z- }. E2 L" _ " U$ F3 C. Q( {2 Y5 e' z
Line to Test Pin Spacing
& ^7 D8 \% P6 ]/ }( j9 q走线与Test元件脚太近
0 U3 E( v+ w( i! R }' z
1 I& y5 ?7 z: O8 r& U: aLine to Through Pin Spacing {' [0 n, d9 F3 y$ O, `/ j4 C
走线与Through元件脚太近5 D( f5 P! E6 K! ]( h, D/ y9 i. j
PP4 w4 e5 Y6 M7 q, f f
1 v1 c5 i9 S; e; I* F: ?, jSMD Pin to SMD Pin Spacing - b% B5 \! s3 |/ Y, N
SMD元件脚与SMD元件脚太近+ s [; i3 U& x$ ~' a3 L' `
7 u' E7 x* n1 i( }6 B+ |6 MSMD Pin to Test Pin Spacing
! v% f( K8 L/ B% |8 vSMD元件脚与Test元件脚太近
9 u8 F: Q3 `* f5 @$ D
+ T/ f* g+ l$ ?- W( QTest Pin to Test Pin Spacing
4 V6 `7 s. E1 `) w) i( O6 T8 vTest元件脚与Test元件脚太近
2 i! {+ y3 l1 W' ]8 r7 N
8 K7 g, O* g$ t0 n; W' y7 VTest Pin to Through Pin Spacing
) l; R9 U0 i" ]& S+ l( ]. Y5 aTest元件脚与Through元件脚太近$ c0 R# `# |- a I" ^
% u. f# s* s5 @5 I! v
Through Pin to SMD Pin Spacing + V j& _# T2 q7 r
Through元件脚与SMD元件脚太近; j5 O/ o/ W6 l$ ~# y# u* u2 [6 ~1 E
4 F; Q, t1 z; g
Through Pin to Through Pin Spacing 2 P: a- T$ U- P3 L; G! w
Through元件脚与Through元件脚太近
7 A( m! z( L0 N& _- oPS
3 V0 i! Z) ~3 }- a, w ]
- g, N) e: |" X. u9 b0 IShape to SMD Pin Spacing
7 b; y4 q- o0 TShape与SMD元件脚太近! H3 _. Y- [- y+ f, T2 I4 N7 {
h4 K$ ?: r* y. b4 S. p% \* TShape to Test Pin Spacing
/ V) c, u, v5 C8 d5 Z; n9 mShape与Test元件脚太近
$ Z& \' z5 i3 x/ h* Y, X
6 g; B$ t( n) S! wThrough Pin to Shape Spacing [; V9 D; H! T
Through元件脚与Shape太近3 s# U K9 n# Z: ^; U% I1 R0 x/ m3 h
PV( K" L k$ E$ D3 ?+ X7 m c' c7 e
& G7 V- O; Y, l" \( H( d
BBVia to SMD Pin Spacing
7 w1 A4 w, i2 F) O% {3 GBBVia与SMD元件脚太近3 ^7 I* I! b5 n" x6 O# E: j
# q6 m6 I: E/ Y |BBVia to Test Pin Spacing
, a# J# _9 g: k% B1 lBBVia与Test元件脚太近
1 |( P. o1 K6 ]) C7 R; Y" j
0 J0 Z5 @3 b: X. U2 d1 k$ XBBVia to Through Pin Spacing + Q' l1 P8 f& w: ]8 b
BBVia 与Through元件脚太近5 [, `' b9 M& E% ^! l4 e. t B
% d$ Y% i/ [1 `) K
SMD Pin to Test Via Spacing * E4 Q, a1 T V5 y4 s% Y
SMD Pin与Test Via太近: @ L K- C* q5 d: F3 w/ A N
z4 I$ T4 g) A' ]3 t, ?SMD Pin to Through Via Spacing
! Z# M- z$ q5 ESMD Pin与Through Via太近
' v; Z& ^, L" i. R$ @9 s / v0 h3 s5 O! P) ~8 c7 \
Test Pin to Test Via Spacing
# \4 Y W$ K6 Q0 RTest Pin与Test Via太近/ x4 y/ e- X) }1 l+ w) ~7 s. r6 b' k
' N, [# ^7 O- |% b3 }+ B# J
Test Pin to Through Via Spacing
. W) f' O2 y8 h P VTest Pin与Through Via太近
/ K* P0 C# Q( {3 O+ G, a
5 C3 V! a7 {. \2 h2 L' g' m+ T+ tTest Via to Through Pin Spacing
+ |* r9 N# L7 hTest Via与Through Pin太近
) Y7 x$ W$ i* v/ [% L0 a
" Z# S6 } U; y: g4 VThrough Pin to Through Via Spacing # F+ B/ v$ f$ E
Through Pin与Through Via太近8 o! x! I6 V# E+ X% F7 w% n
RC" @( V: `3 @" c8 M1 w0 L
& W9 \5 Q/ I }8 X: g
Package to Hard Room 8 }* z0 P* I1 m. ~* ^5 {' {7 Q2 l
元件在其他的Room之内; u j4 u% u! O- y$ T+ A
RE
1 F% ~! A( t' D: Z4 y" U f " n- B4 p4 j% \% X- k3 G6 ?
Min Length Route End Segment at 135Degree ( U3 |1 [% x; m$ r p9 n
无
% l$ H1 ?4 _( P1 S9 @; x* Q
7 f' A( b- V" x$ A( B4 p1 sMin Length Route End Segment at 45/90Degree , R% I# X' k, P. R8 h8 E4 J
无5 S& T" ?$ u* `! ~, C, n
SB0 P" `8 y) X" x9 \; p
3 C( q4 F' q$ R. c7 Y
135Degree Turn to Adjacent Crossing Distance
U7 y- B4 _5 S' D9 w+ E无
3 F2 ~' z" T# m) k+ U4 P
* a- I. b1 }8 u& b; z5 {$ X7 O90Degree Turn to Adjacent Crossing Distance v% T% U% J4 m: c+ r% P% D$ o
无2 K# z8 K% K/ X% J H
SL
& Y0 \6 T [) h2 \' b4 y
5 ]; F" p/ o9 x2 G. q1 _ m: Z- dMin Length Wire Segment
) W6 g6 I6 K" x8 ]无
1 B) X- L4 ~# \ ; m$ T& r6 H# f8 s0 j
Min Length Single Segment Wire ) n) ^! Z2 p7 Q6 J& k Y: R7 }8 ^( X9 ~
无
) @4 t: _* N) USN
+ n; ~, h% \% }9 p* K ; D$ ^9 h% u5 ^1 t
Allow on Etch Subclass
2 P" Q; x& C! [5 ]5 E允许在走线层上3 f. n- o3 D% r0 b4 ^$ i
SO6 u/ a* g* g8 E
; C8 G. y+ M2 R j2 W- ?( o+ LSegment Orientaion
' f- x3 n3 h0 |6 N8 H) D$ Z无
6 F: Y$ r# Q r+ hBB: d/ J/ r' K0 m) H9 T: c
1 |. K" R+ J/ ?+ q0 PBondpad to Bondpad ! w, O5 f' z7 N! R; h0 T
Bondpad之间的错误
7 `; w9 n7 b" [( x6 w% G* kSS
; u+ r3 B5 h8 H z. A) ~
) [' ?" n% I, R4 IShape to Shape 1 g) ?# A8 |% ]8 Q( \0 @
Shape之间的错误) I3 z, p0 V$ x1 D. {
TA& a; m7 V# z' y3 @ l
1 I7 I: I2 [ ^Max Turn Angle
1 p, ?" I& x! J% Y3 R无4 Z# p& {) j8 c3 |: c
VB5 W3 [' |7 Q- n' l. H5 z. X' V
. U4 Q2 v0 @! T" K# c/ g
Via to Bondpad
/ T" K" X5 `' E/ oVia 与Bondpad之间的错误
: {: j4 j2 }4 {. M& N0 qVG# \+ n# n* o9 e! c$ E ^: [
3 z) k7 R" I! x' N. Z
Max BB Via Stagger Distance / ]8 F# Y, O" S8 b( `6 e% t
同一段线的BB Via之间的距离太长
8 P5 U4 k, p) E , \6 Q# l2 T/ X; S6 P. x! s5 q8 c, u
Min BB Via Gap
5 A8 c: T, c! LBB Via之间太近; O. B- l+ p1 c9 ^3 x% c" H% k
, B; S1 V" P# p0 |& d8 @: N# N
Min BB Via Stagger Distance 0 j9 h' p/ g# o( _) h, @
同一段线的BB Via之间的距离太近
, U/ r3 s3 ]7 s! p v
( H8 J5 Z9 Q- C8 X. f5 ]Pad/Pad Direct Connect
+ y: J* E; C, H6 p) ~4 `Pad 在另一个Pad 之上
. {- m, F% Q9 I% T) `7 [VL
/ o0 `( z0 C! [' | 3 r4 {( q, ^+ Q6 B( W
BB Via to Line Spacing
- F$ u% d& k3 I, a- Y6 dBB Via与走线太近
' F3 v" }% o+ y) c5 ~$ M( F e ' |+ ]. N6 r) `$ ?
Line to Through Via Spacing
8 z9 O; h7 w9 E5 P5 A6 N% L走线与Through Via太近
) k7 L! j5 ~) y* I 2 C8 U+ U# y9 B
Line to Test Via Spacing / H' i; h1 T8 ]# ?. P: H6 |: q
走线与Test Via太近
6 M3 n2 `7 Q7 eVS) ]0 ^) I9 O( z+ D& i
. Q8 a% R) G# g( b1 N$ a" {BB Via to Shape Spacing % f3 ~. Q1 X+ B0 q
BB Via与Shape太近 Q5 i4 b) ^. @4 w: e" d( x0 i
$ o- ?5 u- F9 {! o8 {Shape to Test Via Spacing 7 g ^( m' B: m& r
Shape 与Test Via太近" l! k8 J4 K" N6 H. U3 n, z( S
, l* N. Q" v5 {* h4 |- n* AShape to Through Via Spacing
# A% F+ `3 X9 ], D; ZShape与Through Via太近
1 o5 Z5 z4 e6 b! _, k/ T& E# t9 L( NVV m" M9 s0 @7 w6 M
2 J: z" I- \( W1 u5 n# [% wBB Via to BB Via Spacing
" r& i( B4 L: B; @: aBB Via之间太近
7 [7 m F H0 y5 x5 P
* {. S' e4 ^! u# g( T8 N$ RBB Via to Test Via Spacing
& u& X( m0 S& b! t/ i' {BB Via与Test Via太近
" G0 P% C. c% _# K W 0 ^: Y+ L1 l# [: t7 Z8 M4 m
BB Via to Through Via Spacing
+ h# R: S* r6 ~1 Z/ L4 TBB Via与Through Via太近5 _1 m' r8 G; a e) s* W# T+ G' a
& [/ C8 g6 M: g% w/ G% L
Test Via to Test Via Spacing
5 S* l0 l: d" V V. xTest Via之间太近* H" E g6 f& K5 F( g
6 W0 C% T7 N$ I" n
Test Via to Through Via Spacing
5 b4 G& h/ o, [0 h( x* S2 u) VTest Via与Through Via太近
9 W" V( M' r9 w' D2 V; i2 W* J
* E7 O6 J2 y4 Q3 `( M* Z" h; @ gThrough Via to Through Via Spacing 7 s9 {! o2 w1 D+ y5 \4 _
Through Via之间太近2 n" Q2 Z4 ]7 i7 ?
WA
# B9 e6 m" Z6 C$ s( D) F 1 f/ U& g" H4 `- a' ?4 V5 T: R
Min Bonding Wire Length 1 ^0 T5 a, ~6 g
Bonding Wire 长度太短1 l% ~/ C) `5 k( B: B; Y( x0 a& q
WE
Q8 U6 N1 b4 t$ Q B
3 p2 h8 G6 F6 y5 [# \/ G! VMin End Segment Length
, t% B* u2 T$ L& F1 P无
; z% _2 P1 E4 E( M* m
) l- t2 M" g$ W+ E; vMin Length Wire End Segment at 135Degree " V) ]# x/ y5 a! T( r1 h
无/ |5 Z1 D1 S1 }* C6 j$ ]9 Z
) _# t" m& \; X rMin Length Wire End Segment at 45/90Degree * T9 ?+ T; x# P1 R; v: M
无* R; m- t+ y/ N# y" W
WI
+ w$ O* O. r+ G1 U6 w+ F
& p2 C3 {' }/ b8 W7 F" @Max Bonding Wire Length 9 P5 ?- ]7 {3 E- n* T! @0 O
Bonding Wire 长度太长
9 u2 x7 N/ y3 V' OWW0 w% o2 L& R0 w7 l8 m9 q
2 T, v3 {: w, D3 f& E
Diagonal Wire to Diagonal Wire Spacing - F4 v. X6 ~2 g- _' d- F
斜线之间太近' c2 Q3 r- Y! v* E$ E
( Z+ j0 L+ k. ]2 \) R
Diagonal Wire to Orthogonal Wire Spacing
( k. W# _' d. M" B1 i斜线与垂直/水平线之间的距离太近- v( B9 g; A1 |
' W3 P1 }. X- M3 s. H, B3 |, |Orthogonal Wire to Orthogonal Wire Spacing ( h+ V8 j) q3 i
垂直/水平线之间的距离太近
! }2 F0 c4 r% x* u: x0 LWX$ H2 u/ c6 Q) B: M& s8 B
* b& X( X; x1 O/ k
Max Number of Crossing
0 L/ h( a3 E; M$ A3 p无
3 R2 O% _( [" E9 r& _6 F( X9 g0 ]
) D" M' ^2 D* D9 ]& t' m2 D; nMin Distance between Crossing 8 z0 A- b$ O8 A- D' P3 I
无) Q( g. U- ~2 d+ D( z
XB0 `. }1 e% J( } B
) [% u& V1 a" I/ W/ n: Y135 Degree Turn to Adjacent Crossing Distance
2 V1 f9 |0 z0 r0 C0 M无
4 L& I, q9 s! ?+ q8 `. [( N, ` 5 A" ]) s( m; M6 }8 h
90 Degree Turn to Adjacent Crossing Distance , E, @( R+ k( a5 K
无
% u9 u+ g5 _! A2 \8 H+ g! Q7 FXD
{/ r2 ^4 G( V! h% M1 d3 _7 q 0 \' c: Q, [3 Y# d7 d p( ~" Q/ [( a
Externally Determined Violation * A0 D, N/ W) V3 o/ |
无
6 c, t0 l8 J7 J8 |5 F1 U5 QXS2 `( A; D" N& @3 v7 x
( C3 R9 K4 m7 l- ^+ u4 v
Crossing to Adjacent Segment Distances + ? J% b R. N0 a
无0 x0 ^6 v' u3 H! r& U% s
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发表于 2012-11-1 19:26
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