Cadence SPB 16.5及最新Hotfix下载地址（Hotfix更新至033）

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cadence最新版软件SPB 16.5及其Hotfix下载链接如下：
2 b6 _/ j. Q9 p7 [1 g6 n. shttp://dl.vmall.com/c0t5v9lbyp
Hotfix中只需要安装最新的版本即可。

. I. Y  X$ r  BHotfix033对以下项目做了修正：
DATE: 10-31-2012   HOTFIX VERSION: 033
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' Q* q8 o! n' }) E4 r  Q6 GCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
. h2 K6 h% E5 n3 N2 g$ m4 R/ z0 j9 q===================================================================================================================================
- U9 }* v; `3 a& g& I103395  COBALT-COMPILE COMPILE          et3compile fails if compile for 3 boards in 32bit mode
* S" Q$ T# ^4 N! ^5 T: u5 u  r715653  Pspice         MODELEDITOR      Change in pin number assignment with model import for capture symbol
745682  concept_HDL    CORE             Attributes window requires resizing each time DEHDL is launched
# V1 C: v1 \, ]; O3 q825846  CONCEPT_HDL    CORE             The module_order.dat file gets corrupted
2 _4 D3 B7 b" J; |  e' O( m& V846658  CONCEPT_HDL    CORE             About Change the NOTE with DE-HDL
; a+ c) H. V. e( Z5 o938977  CONCEPT_HDL    CORE             Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
942044  CONCEPT_HDL    CORE             ConceptHDL crashes while opening the AMS project
946640  CONCEPT_HDL    CORE             Import Design should inherit module order defined in the imported block
; G/ ~: S; a" D" l968646  allegro_EDITOR EDIT_ETCH        The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
969535  CONSTRAINT_MGR SCM              ASA retains information in the DCF file for parts/blocks that have been deleted and this causes problems.
976723  ADW            MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor
% }) A0 p- F. C  q7 x, K5 s981767  SCM            UI               Add series termination in ASA will crash if both output and input pins are selected.
: w* |) |3 G4 y- {3 @7 ]$ T  \988355  PCB_LIBRARIAN  CORE             PDV moving line-dot pinshapes left to right or visa versa places pintext wrongly
8 C, r" ^" e+ D. n988438  CONCEPT_HDL    CORE             Visible constraint disrupts MOVE command
  A3 D; x/ G8 U993562  CONCEPT_HDL    INFRA            After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).
996577  SPECCTRA       ROUTE            Specctra not routing NET_SHORT connections
997992  CONCEPT_HDL    CORE             Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
1001300 PSPICE         MODELEDITOR      BUG: Simserver crash with encryptedm model
  G) M" O6 ]" {/ B* M1006400 SCM            OTHER            Incorrect warning in SCM due to way voltage value is stored in tabular and schematic blocks
" M: I6 S! V3 F  w9 I3 \" g) t8 y1011502 CONCEPT_HDL    CORE             Undo has an error on circle in DE-HDL during create a schematic symbol
: q4 r. x2 I0 Z& k  o4 H1011798 ADW            LIBDISTRIBUTION  generate a differential report on parts in DB vs parts in PTF while running lib_dist
; k8 @" {# z9 K0 c6 ^' E  E1012685 SIG_EXPLORER   INTERACTIV       SigXP: traceEtchFactor value is not used.
/ ^% @) @0 d& W8 g- T6 X7 ?1013656 SCM            OTHER            create diff-pair should honour diff-pair setup or ask user for positive negative leg
1013721 ALLEGRO_EDITOR EDIT_ETCH        Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
0 ]/ z0 ^. m8 O  p/ B' g; j1014319 CONCEPT_HDL    CORE             renaming HBlocks leads to crash
  [* `0 o5 l6 {1 X2 {+ B, @7 v4 x1017724 ADW            TDA              TDO update should force the schematic to re-read data from disk
0 w" v, f9 N+ q( U7 d5 p5 Q- ], B1018506 ALLEGRO_EDITOR INTERACTIV       Edit copy with retain net of via will assign net to pin
; Q  _. l: O+ }& A6 d1 I) l1019979 SIG_INTEGRITY  LICENSING        extracta batch command result is incorrect
1020746 CONCEPT_HDL    OTHER            PDF Publisher tool behavior inconsistent between OSs
1023051 SCM            UI               Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
1023057 CONCEPT_HDL    CORE             Strange message when opening DE-HDL - INFO(SPCOCN-2055)
1023281 PSPICE         AA_PPLOT         Bugspice advance analysis parARMetric plotter stops after 6000+ runs
/ W0 F9 I# p9 W4 I1023702 CAPTURE        GENERAL          orcad Capture/CIS copy and past page to other design Issue
1023807 SPECCTRA       GUI              Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button
& m! B+ `% E2 L( x# I# b1024890 PCB_LIBRARIAN  METADATA         con2con -metadataonly does not find footprints
; @5 T6 C9 p  p) M0 {  E' R1024899 PCB_LIBRARIAN  CORE             PDV symbol pins grid select all does not respect the filtering
1027147 CIS            UPDATE_PART_STAT CIS gives ERROR(ORCIS-6274) when updating Part status from Part Manager1028237 CONCEPT_HDL    HDLDIRECT        Error binding design when generating simulation netlist
  D" ~, [) ?9 m  K  x1 Z$ }2 @# c1028432 SIP_LAYOUT     DIE_ABSTRACT_IF  Support pin numbers in die abstract flow
" u7 k4 c: {, L" l0 c6 _. @1029369 PDN_ANALYSIS   EMVIEWER         EMViewer: Unit of Current Density.
9 y& I7 o& {' A; G8 e  A- Q2 {. n1030591 CAPTURE        LIBRARY          Library Correction utiltiy locks the library and deosn't frees it even after being closed
3 B, B9 }/ F  \1 ]2 M, m$ C( C1031474 CONCEPT_HDL    ARCHIVER         Uisng Gtar as the compression utility causes the 'delete archive' to fail
1031765 PCB_LIBRARIAN  OTHER            librarian_expert feature is kept checked out for two hours
- y& w1 T% g: x0 E9 C2 P  c* N+ c1032703 F2B            DESIGNVARI       Enhancement Replace Variant Component form needs to be resizeable
# n% v4 c1 b0 G# I1033607 CAPTURE        NETGROUPS        Capture crash if netgroup instance name has square bracket 縖�
1033853 SIG_INTEGRITY  OTHER            netrev crashes when importing logic
1035624 CONCEPT_HDL    CORE             Options pre-selected when launching base product
1 N* A& q! x/ ^( l5 C) |4 B1036580 ALLEGRO_EDITOR MODULES          Module created from completely routed board file has lot of missing connections in it.
1037345 ALLEGRO_EDITOR INTERACTIV       Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)
9 A# Z/ i% n+ \3 ^9 i2 W1038180 ALLEGRO_EDITOR DRC_CONSTR       BGA escapes not being calculated in phase tol
+ F6 v( j: g: Y, B% {/ i1038285 SCM            UI               Restore the option to launch DE-HDL after schgen.
1039147 ALLEGRO_EDITOR COLOR            Need an option to change color of Text marker and Text select in Display listing
, H' r  P0 S1 B% V# {3 ~1040257 CONCEPT_HDL    INFRA            New license files causing slow tool peRFormance
1040575 CIS            CONFIGURATION    SQL database views are not visible in CIS configuration step 2.
1040678 ALLEGRO_EDITOR MANUFACT         Text spacing is inconsistant for top and bottom SM layer in xsection chart
1040869 CONCEPT_HDL    INFRA            About uprev problems to SPB16.5 from 15.7
: @" n* C0 E- E, F9 [; N& E- B/ E1040976 PCB_LIBRARIAN  CORE             PDV replace pinshape on Linux shows very slow performance compared to Windows
: ]8 W  S% t% U! u  {* [; s1042603 PSPICE         SLPS             About SLPS simulation interrupt
) g2 y, X$ i1 c4 `$ g0 j1042695 CIS            CONFIGURATION    Can't see database views of an SQL database in CIS configuration
4 j- A9 b0 D* A  i$ J9 e! @9 x) [1043339 CONCEPT_HDL    PAGE_MGMT        The .con and .xcon files aren't being updated.
+ G8 a# k" ^% J0 D1044029 PSPICE         ENCRYPTION       Encrypted lib not working for attached
. R  @2 j" z2 S+ g' t7 S' Z1044222 ALLEGRO_EDITOR INTERACTIV       Capture Canvas Image changes working directory
1044264 PSPICE         SIMULATOR        Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.
( W7 h# e; W; Q: N1045607 ALLEGRO_EDITOR OTHER            Component get placed even after Cancel IDF in form.
1045609 ALLEGRO_EDITOR PLACEMENT        Statement in the Viewlog for Update Symbol needs correction
1045694 CONCEPT_HDL    INFRA            Why to package the design twice to pass the net_short property to the board?
1045734 ALLEGRO_EDITOR OTHER            Missing padstacks and layers information in cross section chart
1046929 CONSTRAINT_MGR OTHER            Unable to create physical of spacing cset after rename the default cset in design entry.
1047361 CONSTRAINT_MGR OTHER            CM fails to convert static phase tolerance value to database units.
, T' d3 Q& r2 N2 P2 H6 _/ @1047756 CAPTURE        NETLISTS         Not adding user defined properties in netlist generated by orDump.dll
6 _6 ?! g1 d: m6 _9 X1047823 CONSTRAINT_MGR OTHER            acPutValue predicate text not being displayed at bottom of Constraint Manager window.
1047869 CONCEPT_HDL    CORE             How do I define a custom pwr/gnd symbol for correct Verilog syntax?
: h- }/ v1 z% s2 @2 q1049303 CONCEPT_HDL    CORE             Block rename deletes schematic data immediately in 16.5
1049317 CONCEPT_HDL    OTHER            bomhdl with scm mode not working on RHEL in 16.5
1049399 SIG_INTEGRITY  OTHER            Toggling z-axis delay in CM shows the same value
% h, |, _. C* x( O$ E! w1049993 ALLEGRO_EDITOR EDIT_ETCH        Loss of Y axis when adding via in manual group routing
5 i" _4 |. K; f% {6 k+ G3 r1050483 ALLEGRO_EDITOR DRC_CONSTR       DRC has been waived but after updated DRC system generated a new DRC.
0 G  |. I' O/ {1051588 ALLEGRO_EDITOR PAD_EDITOR       Pad_Designer library drill report omits some drill holes
* C; c; v4 f& Z% }  v( q1052005 SIG_INTEGRITY  OTHER            Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
9 j% g# W4 v4 M' {) X3 O& {1052056 ALLEGRO_EDITOR PADS_IN          Pads to Allegro translator fails with error message "ARSE ERROR: Wrong label format:Translation aborted."
1052449 CONCEPT_HDL    COPY_PROJECT     Copy Project does not update all relative paths in the cpm file
0 n" {/ K  l; M: N! I: x1052479 PSPICE         PROBE            Cursor2 (Y2) displays the same value for all traces
1052753 ALLEGRO_EDITOR DRC_CONSTR       Allegro showing soldermask drc only when the symbol is rotated.
1052817 CONCEPT_HDL    CORE             Getting packager error after renaming nets
1053319 CONCEPT_HDL    INFRA            Change in property scope in windows mode is not retained
7 l$ ~$ H0 d1 {1053602 CONCEPT_HDL    OTHER            Using the attached .NDX/DML files causes a lot of delay in invoking Tools > Model Assignment.
7 g  T2 [' f+ z! D3 X' p# j1 W9 r. J1053660 CAPTURE        PROJECT_MANAGER  Find Part Pin name or number is not working
1054010 CONCEPT_HDL    CORE             MAKE_BASE
4 U$ b0 ^8 B7 k2 T1054235 ALLEGRO_EDITOR PLACEMENT        Cannot place alt_symbols for mechanical parts.
* u. Q- ^* M+ J2 |) y; j1054846 CAPTURE        PROJECT_MANAGER  Crash on pressing Esc key
& J3 t' I- H7 ?! _1055328 CONCEPT_HDL    COPY_PROJECT     Project Manager - Project Copy
% }. W# Q# j9 S6 n( h& ~& k0 U: Z7 `1055729 CIS            GEN_BOM          Standard CIS BOM per page is not working correctly with option  Process Selection
1056418 ALLEGRO_EDITOR OTHER            PDF exports the blank text markers whether or not the markers are visible.
) f5 m  f# U# d) M8 x$ }9 L1057003 ALLEGRO_EDITOR SHAPE            Z-copy to create RKI does not follow board outline
1 D% z0 l8 \5 b$ ~. q3 A1057976 ALLEGRO_EDITOR DRC_CONSTR       No Same net Spacing DRC on attached design.
1058364 ALLEGRO_EDITOR skill            axlTransformObject() is moving refdes text when only symbol pin is selected for move
# c9 z2 B, i: C: i1058940 ALLEGRO_EDITOR INTERFACES       IDF(PTC) out command output wrong angle value
1059901 CONCEPT_HDL    CORE             Global Property Change and <<OCC_DELETED>> property value.
: i: ~1 ^9 T. W% r3 a/ f& w, N6 Q1060428 CONCEPT_HDL    CORE             ADW Flow Manager Copy Project fails to complete
1060589 F2B            PACKAGERXL       Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
1061172 CONCEPT_HDL    CORE             Unable to delete Voltage
6 ]5 ]. s6 x; t. `# _1061424 CONCEPT_HDL    CORE             Customer creates <<OCC_DELETED>> property values.
1061659 ALLEGRO_EDITOR DATABASE         Unable to return drawing origin to 00
1062532 CONCEPT_HDL    CONSTRAINT_MGR   Our customer saw different DIFF_PAIR contentsevery time they invoke the Constraint manager.
1062558 APD            DXF_IF           If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
1064707 CONCEPT_HDL    CHECKPLUS        Rules Checker core dumps on design
' \+ N+ s+ x% h6 @7 l1065124 PCB_LIBRARIAN  SETUP            PTF properties cannot be deleted from the setup in PDV
1 O+ ?# l. C! }1065745 SIP_LAYOUT     DATABASE         The logic assign net command crashes the application
1065860 ALLEGRO_EDITOR REPORTS          Design crashes when running a padstack usage report
( L6 V. p2 h& f! O4 ?. n1066051 ALLEGRO_EDITOR TESTPREP         Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
1066318 CONCEPT_HDL    CREFER           Issue with LOCATION visibility in flattened schematic
- l! A8 H/ w- ?) i2 |3 `1068425 F2B            DESIGNVARI       Out of memory message in Variant Editor while 縞hange properties� command
. L) f/ [& {. G+ O- A1068966 SIP_LAYOUT     DRC_CONSTRAINTS  DRC update aborts on this design with  ERROR -3000067
5 W& h! y. b" n/ O& j8 I8 n1069215 CAPTURE        DATABASE         Capture Crash on usnig a TCL utltiy to correct design
1069517 SIP_LAYOUT     DIE_EDITOR       change die abstract pins tab default action from delete to modify

mengshang

真的很感谢您

topway

謝謝分享，不錯

amaryllis

眨眼之间又更新了

  O2 f$ n. V8 a/ v2 b谢谢楼主，辛苦了

wolfshiao

再下來看看..
, t6 x! o5 T4 e7 m% ]0 a9 t, s感謝分享了..

大波哥

感谢分享

elm99

谢谢楼主分享！

rx_78gp02a

这次改进的相当多啊，不知道16.6的hotfix什么时候有呢

linsky2000

顶，谢谢楼主分享！

LiuY

下载起来好慢啊

littlehit

谢谢分享

zbmzy

谢谢分享

lljian

哈哈哈哈哈哈哈哈哈哈哈哈哈哈哈哈哈哈