Cadence SPB 16.5及最新Hotfix下载地址（Hotfix更新至033）

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cadence最新版软件SPB 16.5及其Hotfix下载链接如下：
http://dl.vmall.com/c0t5v9lbyp
5 F; u$ i& b3 n3 \& h8 ?Hotfix中只需要安装最新的版本即可。
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1 F4 `" y  k6 L0 U' }  nHotfix033对以下项目做了修正：
DATE: 10-31-2012   HOTFIX VERSION: 033
$ [  ?5 x  R$ F: g) E: }! M===================================================================================================================================
$ c! E% X- A# T. FCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
103395  COBALT-COMPILE COMPILE          et3compile fails if compile for 3 boards in 32bit mode
) i# I$ a5 q: R715653  Pspice         MODELEDITOR      Change in pin number assignment with model import for capture symbol
  {' o# g+ w% q  j7 z745682  concept_HDL    CORE             Attributes window requires resizing each time DEHDL is launched
825846  CONCEPT_HDL    CORE             The module_order.dat file gets corrupted
' v: H2 B1 {1 n4 X846658  CONCEPT_HDL    CORE             About Change the NOTE with DE-HDL
938977  CONCEPT_HDL    CORE             Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
' t2 B; C. ^6 A$ m8 z' t2 l) A; R942044  CONCEPT_HDL    CORE             ConceptHDL crashes while opening the AMS project
946640  CONCEPT_HDL    CORE             Import Design should inherit module order defined in the imported block
" g! y4 y( u( s* x4 ~- f968646  allegro_EDITOR EDIT_ETCH        The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
969535  CONSTRAINT_MGR SCM              ASA retains information in the DCF file for parts/blocks that have been deleted and this causes problems.
976723  ADW            MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor
4 ^! a( ^9 A+ l( \, x# \981767  SCM            UI               Add series termination in ASA will crash if both output and input pins are selected.
2 f# |# u3 Q& m- Q3 z* X, R. X988355  PCB_LIBRARIAN  CORE             PDV moving line-dot pinshapes left to right or visa versa places pintext wrongly
8 I5 [8 O, ?( o7 O988438  CONCEPT_HDL    CORE             Visible constraint disrupts MOVE command
993562  CONCEPT_HDL    INFRA            After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).
996577  SPECCTRA       ROUTE            Specctra not routing NET_SHORT connections
997992  CONCEPT_HDL    CORE             Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
: r  ^7 f& F5 W7 u1001300 PSPICE         MODELEDITOR      BUG: Simserver crash with encryptedm model
1006400 SCM            OTHER            Incorrect warning in SCM due to way voltage value is stored in tabular and schematic blocks
1011502 CONCEPT_HDL    CORE             Undo has an error on circle in DE-HDL during create a schematic symbol
6 d0 k! |  A. }% m* i- T1011798 ADW            LIBDISTRIBUTION  generate a differential report on parts in DB vs parts in PTF while running lib_dist
9 m  l8 G" h. b/ M4 X8 X1012685 SIG_EXPLORER   INTERACTIV       SigXP: traceEtchFactor value is not used.
2 a2 A. `7 |8 ^8 i* b8 ?/ g/ @1013656 SCM            OTHER            create diff-pair should honour diff-pair setup or ask user for positive negative leg
& d* N4 T1 S0 d: V8 T+ _+ ]1013721 ALLEGRO_EDITOR EDIT_ETCH        Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
1014319 CONCEPT_HDL    CORE             renaming HBlocks leads to crash
  w( v& M6 M) T6 z+ u) p5 P# i1017724 ADW            TDA              TDO update should force the schematic to re-read data from disk
1018506 ALLEGRO_EDITOR INTERACTIV       Edit copy with retain net of via will assign net to pin
6 T$ `1 w3 `* `- l6 _# o" C1019979 SIG_INTEGRITY  LICENSING        extracta batch command result is incorrect
5 j* s* E6 ]' }2 f1 `$ S1020746 CONCEPT_HDL    OTHER            PDF Publisher tool behavior inconsistent between OSs
6 h8 _6 k8 D- o' E& E2 Y1023051 SCM            UI               Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
1023057 CONCEPT_HDL    CORE             Strange message when opening DE-HDL - INFO(SPCOCN-2055)
: z4 z+ Q, A9 m; d1023281 PSPICE         AA_PPLOT         Bugspice advance analysis parARMetric plotter stops after 6000+ runs
1023702 CAPTURE        GENERAL          orcad Capture/CIS copy and past page to other design Issue
6 T5 O7 [  T# S+ v2 \1023807 SPECCTRA       GUI              Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button
1024890 PCB_LIBRARIAN  METADATA         con2con -metadataonly does not find footprints
1024899 PCB_LIBRARIAN  CORE             PDV symbol pins grid select all does not respect the filtering
: A8 G7 p2 s  p" ?# ]1027147 CIS            UPDATE_PART_STAT CIS gives ERROR(ORCIS-6274) when updating Part status from Part Manager1028237 CONCEPT_HDL    HDLDIRECT        Error binding design when generating simulation netlist
1028432 SIP_LAYOUT     DIE_ABSTRACT_IF  Support pin numbers in die abstract flow
+ a: n* e5 t9 {. i) `# A6 k1029369 PDN_ANALYSIS   EMVIEWER         EMViewer: Unit of Current Density.
1030591 CAPTURE        LIBRARY          Library Correction utiltiy locks the library and deosn't frees it even after being closed
1031474 CONCEPT_HDL    ARCHIVER         Uisng Gtar as the compression utility causes the 'delete archive' to fail
1031765 PCB_LIBRARIAN  OTHER            librarian_expert feature is kept checked out for two hours
/ ]$ o, E5 R5 B3 w; K( H1032703 F2B            DESIGNVARI       Enhancement Replace Variant Component form needs to be resizeable
  |- u( E0 ?2 ]1033607 CAPTURE        NETGROUPS        Capture crash if netgroup instance name has square bracket 縖�
) D4 E/ Y. f  C2 Z6 {1033853 SIG_INTEGRITY  OTHER            netrev crashes when importing logic
1035624 CONCEPT_HDL    CORE             Options pre-selected when launching base product
6 `6 q' z& p+ u1036580 ALLEGRO_EDITOR MODULES          Module created from completely routed board file has lot of missing connections in it.
1037345 ALLEGRO_EDITOR INTERACTIV       Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)
1038180 ALLEGRO_EDITOR DRC_CONSTR       BGA escapes not being calculated in phase tol
1038285 SCM            UI               Restore the option to launch DE-HDL after schgen.
/ K# l% s( m2 l7 f1 L$ e. N- Y5 C1039147 ALLEGRO_EDITOR COLOR            Need an option to change color of Text marker and Text select in Display listing
8 m0 C+ l/ e; A( y# ^7 @1040257 CONCEPT_HDL    INFRA            New license files causing slow tool peRFormance
1040575 CIS            CONFIGURATION    SQL database views are not visible in CIS configuration step 2.
/ r4 Z1 w* G  f, |. F4 [8 u2 C1040678 ALLEGRO_EDITOR MANUFACT         Text spacing is inconsistant for top and bottom SM layer in xsection chart
1040869 CONCEPT_HDL    INFRA            About uprev problems to SPB16.5 from 15.7
1040976 PCB_LIBRARIAN  CORE             PDV replace pinshape on Linux shows very slow performance compared to Windows
2 P/ S/ u& }  b: m1 W1042603 PSPICE         SLPS             About SLPS simulation interrupt
$ p& i, s* g" ]1042695 CIS            CONFIGURATION    Can't see database views of an SQL database in CIS configuration
4 G& J9 m' o, `1043339 CONCEPT_HDL    PAGE_MGMT        The .con and .xcon files aren't being updated.
1044029 PSPICE         ENCRYPTION       Encrypted lib not working for attached
9 _0 Q( W  g$ r4 C  Y9 G8 e1044222 ALLEGRO_EDITOR INTERACTIV       Capture Canvas Image changes working directory
: D) R4 C2 @. f: K/ O1044264 PSPICE         SIMULATOR        Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.
$ j2 V& y4 Y7 G' p% ~1 |2 b8 l7 Z$ v1045607 ALLEGRO_EDITOR OTHER            Component get placed even after Cancel IDF in form.
1045609 ALLEGRO_EDITOR PLACEMENT        Statement in the Viewlog for Update Symbol needs correction
1045694 CONCEPT_HDL    INFRA            Why to package the design twice to pass the net_short property to the board?
1045734 ALLEGRO_EDITOR OTHER            Missing padstacks and layers information in cross section chart
( H8 F. z8 \4 q, ~7 ^) j1046929 CONSTRAINT_MGR OTHER            Unable to create physical of spacing cset after rename the default cset in design entry.
1047361 CONSTRAINT_MGR OTHER            CM fails to convert static phase tolerance value to database units.
1047756 CAPTURE        NETLISTS         Not adding user defined properties in netlist generated by orDump.dll
# G& g  h* N3 Z6 J  z" H1047823 CONSTRAINT_MGR OTHER            acPutValue predicate text not being displayed at bottom of Constraint Manager window.
* E* N: n; T1 M' F  E+ [; k! U/ ^2 l, I1047869 CONCEPT_HDL    CORE             How do I define a custom pwr/gnd symbol for correct Verilog syntax?
1049303 CONCEPT_HDL    CORE             Block rename deletes schematic data immediately in 16.5
4 \2 M- f$ |! [  s3 ^. C) |1049317 CONCEPT_HDL    OTHER            bomhdl with scm mode not working on RHEL in 16.5
: |* D5 P% Y% c+ t; U1049399 SIG_INTEGRITY  OTHER            Toggling z-axis delay in CM shows the same value
1049993 ALLEGRO_EDITOR EDIT_ETCH        Loss of Y axis when adding via in manual group routing
5 h- u8 D' L, J' W1050483 ALLEGRO_EDITOR DRC_CONSTR       DRC has been waived but after updated DRC system generated a new DRC.
9 C9 Z- I3 K2 r& q. d' z1051588 ALLEGRO_EDITOR PAD_EDITOR       Pad_Designer library drill report omits some drill holes
1052005 SIG_INTEGRITY  OTHER            Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
1052056 ALLEGRO_EDITOR PADS_IN          Pads to Allegro translator fails with error message "ARSE ERROR: Wrong label format:Translation aborted."
1052449 CONCEPT_HDL    COPY_PROJECT     Copy Project does not update all relative paths in the cpm file
% \8 R% [# `' w$ @& T# x5 ^( ]1052479 PSPICE         PROBE            Cursor2 (Y2) displays the same value for all traces
: g3 w0 U6 N6 {" p; R1052753 ALLEGRO_EDITOR DRC_CONSTR       Allegro showing soldermask drc only when the symbol is rotated.
1052817 CONCEPT_HDL    CORE             Getting packager error after renaming nets
9 H: x) ?$ H) g$ H7 U. w1053319 CONCEPT_HDL    INFRA            Change in property scope in windows mode is not retained
% z; j  u, M" c0 O1053602 CONCEPT_HDL    OTHER            Using the attached .NDX/DML files causes a lot of delay in invoking Tools > Model Assignment.
1053660 CAPTURE        PROJECT_MANAGER  Find Part Pin name or number is not working
1054010 CONCEPT_HDL    CORE             MAKE_BASE
, B0 k& }% I& a/ d1054235 ALLEGRO_EDITOR PLACEMENT        Cannot place alt_symbols for mechanical parts.
! u8 _& b, V9 G, _; H1054846 CAPTURE        PROJECT_MANAGER  Crash on pressing Esc key
! u* h, y! ?2 K( V, O+ n. k1055328 CONCEPT_HDL    COPY_PROJECT     Project Manager - Project Copy
; E. a& ~. m2 X! [1055729 CIS            GEN_BOM          Standard CIS BOM per page is not working correctly with option  Process Selection
- T9 c0 S- p! W1 R1056418 ALLEGRO_EDITOR OTHER            PDF exports the blank text markers whether or not the markers are visible.
" I" t7 n( o( h/ @1057003 ALLEGRO_EDITOR SHAPE            Z-copy to create RKI does not follow board outline
1057976 ALLEGRO_EDITOR DRC_CONSTR       No Same net Spacing DRC on attached design.
1058364 ALLEGRO_EDITOR skill            axlTransformObject() is moving refdes text when only symbol pin is selected for move
  H$ k8 q" L1 [5 J) J1058940 ALLEGRO_EDITOR INTERFACES       IDF(PTC) out command output wrong angle value
1059901 CONCEPT_HDL    CORE             Global Property Change and <<OCC_DELETED>> property value.
4 L( d. u( c0 ?5 |1060428 CONCEPT_HDL    CORE             ADW Flow Manager Copy Project fails to complete
1060589 F2B            PACKAGERXL       Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
0 K- F7 u0 Z; [5 X1061172 CONCEPT_HDL    CORE             Unable to delete Voltage
1061424 CONCEPT_HDL    CORE             Customer creates <<OCC_DELETED>> property values.
1061659 ALLEGRO_EDITOR DATABASE         Unable to return drawing origin to 00
1062532 CONCEPT_HDL    CONSTRAINT_MGR   Our customer saw different DIFF_PAIR contentsevery time they invoke the Constraint manager.
1062558 APD            DXF_IF           If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
! e6 W- Z+ s/ E) k1064707 CONCEPT_HDL    CHECKPLUS        Rules Checker core dumps on design
1065124 PCB_LIBRARIAN  SETUP            PTF properties cannot be deleted from the setup in PDV
1065745 SIP_LAYOUT     DATABASE         The logic assign net command crashes the application
6 S3 d- C: d" i! X1 V5 G1065860 ALLEGRO_EDITOR REPORTS          Design crashes when running a padstack usage report
1066051 ALLEGRO_EDITOR TESTPREP         Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
4 @$ P( F+ K! s: y1066318 CONCEPT_HDL    CREFER           Issue with LOCATION visibility in flattened schematic
1068425 F2B            DESIGNVARI       Out of memory message in Variant Editor while 縞hange properties� command
3 m+ R5 V7 @2 c: ^7 L4 M1068966 SIP_LAYOUT     DRC_CONSTRAINTS  DRC update aborts on this design with  ERROR -3000067
6 m/ j: n# d- d. [* B1069215 CAPTURE        DATABASE         Capture Crash on usnig a TCL utltiy to correct design
1069517 SIP_LAYOUT     DIE_EDITOR       change die abstract pins tab default action from delete to modify

mengshang

真的很感谢您

topway

謝謝分享，不錯

amaryllis

眨眼之间又更新了
$ f. `' D5 y  l- x, u/ V/ W( ~3 R9 i
; r, H4 P  b3 j* W) h谢谢楼主，辛苦了

wolfshiao

再下來看看..
感謝分享了..

大波哥

感谢分享

elm99

谢谢楼主分享！

rx_78gp02a

这次改进的相当多啊，不知道16.6的hotfix什么时候有呢

linsky2000

顶，谢谢楼主分享！

LiuY

下载起来好慢啊
5 \# V8 N* K2 h

littlehit

谢谢分享

zbmzy

谢谢分享

lljian

哈哈哈哈哈哈哈哈哈哈哈哈哈哈哈哈哈哈