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本帖最后由 紫菁 于 2017-9-14 11:21 编辑 ( N& B- i0 J. h" F
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下面链接是cadence SPB16.3及最新Hotfix下载地址，需要的可以下载！& E l: a3 c% K) i
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% s+ I8 W8 h8 j: a, kHotfix057更新的内容如下所示：" ^7 A/ k4 V8 J. i! Z( i' V; p
DATE: 12-19-2012 HOTFIX VERSION: 057
J( ^1 C, u F* Q( j: N; E===================================================================================================================================: Z0 M, Y8 _* k1 Q$ k0 @4 K
CCRID PRODUCT PRODUCTLEVEL2 TITLE
! ^9 J* W$ G" h/ i, d3 n===================================================================================================================================
0 |$ q1 q% b5 _' u/ i& i1080193 SIG_INTEGRITY ASSIGN_TOPOLOGY View Topology freeze during the extraction of the net connected to resistor network.
, X5 \. f0 s+ m1082509 allegro_EDITOR INTERFACES Export DXF in the 16.3 S056 roatate some pins.
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DATE: 12-7-2012 HOTFIX VERSION: 056* o& I2 r1 X3 w! p; S
===================================================================================================================================
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===================================================================================================================================
6 H, \' B/ x- T" M% b. \; ^825813 concept_HDL CORE HDL crashes when copying a property from one H block to other
+ n1 G, J, U: F871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash
$ A! i q* e# s# w0 J871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide
4 O: o: x. e% k2 h/ T" ~873917 CONCEPT_HDL CORE Markers dialog is not refreshed$ N7 o ^3 }8 r- |* ]7 C
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License4 R1 t9 I$ W, @9 ^
892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator: k# h: i7 T/ W# W! ]3 t
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic# b. {1 }4 S( e4 K! a! q
1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide |
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发表于 2013-1-14 11:49
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