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本帖最后由 紫菁 于 2017-9-14 11:21 编辑 # b: W. M2 `' @" J$ b
- o$ X- s. x" g下面链接是cadence SPB16.3及最新Hotfix下载地址，需要的可以下载！
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Hotfix057更新的内容如下所示：
& ?& x0 v$ I2 ]% @DATE: 12-19-2012 HOTFIX VERSION: 057+ `1 |$ f Q8 d7 `0 j% [7 _
===================================================================================================================================
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===================================================================================================================================
3 f8 b: N; K4 K" j4 I/ v1080193 SIG_INTEGRITY ASSIGN_TOPOLOGY View Topology freeze during the extraction of the net connected to resistor network.
, m4 ~2 J1 S- {8 a1082509 allegro_EDITOR INTERFACES Export DXF in the 16.3 S056 roatate some pins.
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DATE: 12-7-2012 HOTFIX VERSION: 056) S& h% A. a! H/ o U# Y% e
===================================================================================================================================
' D8 |8 {" g" J" E9 l7 K/ _CCRID PRODUCT PRODUCTLEVEL2 TITLE
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825813 concept_HDL CORE HDL crashes when copying a property from one H block to other
+ J2 Z9 X$ U- j+ ?( i871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash7 I: ?% }/ ^0 H3 I' w
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide1 H# [/ h% d9 h& E
873917 CONCEPT_HDL CORE Markers dialog is not refreshed
! `9 j' `+ O7 Q& z6 P3 a887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License1 q8 r1 N a/ i! k! {: e" A" ~: [* Q
892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator3 d& v( n4 B# _! S* Y) h. g0 ` c
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic
3 I4 k; B4 b1 b b' p1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide |
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发表于 2013-1-14 11:49
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