|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
cadence SPB 16.5及最新Hotfix下载地址（Hotfix更新至038）: m& k; S! k4 a l1 d! u5 E
! X5 O+ n) S0 a
+ Q3 g5 n1 C$ y, e/ v! X6 E a$ D. {" O" r! ~' ^/ [4 K7 D
下载地址：http://dl.vmall.com/c05sb7i5ed
5 \5 C7 o ~. T5 z
' u5 }6 l0 [' J# }. i. W: K" m2 S6 r# Y: T
Hotfix中只需要安装最新的版本即可。$ w- g. G6 P2 v) D0 d0 p, P
% u2 F# }8 Z# h6 L8 KHotfix038对以下项目做了修正：) S b5 h ^0 W, [' _' j! z, M
DATE: 02-15-2013 HOTFIX VERSION: 0385 ?+ T; ?6 ]& R o0 ~
===================================================================================================================================
/ n/ w$ u8 k5 Y- x9 hCCRID PRODUCT PRODUCTLEVEL2 TITLE5 N5 M+ X# e& X
===================================================================================================================================5 ` |' ]- x! i6 A- l
787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics
/ u0 t* B$ d( b7 a C. x8 h P911292 concept_HDL CORE Property command on editing symbol attaches property to ORIGIN immediately
( V' z M- e; \7 x1 n0 y995532 FSP DE-HDL_SCHEMATIC Hierarchical block name representing FPGA does not get updated in DEHDL after refdes change in FSP., _5 e* ~- B1 C$ W1 A* h" c1 p
1005812 F2B BOM bomhdl fails on bigger SCM Projects6 D& s/ {* v8 F, X9 u0 m
1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.+ q9 s. ] H" C
1059037 CIS PLACE_DATABASE_P Enable Refresh symbol libs menu in CIS explorer
6 s/ |' V- K. X" ^4 `( @1065636 CONCEPT_HDL OTHER Text not visible in published pdf( D0 T6 `- ?4 g) ^* g
1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts9 r& Q: `; f3 h1 c
1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic& Y6 ?- T6 J* @; h8 N3 H
1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate
. p1 H* j" w! |2 d. k) _ {1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher
8 m! Z1 l4 ]# u2 N- I1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.
, @* T% ~ i- Y$ f; i# ?& N- b2 N" J1093050 allegro_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing.6 V r/ t% u. e5 N
1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?$ r% o. d4 Y/ M: V. K$ V) m
1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3/ V' b( A! A3 y7 Q& w* [$ K2 Q
1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor; A$ Z" E8 Y( P- |
1095861 F2B BOM Using Upper-case Input produces incorrect BOM results
7 p' o9 {6 {$ S, Y, B1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn't show up after suppress unconnected pads� option.7 z8 @9 M* w6 q& S4 T4 S4 E
1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff8 q. X( D& _$ q% f
1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible: \- A4 ^* d5 h- |
1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35( o7 L v+ c: s( |; r, X
1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.3 \3 j" {4 ?- v- m
1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes.
4 W: f4 ]# K v3 ?3 q1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.! _, q# E6 E/ d7 p2 r1 |
1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend4 _& K& g7 W" a9 J Z z8 F1 |1 s
1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors) i" v: M+ K, _1 ]/ v" C' `/ u2 o) }
1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.
. x; b' n9 W4 K- f1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy |
|
[复制链接]
/1 
发表于 2013-2-24 21:41
收藏
淘帖
支持！
反对！
顶起啊 好家伙前几天才看到28的 现在都有38的了