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cadence SPB 16.5及最新Hotfix下载地址(Hotfix更新至038)% ~ P4 E, ?) ~ F+ R
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. s6 W$ E6 k! ~+ Q7 U( R下载地址:http://dl.vmall.com/c05sb7i5ed
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' [. P! G% p( P9 W7 j. KHotfix中只需要安装最新的版本即可。
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Hotfix038对以下项目做了修正:
# s6 U( d+ j5 q A5 v6 g. _( UDATE: 02-15-2013 HOTFIX VERSION: 038
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CCRID PRODUCT PRODUCTLEVEL2 TITLE0 w# r9 i7 p- _4 J
===================================================================================================================================
: c" }8 N, _" S* v& M% E! z2 W787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics
4 j) t+ R2 J7 H9 G. o" ?911292 concept_HDL CORE Property command on editing symbol attaches property to ORIGIN immediately, W* v5 G' Y7 d7 x: l, W! T
995532 FSP DE-HDL_SCHEMATIC Hierarchical block name representing FPGA does not get updated in DEHDL after refdes change in FSP.
6 e; M s( z9 v; Z) h1 D1005812 F2B BOM bomhdl fails on bigger SCM Projects% x8 f, {3 A3 d6 t
1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.! o- M# E- Q% r4 b
1059037 CIS PLACE_DATABASE_P Enable Refresh symbol libs menu in CIS explorer& h) y7 ]" x/ T! M2 ?
1065636 CONCEPT_HDL OTHER Text not visible in published pdf7 G$ j5 U- u0 j8 l9 M- d* R9 q
1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts4 B @2 r" z! u& d# \
1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic" L' v. ~- T, ]
1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate$ @" S& s, _. V
1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher/ {0 H, l& z1 |# W: | m
1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.
8 j/ s6 B$ ?% ?# t: R1093050 allegro_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing./ T8 h% z3 D! J8 O" e' h% m
1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?
+ o8 e& R2 B, L' z) {# L1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.35 a9 r* {! e0 R& X. f4 l( Y
1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor% m6 G+ t' ?& I
1095861 F2B BOM Using Upper-case Input produces incorrect BOM results
+ w4 d: w8 E$ E7 @1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn't show up after suppress unconnected pads� option.
' w; A: u6 ?# \8 |$ r8 V. H/ {1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff4 g0 i7 x7 R- j6 i4 J# z
1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible# X- K# q' q9 z. x
1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35 ?7 @" T4 b+ T4 T! U
1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.% B s+ g9 L0 W3 u
1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes.
) {' z: U; A; P3 w: ?- r1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.
$ T7 l' u+ O9 N5 B' Y. e1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend: P. G: C* _/ B8 {/ B
1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors h3 z( o$ E0 L& e. Y
1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.
0 {: z$ w3 V. y. g; }1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy |
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