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cadence SPB16.6已经推出,需要的朋友可以点击下面的链接下载:2 E, H" b- H: u0 ?( F
dl.vmall.com/c0pxuzug1s
9 X1 K, L. R- ~1 h: @# Y8 d. N6 {里面有补丁Hotfix_SPB16.60.001_wint_1of1.exe
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DATE: 03-7-2013 HOTFIX VERSION: 005
. J2 f7 H" u: h ?+ G===================================================================================================================================
, |% L/ L4 }3 w+ R4 r" HCCRID PRODUCT PRODUCTLEVEL2 TITLE
4 g, C0 C% ~, y) w! D===================================================================================================================================
' B' E$ l2 y, F# T, h- G1 T/ e3 \1067770 IXCOM-COMPILE COVERAGE Assertion failed: file ../covToggleCoverageXform.cpp, line 1102
$ J5 U4 K/ e0 _1 v; M1100442 allegro_EDITOR PLACEMENT Placement queue shows components whichs are already placed9 t' A: t0 C: l- @. v; S ~; _
1101555 ALLEGRO_EDITOR DATABASE Allegro Crash frequently# ]! Q1 E. y, I0 Z: y
1104011 ALLEGRO_EDITOR DATABASE Place replicate move group of a modules leaves traces behind
$ g' n9 l9 t& E& ~+ G" C1104065 SCM NETLISTER SCM 16.6 has problem generating Verilog with existing sym_1 view" g; N. q* A* ~6 C" m# l
1104605 F2B PACKAGERXL Pins of function swapped part in block not displayed
6 O) q, {3 p$ f0 v, r0 B- t- a1104790 SCM IMPORTS Corrupt data once SiP file is imported into SCM
( W* |% l& T) u2 b' S" o1105066 APD IMPORT_DATA Import NA2 worked in 16.5 "035" but fails in 037 and 16.69 x( a' U9 P1 j) w0 Z
1106323 ALLEGRO_EDITOR PLACEMENT Unable to locate specific placed symbol on this board as it becomes invisible after placement.
- D3 }( ^9 G6 Q, \1108032 concept_HDL CORE 'Find' option does not list all Components in the Design
9 Z& Q9 h0 l! L a" K( K1109080 ALLEGRO_EDITOR OTHER Window DRC is not working in orcad PCB Editor Professional |
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