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DATE: 03-29-2013   HOTFIX VERSION: 006
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CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
* |$ N4 a% C3 E. P9 t===================================================================================================================================
- p# e" y# _( X2 y, r* U110139  FIRST_ENCOUNTE GUI              Error in Save OA Design form
3 u, t" A) }  |. W" o625821  concept_HDL    CORE             publishpdf  from command line doen not work  if temp directory does not exist.
642837  Pspice         SIMULATOR        Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep
650578  allegro_EDITOR SHAPE            Allegro should do void only selected Shape without "Update Shape".
% l' O4 {8 [% m1 c$ q* C9 g% ]653835  ALLEGRO_EDITOR MANUFACT         Double character drill code overlaps with "cross" in NC drill legend
687170  SIP_LAYOUT     DRC_CONSTRAINTS  Shape to Route Keepout spacing DRC display incorrect
9 W* K- e: z2 a787041  FSP            DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics
- b  }0 [' {5 Z7 @& z0 z825813  CONCEPT_HDL    CORE             HDL crashes when copying a property from one H block to other
" ?5 [) p1 v/ \6 t834211  ALLEGRO_EDITOR SHAPE            Constant tweaking of shape oversize values is time consuming
835944  ALLEGRO_EDITOR OTHER            Customer want to change for Jumper symbol by other Alt symbol.
1 i2 ~/ ^# H" [2 @3 o# d- _8 a2 v868981  SCM            SETUP            SCM responds slow when trying to browse signal integrity
3 ?$ _, o1 s1 T) r. w871899  CONCEPT_HDL    CORE             'Multiple:' column of Grid window in DE-HDL option is too wide
873917  CONCEPT_HDL    CORE             Markers dialog is not refreshed
& P  O7 w1 j- h" o5 Y8 d887887  CONCEPT_HDL    CORE             Option to find unconnected Pins/Nets with DEHDL L License
888290  APD            DIE_GENERATOR    Die Generation Improvement
6 A) f. k# a! @8 X, }; r892857  CONCEPT_HDL    CORE             packager treats R? as a unique reference designator
7 I8 J( K' [5 M+ I2 n4 h9 |& Y902908  PSPICE         SIMULATOR        Support of CSHUNT Option in Pspice
908254  ALLEGRO_EDITOR INTERACTIV       Enhancement request for DRC marker to have a link to CM
0 l) b9 Z3 x! N, U0 z, @$ `0 V922422  CAPTURE        NETLIST_ALLEGRO  Netlist errors when using mix of convert and normal symbols
4 F5 Y( C/ E; E9 S" [923361  ALLEGRO_EDITOR INTERACTIV       Stop writting PATH variables in env file if no modifications are done using User Preferences
935155  CAPTURE        DRC              No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC
945393  FSP            OTHER            group contigous pin support enhancement
! U* W1 U2 j4 Y9 L969342  ALLEGRO_EDITOR DATABASE         Enhanced password security for Allegro database
& g* o; z% t4 q% J; F& v! t$ o1005078 CAPTURE        ANNOTATE         Copy paste operation does not fill the missing refdes
& q3 I% z3 z) b7 g6 u1005812 F2B            BOM              bomhdl fails on bigger SCM Projects
$ [( ]" @  p) B, P7 ]1010988 CAPTURE        OPTIONS          ENH: ADD ISO 8601 Date Time format to Capture
1011325 ALLEGRO_EDITOR PLACEMENT        Placement replication creates modules with duplicate names
; g: C% \9 `- m& J1016640 ALLEGRO_EDITOR PLACEMENT        Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net
( \+ [0 p, B' e' r! I8 L1018756 CONCEPT_HDL    CONSTRAINT_MGR   Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical
1032387 FSP            OTHER            Pointer to set Mapping file for project based library.
1032609 FSP            IMPORT_CONSTRAIN Import qsf into FSP fails with ¿PLL PLL_3 does not exist in device instance�
1040678 ALLEGRO_EDITOR MANUFACT         Text spacing is inconsistant for top and bottom SM layer in xsection chart
. X$ m) T4 ^" ?* S: p: z0 ]1042025 APD            WIREBOND         Order placement of  power rings for power/ground rings generation with using PeRForm Auto Bonding
/ r* q1 q2 M6 s& v0 c( @3 w$ x1045500 CONCEPT_HDL    CORE             Why Search results does not display the correct Physical Pages.
" X+ {3 P5 [( G/ e1047259 CIS            EXPLORER         Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type
7 m* p9 u% u" `1047756 CAPTURE        NETLISTS         Not adding user defined properties in netlist generated by orDump.dll
9 W% e. X# E  n# G0 z4 _1052455 RF_PCB         DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation
3 \4 u* U3 k1 \" ^  x  E1054314 CONCEPT_HDL    CORE             Zoom of custom text is different from other schematic objects
9 }. {6 R& z# I6 a$ Q4 B1061529 CONCEPT_HDL    CORE             Space can be included in LOCATION value and cannot be checked by checkplus
6 M) E5 a; C* T) m1064035 CONCEPT_HDL    COMP_BROWSER     Component Browser crashes on part number search using a library containing >23K parts
" u2 ~3 J2 A; N% |# q1064604 ALLEGRO_EDITOR MANUFACT         Enh - Include ability to add slot notes to designs
1065636 CONCEPT_HDL    OTHER            Text not visible in published pdf
* a! |6 W8 U. V1065843 CIS            PART_MANAGER     time stamp on library from different time zones triggers part manager lib out of date warnings
9 I$ c* s+ T! K5 h1066701 ALLEGRO_EDITOR OTHER            Missing padstack warnings not in Symbol refresh log summary
1067283 SCM            PACKAGER         ALLOW_CONN_SWAP does not work for lower level schematic parts
; F1 r4 f/ g" r. U# T% X1067400 CONCEPT_HDL    CORE             ERROR(SPCOCD-171): Port exists in symbol but not in the schematic
/ o1 j- j9 H5 t2 ?1068878 CONCEPT_HDL    CORE             Rotating symbol causes the pin name to be upside down
7 X+ y. d7 J! |3 W  a" ^1069896 ALLEGRO_EDITOR EDIT_ETCH        Cline changes to arc when routing even when Line lock is set to Line 45
1070465 CONCEPT_HDL    CORE             Why does ConceptHDL crash on renaming a Port Signal
1071037 PSPICE         SIMULATOR        Provide option to disable Index Files Time Stamp Check
. D0 |% v" j/ s1 [9 r! l+ t1072311 CONCEPT_HDL    OTHER            Schematics are incorrect after importing design.
1072691 CONCEPT_HDL    CORE             Customer has the crash from Run Script of DE-HDL 16.51 again(#3)
, D" n! R' L' }' |/ e9 K1 f3 `1072859 SIP_LAYOUT     DIE_EDITOR       padstack selection window crash from Die Editing: Component editing of Co-Design Die
1073354 CONCEPT_HDL    CORE             Bubble defined on symbol pin is not visible on the schematic
1073837 ALLEGRO_EDITOR GRAPHICS         Some objects disappear on ZoomIn ZoomOut
1074243 ALLEGRO_EDITOR GRAPHICS         Allegro WorldView window does not always refresh after dehighlight of objects
' E) J9 l% _/ [1 R) L- N* f1074606 ALLEGRO_EDITOR INTERACTIV       Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format
2 y! g- q" u# T+ j9 n9 s$ o$ |1074794 ALLEGRO_EDITOR REPORTS          add commonly reguested via reports to Allegro and ICP reports.  Via per net, via per layer per net
1075587 CONCEPT_HDL    PAGE_MGMT        Unable to insert page in schematic
1076117 PSPICE         PROBE            Copy & Paste text/label in probe window changes font size and later gets invisible
" a% J2 s0 H+ [: ^1 @1076145 SIP_LAYOUT     DIE_ABSTRACT_IF  Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.
! Q4 k& y. Y. d* {, O1076566 ALLEGRO_EDITOR EDIT_ETCH        Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.
1076604 ALLEGRO_EDITOR SHAPE            Sliding via in pad corrupts surrounding shape and generates false DRC Errors
8 F  j/ q$ n7 \: K1076820 SPECCTRA       FANOUT           Fanout fails to stack vias in bga pads.
1076868 ALLEGRO_EDITOR PARTITION        Symbols become 'read only' inside a design partition
1076879 GRE            IFP_INTERACTIVE  Plan Column should not be present in Visibility tab for Symbol Editor
1076898 CONCEPT_HDL    CORE             User can not increase logic grid size value continuously using Up button on Design Entry HDL Options
1077026 CIS            LINK_DATABASE_PA fonts changes while linking db part in 16.5
: L9 Q# z9 l8 h. n+ e# n1077187 ALLEGRO_EDITOR DATABASE         DBDoctor appears to fix database but nothing is listed in the log file.
) Q" z' T: w+ l2 Z; |1 h( [1077527 CONCEPT_HDL    CORE             ConceptHDL net with name U cannot be found using Global navigate
" s# e) u7 B+ j. e1077621 CONCEPT_HDL    CORE             DEHDL crashes when saving page 3
+ I+ {+ R7 B7 ^4 z: U' _! j1078270 SCM            UI               Physical net is not unique or not valid
1079616 CONSTRAINT_MGR CONCEPT_HDL      Packager error in 16.5 which is resolved when system is re-booted
" f# {# P  Y+ _2 N4 E4 l9 m& c1079821 CONCEPT_HDL    CORE             Project Setup does not respect $TEMP variable for temp_dir and creates a  directory in project calle
1080142 CIS            CONFIGURATION    peated entries in Allowed Part Ref Prefs
0 ~* B" f7 [+ z. D' W' o6 |) a1080207 ALLEGRO_EDITOR INTERACTIV       Separate the 2  types of SOV violations."Segments over voids & Segments with missing plane coverage"
1080261 PSPICE         SIMULATOR        Encryption support for lines longer than 125 characters
1080336 CONCEPT_HDL    CORE             Backannotation error message ehnancement
1081001 ALLEGRO_EDITOR PLACEMENT        Package boundary is not visible while manually placing a component when using orcad license
1081237 ALLEGRO_EDITOR PLACEMENT        Place replicate > apply does not apply component pin properties stored in .mdd
1081284 MODEL_INTEGRIT TRANSLATION      Space in the file path will create a bogus error
1081346 ALLEGRO_EDITOR INTERACTIV       With Place manual, rotation of the symbol is not updated.
1081760 FSP            CONFIG_SETTINGS  Content of ¿FPGA Input/Output Onchip termination� columns resets after update csv command
1082220 FLOWS          OTHER            Error SPCOCV-353
& c9 M$ \# t7 B1 F1082492 ALLEGRO_EDITOR PLACEMENT        Place replicate create does not highlight symbols.
" v' f. j7 y- G0 R& k6 ?5 D) z: k1082676 ALLEGRO_EDITOR EDIT_ETCH        HUD meter doesnot display while sliding / add command
& S: d3 P& z) U4 W1082737 CAPTURE        GENERAL          The ¿Area select� icon shows wrong icon in Capture canvas.
1082739 CAPTURE        OTHER            The product choices dialogue box shows incorrect name
- ~- D4 g3 x: V4 K- ^1082785 CONCEPT_HDL    CORE             DE HDL should clean the design with non sync properties in some automated way
1083761 CONCEPT_HDL    OTHER            AGND text missing from PDF Publisher
1083964 CONCEPT_HDL    OTHER            Do not display Value and other attributes on variant parts which are DNI
' D3 a; E, {, S* n- X1084023 PSPICE         MODELEDITOR      Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file
1084178 ALLEGRO_EDITOR SHAPE            Spike create on dynamic void.
: A% Z; Q6 Z  E3 N; ]3 N1084637 ALLEGRO_EDITOR INTERACTIV       Enhancement: Pick dialog should automatically be set to enter coordinates
1085010 CONCEPT_HDL    CREFER           Crefer crashes if the property value in the dcf file has more than 255 characters
1085347 CAPTURE        SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.
1085522 ALLEGRO_EDITOR INTERACTIV       Allegro add angle to Display->Measure results
' }- R) j8 N/ \" B1 a$ i1085791 CONCEPT_HDL    CORE             Publish PDF can not output Constraint Manager properties into PDF file.
. z# ^; _. m& ?4 h; a1 Z1085891 ALLEGRO_EDITOR INTERACTIV       about DRC update
) T$ T  W- u3 @( E2 Q! a. }1085990 CAPTURE        DRC              B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO
1086514 CONCEPT_HDL    COMP_BROWSER     Component Browser placement restrictions not working
1086576 CONCEPT_HDL    CHECKPLUS        CheckPlus hangs when running Graphic rules.
& a7 `: |4 O+ o8 u8 q1086671 PSPICE         SIMULATOR        SPB16.6 pspice crashes with attached design
' _  ^: ~5 G) g: W# V1086749 ALLEGRO_EDITOR mentor           mbs2brd: DEFAULT_NET_TYPE rule is not translated
1086886 CAPTURE        PROPERTY_EDITOR  "Is No Connect" check box in property editor doesn't work for power pins
1086902 CONCEPT_HDL    INFRA            Problems occurred while loading design connectivity
1 L: W3 g( A+ @; Q1 r8 h1086937 PSPICE         ENVIRONMENT      PSpice Color map getting doubled leading to crash after colors are modified number of times.
1087221 CONCEPT_HDL    OTHER            Part manager could not update any parts.
6 |3 t8 Y$ s2 G/ I" p/ q$ t1087223 CAPTURE        CROSSREF         Cross Probing issue when login into system with user name containing white space
1087295 SIP_LAYOUT     EXPORT_DATA      Enable "Package Overlay File for IC" for concurrent co-design dies too
1087658 CAPTURE        PRINT/PLOT/OUTPU Lower level design pages are getting print twice
1088231 F2B            PACKAGERXL       Design fails to package in 16.5
1088252 CONCEPT_HDL    CORE             Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.
1088606 ALLEGRO_EDITOR INTERACTIV       Pin Number field do not support Pin Range for Symbol Editor
$ f! z+ m5 v2 i$ D- G, z+ R1088983 CONSTRAINT_MGR CONCEPT_HDL      Units resolution changed in 16.6 Constraint Manager
1089017 ALLEGRO_EDITOR SHAPE            What is the cause of the shape not filling?
6 u1 J9 J$ u8 b( D1089259 SCM            IMPORTS          Cannot import block into ASA design
/ @3 Z' F  R' }* s% d1089356 SIP_LAYOUT     DIE_EDITOR       Distributed co-design : launching die editor taking more than an hour to bring up edit form
1089362 PSPICE         STABILITY        Pspice crash on pspice > view simulation result on attached project
1089368 SCM            OTHER            Can't do Save - cp: cannot stat ... No such file or directory
6 J# f* `) Y- g% l1089605 CONCEPT_HDL    CONSTRAINT_MGR   Power net missing from the CM opened from DEHDL Schematic editor.
1090068 ALLEGRO_EDITOR SHAPE            shape priority issue in SPB165
1090125 ALLEGRO_EDITOR DATABASE         Q- The rename resequence log file is not giving correct message.
0 ^8 E8 g0 ]& ?% b4 ]; `1090181 GRE            CORE             AiDT fails for the nets with errors SPGRE-21 & SPGRE-22
* w0 G+ |7 V5 ]1 `# q1090930 CONSTRAINT_MGR CONCEPT_HDL      DEHDL-CM does not retain customized worksheet.
, Z2 n( ~! \" n: @  E6 K; K1091335 CONCEPT_HDL    OTHER            Color change cannot remain in some situation.
1091347 CAPTURE        TCL_INTERFACE    The Project New link on Start Page doesn't work when Journaling is enabled
1091359 CAPTURE        GENERAL          Toolbar Customization missing description
! a2 N5 `7 D0 |, Y: k% h0 e1091662 CONCEPT_HDL    CORE             Incorrect behavior with the SHOW_PNN_SIGNAME directive
3 M2 I. \& ~0 N! J! i# i1091714 CAPTURE        PART_EDITOR      More than one icons gets selected in part editor at the same time
1092411 CONSTRAINT_MGR INTERACTIV       In v16.6 CM multiple net name selection under net column is not working as in v16.5
1092426 CONCEPT_HDL    CORE             Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design
% m. x7 ^# b" d5 P+ _1092874 CONCEPT_HDL    CORE             DEHDL wire short during move not detected with check enabled
1092882 ALLEGRO_EDITOR EDIT_ETCH        AICC should be removed from orcad PCB Designers design parameters
1092918 CAPTURE        GENERATE_PART    Generate part functionality gives no/misleading information in sesison log in case of error
1092933 CONCEPT_HDL    OTHER            PDF Publisher saves the pdf generated in the previous project folder
1093327 CONCEPT_HDL    OTHER            Getting error SPCODD � 369 Unable to load physical part in variant editor
; D" L0 j( c& o) P+ g1093391 CONSTRAINT_MGR OTHER            Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.
1093886 SPECCTRA       HIGHSPEED        Pin delay does not work in PCB Router when specified in time
1094223 CAPTURE        PROPERTY_EDITOR  CTRL+S does not work in Property Editor but RMB > Save.
1094513 CONCEPT_HDL    CORE             How to display $PNN for which SIG_NAME is not visible?
1094611 CAPTURE        PROPERTY_EDITOR  E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic
1094618 CONCEPT_HDL    INFRA            Unable to uprev the design in 16.5
4 s* G4 D* @( M- w& f3 N9 t1094867 CONCEPT_HDL    CORE             Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet
1095449 SIP_LAYOUT     LOGIC            Allow netlist-in wizard to work on a co-design die
) Y2 U8 l3 K* u; B4 G1095701 CONCEPT_HDL    CORE             Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block
1095705 CONCEPT_HDL    CREFER           Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3
" w: n, b% K0 o  x, Q1095861 F2B            BOM              Using Upper-case Input produces incorrect BOM results
, ]7 x, ^4 P6 {3 T' g( k1096318 ALLEGRO_EDITOR INTERFACES       IDF import not removing MCAD tagged objects during import
1097241 CONCEPT_HDL    CORE             Concepthdl - zoom in to first object in Find result automatically
7 p* E' t( n$ z  o1097468 ALLEGRO_EDITOR INTERACTIV       Need ability to hilight and assign color to vias
7 @, W- z2 e3 Y5 b1097675 CAPTURE        ANNOTATE         Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate
) p: [, q6 b8 d- C8 o. s1099151 SIG_INTEGRITY  SIMULATION       All Neighbor crosstalk numbers reported when there are no aggressors
1099175 CONCEPT_HDL    CORE             CPM directive that enables the Command Console Window in DE-HDL
5 x% u5 _* M8 N3 L3 Q$ F1099838 CAPTURE        TCL_INTERFACE    TCL library correction utility is not working correctly.
1099903 ALLEGRO_EDITOR PLACEMENT        Mirror and rotating component places component mirror side
* f1 ^# H  C/ m/ g1099941 ALLEGRO_EDITOR PLACEMENT        Problem in rotating bottom components when using Place Manual or place manual -h command
1099998 CONCEPT_HDL    CHECKPLUS        CheckPlus marker file not locating signal when signal name includes the # character.
5 t% x- Y( `& y; o7 u7 G* b1100018 CONCEPT_HDL    COPY_PROJECT     CopyProject gives errors about locked directives
1100449 ALLEGRO_EDITOR ARTWORK          Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork
1100758 CAPTURE        LIBRARY          Import properties does not update pin numbers of multi section parts
6 l7 k  R8 v7 I' p+ w; |# @: J. \1101009 CONCEPT_HDL    CORE             Cursor stays as arrow after performing File > Save Hierarchy
% h9 J9 s+ S# Q) v1101497 ALLEGRO_EDITOR UI_FORMS         Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.
1101813 SIP_LAYOUT     DIE_ABSTRACT_IF  Support die abstract properties
1102531 ALLEGRO_EDITOR GRAPHICS         Allegro graphics distortion infinite cursor 16.6
3 \( t! R) Q6 u& U- T( R1102623 ALLEGRO_EDITOR SHAPE            Strange void around the pad
1103246 FSP            FPGA_SUPPORT     New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3
1103631 MODEL_INTEGRIT OTHER            Model Integrity license when using orcad
1103703 F2B            DESIGNSYNC       Toolcrash with Design Differences
1103712 CONCEPT_HDL    COPY_PROJECT     Copy Project crashes on customer design attempting to update symbol view
& H$ I; @$ Z% v5 e1104068 CAPTURE        DRC              "Check single node connection" DRC gets reset in 16.6
' b' d* T6 a: S8 l" \) b1104121 PSPICE         AA_OPT           ¿Parameter Selection� window not showing all the components : on WinXP
! U# x) b, I9 o/ J4 p1104575 CONCEPT_HDL    CORE             Allign does not allign offgrid symbols correctly
1104727 CONSTRAINT_MGR SCM              Net Group created in sip does not transfer to SCM
1105128 CONSTRAINT_MGR DATABASE         Import dcf does not clear out user defined schedule.
1105195 SIP_LAYOUT     WIREBOND         Request that Tack points default to a "fixed" position after Generate Bond Wires.
1105249 ALLEGRO_EDITOR OTHER            PDF out--- component user defined prop doesn't list the prop selection form
1105443 PSPICE         AA_OPT           Parameter selection window in optimizer  does not list param part
* i+ ^" e9 S0 h$ F+ B1105818 ALLEGRO_EDITOR INTERACTIV       Menu-items seperators are clickable and menu goes away when clicked
0 j$ J# D# o# i8 s# ~2 Y( i1105822 ALLEGRO_EDITOR SCHEM_FTB        Netrev failing with compact pin syntax
5 {2 C0 Q' H0 D1 K) K1105993 SIP_LAYOUT     LOGIC            Import netlist no longer works with co-design die in SiP 16.6
1106332 SIP_LAYOUT     OTHER            sprintf for axlSpreadsheetDefineCell writes characters in upper case only
1106786 CAPTURE        SCHEMATICS       Bug: Pointer snap to grid
3 ]" S5 {, {/ S) e  [1107132 FSP            OTHER            Altera ArriaV (5AGXMA5GF31C4) support.
1107151 ALLEGRO_EDITOR ARTWORK          Shape filling removed when changing artwork format to RS274X in Global Dynamic Param
: m7 S# B# n1 R. w/ [1107237 SIP_LAYOUT     WIZARDS          Updating a Die using the Die Text In Wizard will error out and not finish
) b5 g% P9 g+ z1107371 ADW            COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).
1107599 CAPTURE        STABILITY        Capture 16.6 crash when trying to invoke
1108118 ALLEGRO_EDITOR OTHER            PDF Publisher pad rotation messed up with flashed pad.
1108574 ADW            COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode
1109095 SIP_LAYOUT     WIREBOND         Bondfinger move in hug mode create drcs
; N4 s1 U3 |# S' i1109113 ALLEGRO_EDITOR DATABASE         Allegro Netrev crash with SPB 16.6
1109622 SIP_LAYOUT     DATABASE         In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.
1110077 ALLEGRO_EDITOR DRC_CONSTR       Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
1110256 ALLEGRO_EDITOR SHAPE            Auto void on dynamic shape is not correct in 16.6
1110264 RF_PCB         FE_IFF_IMPORT    IFF Import in DEHDL has component offset
6 q4 g6 P7 x) h. I/ x; V! [1 Y: z1111226 ALLEGRO_EDITOR DATABASE         Name too long error with Uprev command when output file name exceeds 31 characters
1111234 ALLEGRO_EDITOR MANUFACT         Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
( p6 n( d  }' ?, K1112431 SIP_LAYOUT     COLOR            Frequent crash while working with latest version of CDNSIP
1112493 ALLEGRO_EDITOR DATABASE         Customer does not like 16.6 Ratsnest points Closest Endpoint
1112774 GRE            CORE             Allegro GRE not able to commit plan after topological plan
1113908 ALLEGRO_EDITOR COLOR            Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.
* H( v) b* l) R+ _+ ?7 r1114815 ALLEGRO_EDITOR OTHER            Q1: Switchversion error when reading -fa file
1114994 ALLEGRO_EDITOR DATABASE         Getting an error after upreving components to 16.6

DATE: 03-7-2013    HOTFIX VERSION: 005
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3 z2 z5 j0 R3 T  G. V3 kCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
1067770 IXCOM-COMPILE  COVERAGE         Assertion failed: file ../covToggleCoverageXform.cpp, line 1102
" \7 Y' U4 m0 ^, z- @3 a% m1100442 ALLEGRO_EDITOR PLACEMENT        Placement queue shows components whichs are already placed
. X" k- f& s* }) V1101555 ALLEGRO_EDITOR DATABASE         Allegro Crash frequently
1104011 ALLEGRO_EDITOR DATABASE         Place replicate move group of a modules leaves traces behind
8 y; R6 M# ~( U1 x! h) t5 ~1104065 SCM            NETLISTER        SCM 16.6 has problem generating Verilog with existing sym_1 view
( C0 O0 I: E8 X0 v( I1104605 F2B            PACKAGERXL       Pins of function swapped part in block not displayed
! [) M7 h9 b& B& y; s1104790 SCM            IMPORTS          Corrupt data once SiP file is imported into SCM
$ {; r* F. j9 E1105066 APD            IMPORT_DATA      Import NA2 worked in 16.5 "035" but fails in 037 and 16.6
1106323 ALLEGRO_EDITOR PLACEMENT        Unable to locate specific placed symbol on this board as it becomes invisible after placement.
) x  T1 ^2 |. m" f& `* d9 v1108032 CONCEPT_HDL    CORE             'Find' option does not list all Components in the Design
1109080 ALLEGRO_EDITOR OTHER            Window DRC is not working in OrCAD PCB Editor Professional

* N# I( Z1 P  l/ Y$ pDATE: 02-22-2013   HOTFIX VERSION: 004
===================================================================================================================================
1 g1 r1 c' u3 h$ Z9 O/ |$ ?( [CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
5 N& j1 O- y) T3 d8 G: d===================================================================================================================================
1081026 ALLEGRO_EDITOR GRAPHICS         3D Viewer do not show the height for the embedded component correctly
* q8 c( l. l8 |1095225 ALLEGRO_EDITOR EDIT_ETCH        The Constraint option does not work from right mouse click>Options>Line Width > constraint during interactive routing
9 e4 |* j2 u* ?& Z. V! l7 b1096356 ALLEGRO_EDITOR DATABASE         Cannot Analyze a Matched Group in CM
1097481 ALLEGRO_EDITOR INTERACTIV       Allow replace padstack command in design partition
$ f9 E: j8 n1 R$ q7 l$ E6 b0 f& U1098252 ALLEGRO_EDITOR MANUFACT         Double digit drill character overlaps with figure "circle" in NC drill legend
1099958 ALLEGRO_EDITOR PAD_EDITOR       Library Drill Report producing an empty report
9 m. R, A" y. }. O9 k$ A. B1100401 ALLEGRO_EDITOR OTHER            Invalid switch message for "m" for a2dxf command
  ?. E: J; A8 Y- A& b1 n, {1101026 ALLEGRO_EDITOR OTHER            utl_perftune hanging in fpoly_RemoveVerySmallSegments(), causing shape degassing never to exit.
1101064 SIP_LAYOUT     SHAPE            'Shape force update creates a rat
1102798 SIP_LAYOUT     OTHER            Stream out puts offset pad in wrong position if pad is mirrored but not rotated.
( O9 L8 D! N* \, o8 ?1 F
DATE: 02-8-2013    HOTFIX VERSION: 003
===================================================================================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
' y2 a4 m& A! u8 _+ r, M! Y===================================================================================================================================
1077728 APD            EXTRACT          Extracta.exe generate the incorrect result
& a4 L# l9 F( C; `. V* U! c1084711 APD            DXF_IF           Padstacks with offsets cause violations in Export > DXF
$ R0 s6 k  z0 k# q' x3 H1090369 SIG_INTEGRITY  LICENSING        Impedance value not updating in OrCAD PCB Designer
) U% ~! e+ S7 q& w4 V. H  b* e, m1093050 ALLEGRO_EDITOR DRC_CONSTR       Taper trace on diff pairs not checking to min line spacing.
1093563 SPECCTRA       ROUTE            PCB Router crashes with reduce_padstack set to on
1093717 APD            DATABASE         Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent
( ~2 X. J, X/ _* ^( ?1 W. g1094788 SIP_LAYOUT     WIREBOND         Wirebond edit move command
. U' H% c# ]1 ?/ X2 ?1095786 ALLEGRO_EDITOR DRC_TIMING_CHK   Allegro PCB crashes when running DBDoctor
1096234 ALLEGRO_EDITOR DFA              Via pad connected to shape didn¿t show up after ¿Suppress unconnected pads� option.
& T$ {( Q6 F' K& R! A: f+ [3 k& V, G1096313 RF_PCB         LIB_TRANSLATOR   Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff
7 _0 Q9 g8 R* q! k" }1 y; `1096613 ALLEGRO_EDITOR INTERACTIV       Enh-While moving parts silk ref des should remain visible
. [6 c. h2 @  O) B+ L8 h1096676 CONCEPT_HDL    CORE             SPB 16.5 HF36 breaks designs that workded fine in HF35
" f9 i0 L# [1 r# l# s  M) i: G/ @1096913 APD            IMPORT_DATA      Import > NA2 fails to bring in the Y1 component.
1097751 ALLEGRO_EDITOR DATABASE         Import CIS netlist crashes.
1097889 ALLEGRO_EDITOR DRC_TIMING_CHK   Allegro crashes when routing from a via to a pin using High Speed option license.
- _# c" {# q. Q. j  B7 Y; J
DATE: 1-25-2013    HOTFIX VERSION: 002
( b5 F! c# X4 o1 m- N' ]===================================================================================================================================
' j1 J/ B+ @5 N3 g" FCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
2 ]% |5 }! d  g, c2 ]9 O# `===================================================================================================================================
491042  CONCEPT_HDL    SECTION          Prevent PackagerXL from changing visibility on SEC attribute
. z: @( [( q/ Z$ p863928  ALLEGRO_EDITOR INTERACTIV       Segment over void higlights false "nets with arc"
; T% T/ M( V" e$ i% T% T1 _1067272 PCB_LIBRARIAN  CORE             Unable to retain the symbol outline changes
. _, S/ L4 Y. ^/ c$ j# U+ i0 k" C1074820 ALLEGRO_EDITOR GRAPHICS         losing infinite cursor tracking after selecting the add text command with opengl enable
1075622 CONCEPT_HDL    CORE             PDV Edit Symbol in DE-HDL all editing functions disabled since Hotfix 33
1076986 APD            WIREBOND         Wirebond Adjust Min DRC does not maintain the finger position in the same sequence
& v2 A2 Z( h, b: p( R1078031 SIG_INTEGRITY  REPORTS          Requesting improvement to progress indicator for report generator
1080213 SIP_LAYOUT     WIREBOND         Wrong behavior of Redistribute Fingers Command
1080667 ALLEGRO_EDITOR GRAPHICS         Allegro lines with fonts not displayed correctly in 16.6
7 q8 ~; k& ?1 {% {$ K$ |3 H1080982 CONCEPT_HDL    CORE             Crash of Allegro Design Entry during a copy of a note.
# p, {0 v8 n- t( d1081200 CONSTRAINT_MGR OTHER            In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete.
1081553 CONCEPT_HDL    OTHER            Model Assignment can not translate M (Milli-ohm) property value of DE HDL.
1081696 ALLEGRO_EDITOR INTERACTIV       Compose shape not working when radius is set to 1.0
1082595 ALLEGRO_EDITOR COLOR            Infinite cursor remains white even we change background to white
1082704 ALLEGRO_EDITOR GRAPHICS         infinite cursor disappears when using Display>Measure
. _, e# r# x$ @  J( e( i4 e6 L+ ^0 A, L1082715 SIG_EXPLORER   INTERACTIV       Single line impedance for BOTTOM Layer is not calculated in cross section upon changing the thickness of dielectic layer
1082774 ALLEGRO_EDITOR TECHFILE         Import techfile command terminates abnormally when importing a generic techfile.
$ r. L0 Z) Z; {) f1 ~3 y& h1082820 CONSTRAINT_MGR UI_FORMS         The configure generic cross-section pull downs do not work.
1083133 SIP_LAYOUT     INTERACTIVE      SiP will crash when using the beta Pad Rename command to change a BGA pads name.
1083158 ALLEGRO_EDITOR GRAPHICS         The cursor chage to Arrow head for Shape Select is more sensitive to location in SPB 16.6
1083533 CONCEPT_HDL    CONSTRAINT_MGR   Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout
9 [' P& C2 K: z+ M7 z7 Y1083637 PCB_LIBRARIAN  CORE             Save As is not renaming the NAME in the symbol.css file
1083934 ALLEGRO_EDITOR PAD_EDITOR       Error(SPMHUT-41): File selected is not of type Drawing.
1084148 CONCEPT_HDL    CHECKPLUS        The CheckPlus hasProperty predicate fails in the Physical environment.
8 m1 r2 Q0 H0 {+ T% Q, a1084166 SIP_LAYOUT     DIE_ABSTRACT_IF  Updating sip layout with new die abstract doesn't properly update IC_DESIGN_CELL* properties
: L7 x# W2 f5 y4 a( |7 M6 G$ [& ?1084285 CONCEPT_HDL    INFRA            Corrupted dcf was never fixed and caused PXL error
1084441 CONCEPT_HDL    CORE             Assigned net property value changes to numeric
1084542 ALLEGRO_EDITOR DRAFTING         Dimensions associated with frect doesn't rotate with the symbol.
8 {. @" }1 o* o' R9 V1084736 APD            IMPORT_DATA      Import SPD2 file from UPD-L shape Pad and text issue
1085008 ALLEGRO_EDITOR INTERACTIV       Relative (from last pick) option in the Pick dialog not working for pick command
1085139 ALLEGRO_EDITOR GRAPHICS         Infinite Cursor disappear during Add Connect if Infinite_cursor_bug_nt is enabled
7 Y8 Q* T+ ~( v# T' v" U1085187 SIP_LAYOUT     INTERFACE_PLANNE netrev with overwrite constraints fatal error
6 h. g- t, r# t4 t0 ]1 _# o1086402 ALLEGRO_EDITOR GRAPHICS         Infinite cursor dissapear when using command like add connect or Place manually with opengl enabled.
1086905 PSPICE         SIMULATOR        PSpice crash while simulating circuit file with BREAK function
1087770 ALLEGRO_EDITOR EDIT_ETCH        Allegro crashes on a pick with the slide command.
1088412 SCM            CONCEPT_IMPORT   why reimport block adds _1 to the netnames?
1088958 CONSTRAINT_MGR INTERACTIV       annot create Differential Pairs out of nets that belongs to a Net Group
1089336 ALLEGRO_EDITOR GRAPHICS         infinite cursor and pcb_cursor_angle
1090689 ADW            LRM              LRM: Unable to select any Row regardless of Status
1090955 ALLEGRO_EDITOR OTHER            Cancel command crashes PCB Editor when add rectangle
% }3 X0 \& o% Q" ~! t0 Z1091047 ALLEGRO_EDITOR REPORTS          The "Dangling Lines Via and Antenna� report seems to be missing vias that are antennas.
1091218 ADW            LRM              LRM is not worked for the block design of included project
$ I0 }' W, [" M) q$ Y' U1091443 ALLEGRO_EDITOR OTHER            Crash when toggling suppress pads
" |% o6 t+ j+ O1091706 ALLEGRO_EDITOR EDIT_ETCH        Allegro crash while routing after setting variable acon_no_impedance_width
1092916 CAPTURE        OTHER            Capture crash
1093573 ALLEGRO_EDITOR DATABASE         team design opening workflow manager crashes allegro.  possibly corrupt database

DATE: 12-18-2012   HOTFIX VERSION: 001
===================================================================================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
501079  ALLEGRO_EDITOR MODULES          Enhancement for Module swap function similar to component swap
" g6 \$ A; t* p7 R3 H% E8 a745682  CONCEPT_HDL    CORE             Attributes window requires resizing each time DEHDL is launched
8 a$ `* N: y, d8 T  `825846  CONCEPT_HDL    CORE             The module_order.dat file gets corrupted
871886  CONCEPT_HDL    CORE             Browse button in Signal Integrity window of DE-HDL option causes program crash
# y- H' n' r: _3 `$ f891439  ALLEGRO_EDITOR INTERACTIV       moving cline segments
898029  CAPTURE        PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore
9 v' \* D4 f; l$ j$ w/ q923210  CONCEPT_HDL    CORE             Search with multiple properties does not show all properties
3 Y+ f3 ~: c% j% n2 y938977  CONCEPT_HDL    CORE             Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
; b+ V, T3 o3 n5 k! o947451  ALLEGRO_EDITOR INTERACTIV       Allow the tool to select multiple shapes when assigning a net to more than one shape.
968646  ALLEGRO_EDITOR EDIT_ETCH        The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
- H1 [! e, {5 X9 c976723  ADW            MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor
+ |3 U6 I* X3 `981767  SCM            UI               Add series termination in ASA will crash if both output and input pins are selected.
982273  SCM            OTHER            Package radio button is grayed out
988438  CONCEPT_HDL    CORE             Visible constraint disrupts MOVE command
989471  ALLEGRO_EDITOR INTERACTIV       Functionality to zoom to the selected object in Pre Select Mode
993562  CONCEPT_HDL    INFRA            After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).
& _8 m0 Q. L/ a, \996577  SPECCTRA       ROUTE            Specctra not routing NET_SHORT connections
997992  CONCEPT_HDL    CORE             Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
- P4 p9 r$ a0 q( L5 `1001300 PSPICE         MODELEDITOR      BUG: Simserver crash with encryptedm model
1010124 PSPICE         SIMULATOR        Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs
& x( u- B" G0 |5 I9 K9 D& w& m+ c1013656 SCM            OTHER            create diff-pair should honour diff-pair setup or ask user for positive negative leg
1013721 ALLEGRO_EDITOR EDIT_ETCH        Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
1016859 SCM            REPORTS          dsreportgen exits with %errorlevel%
5 t* I& F8 o7 ?, f+ d' x1018506 ALLEGRO_EDITOR INTERACTIV       Edit copy with retain net of via will assign net to pin
1020746 CONCEPT_HDL    OTHER            PDF Publisher tool behavior inconsistent between OSs
& k4 C: \8 d) u2 h9 q; N1020798 SIP_LAYOUT     SHAPE            Shape not voiding on layer 2 causing shorts
$ M& V4 B8 R! O4 ?& o4 `1023051 SCM            UI               Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
1023774 APD            WIREBOND         After "xml wire profile data" is imported it isn't reflected to actual wire.
1023807 SPECCTRA       GUI              Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button
5 ]1 {( r$ V  t7 X$ i1024239 ALLEGRO_EDITOR INTERFACES       DXF pin location is moved when I execute DXF out
1028237 CONCEPT_HDL    HDLDIRECT        Error binding design when generating simulation netlist
1030591 CAPTURE        LIBRARY          Library Correction utiltiy locks the library and deosn't frees it even after being closed
1 {8 G5 {- T% G, V3 z, i1035624 CONCEPT_HDL    CORE             Options pre-selected when launching base product
- A/ n3 l5 W: K, S1035896 SIP_LAYOUT     ASSY_RULE_CHECK  Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly
1036580 ALLEGRO_EDITOR MODULES          Module created from completely routed board file has lot of missing connections in it.
1037345 ALLEGRO_EDITOR INTERACTIV       Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)
1038180 ALLEGRO_EDITOR DRC_CONSTR       BGA escapes not being calculated in phase tol
1038285 SCM            UI               Restore the option to launch DE-HDL after schgen.
1038371 ALLEGRO_EDITOR INTERFACES       Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."
& v' I- A! E9 l. g. G7 m" W: A1038577 ALLEGRO_EDITOR DATABASE         Modifying Void crashes Allegro
3 a% U$ d/ T+ A9 x! ~4 H: y  [1039112 ALLEGRO_EDITOR ARTWORK          Antietch and Boundary layers deleted when Match Display selected
1039147 ALLEGRO_EDITOR COLOR            Need an option to change color of Text marker and Text select in Display listing
& D6 ]# g5 P% C0 y1040653 ALLEGRO_EDITOR DATABASE         Cannot update netlist data,  ERROR(SPMHDB-121): Attribute definition not found.
1041368 APD            DEGASSING        The Degas_No_Void properties assigned to Cline does not work.
1041864 ALLEGRO_EDITOR MANUFACT         Allegro crashes when opening the Backdrill setup menu
7 U+ N& @8 R5 {/ f1042199 SIG_INTEGRITY  SIMULATION       Waveform list was not refreshed by switching tab.
) Q0 }% g2 H6 g: W  U1042348 SIP_LAYOUT     STREAM_IF        GDSII export includes the full refernce path, breaks CATS flow
1043861 SIG_INTEGRITY  REPORTS          Derating values are NA in bus simulation report when derating table is not in working directory
  S% b. S9 V# Y4 o4 p: X" D1043903 GRE            GLOBAL           This design crashes during planning phases in GRE.
1044029 PSPICE         ENCRYPTION       Encrypted lib not working for attached
% b7 g. G$ o% Z9 j1044222 ALLEGRO_EDITOR INTERACTIV       Capture Canvas Image changes working directory
/ e- s; g4 u4 n( o1044264 PSPICE         SIMULATOR        Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.
1044577 GRE            CORE             Plan > Topological either crashes or hangs GRE
% y' q3 x" c) C. y' O/ A$ W1044687 TDA            CORE             tda does not get launched if java is not installed
4 l# k. c% s7 u/ h! K1044754 SIG_INTEGRITY  SIMULATION       Incorrect waveforms when simulating with stacked die
1045607 ALLEGRO_EDITOR OTHER            Component get placed even after Cancel IDF in form.
1045694 CONCEPT_HDL    INFRA            Why to package the design twice to pass the net_short property to the board?
3 G) ]& c3 T% s2 X6 f1 i5 w) A! C1045863 CONCEPT_HDL    INFRA            Customer had the crash several times when they run script with SPB16.51.
! {" W( V4 n5 x) ]9 N: @1046929 CONSTRAINT_MGR OTHER            Unable to create physical of spacing cset after rename the default cset in design entry.
1047590 ALLEGRO_EDITOR SCHEM_FTB        Buses created in Allegro-CM are deleted by netrev in traditional flow
: y3 W/ `/ \  V0 Q3 b% ~3 v" y+ q1047823 CONSTRAINT_MGR OTHER            acPutValue predicate text not being displayed at bottom of Constraint Manager window.
8 n7 z  F# D: s/ D* A# W( @) v1048403 ALLEGRO_EDITOR skill            Allegro crashes opening more than 16 files with skill
1049262 ALLEGRO_EDITOR OTHER            APD and extracta crash owing to Wirebond.
1049303 CONCEPT_HDL    CORE             Block rename deletes schematic data immediately in 16.5
1049317 CONCEPT_HDL    OTHER            bomhdl with scm mode not working on RHEL in 16.5
$ C- R+ P' U7 l% g1049399 SIG_INTEGRITY  OTHER            Toggling z-axis delay in CM shows the same value
1049956 ALLEGRO_EDITOR DATABASE         BUG:dbdoctor deletes fillets as design is migrated from old version
1 Q! c2 F6 E( w0 N  ]0 B6 Z1050408 APD            DXF_IF           Symbol has 45 degrees rotation  in mcm but DXF doesn¿t.
: P& z+ R! U, R4 r6 ^1050483 ALLEGRO_EDITOR DRC_CONSTR       DRC has been waived but after updated DRC system generated a new DRC.
3 c4 u; V% ?& V2 t4 r. M1050918 ALLEGRO_EDITOR MANUFACT         Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.
% J6 G5 Y" S! Y$ M& \) Q  U1051588 ALLEGRO_EDITOR PAD_EDITOR       Pad_Designer library drill report omits some drill holes
1052005 SIG_INTEGRITY  OTHER            Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
" u9 P/ _8 ]$ v( f/ J1052045 ALLEGRO_EDITOR OTHER            Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3
5 F* ]0 b5 x4 r5 p+ ^( U9 W1052449 CONCEPT_HDL    COPY_PROJECT     Copy Project does not update all relative paths in the cpm file
1052600 ALLEGRO_EDITOR SHAPE            Adding a specific cline causing shape errors
1052753 ALLEGRO_EDITOR DRC_CONSTR       Allegro showing soldermask drc only when the symbol is rotated.
1054235 ALLEGRO_EDITOR PLACEMENT        Cannot place alt_symbols for mechanical parts.
1054269 ALLEGRO_EDITOR MANUFACT         Backdrill Setup and Analysis crashes on attached design
1054351 ALLEGRO_EDITOR SHAPE            Shape voiding fails for board having diffpairs with arcs
* z! a! K! }; c, X. K3 A/ R1054456 ALLEGRO_EDITOR MENTOR           mbs2lib incorrectly translates refdes label
1055273 ALLEGRO_EDITOR INTERFACES       DXF exported from Allegro has an offset in pad location for Y- direction.
1055328 CONCEPT_HDL    COPY_PROJECT     Project Manager - Project Copy
1055481 APD            SHAPE            keepout does not clear shape unless it's picked up and dropped down
% I0 d. m' s/ F1055729 CIS            GEN_BOM          Standard CIS BOM per page is not working correctly with option  Process Selection
: L" ^4 w( I4 w7 Y: y/ H1056418 ALLEGRO_EDITOR OTHER            PDF exports the blank text markers whether or not the markers are visible.
5 y$ J" e7 Y0 q, s6 Z$ Y! J3 p1056579 CAPTURE        OTHER            Ability to define custom variables for titleblocks that update for specific variant views
- M8 M5 x* Y6 O- d  G1 f; L1057003 ALLEGRO_EDITOR SHAPE            Z-copy to create RKI does not follow board outline
* ^+ [- c. H" l  g* v& B9 X1057976 ALLEGRO_EDITOR DRC_CONSTR       No Same net Spacing DRC on attached design.
$ v+ T6 y# h1 i1058002 SIG_INTEGRITY  SIMULATION       Incorrect Xtalk sim netlist was created.
& J2 J( P9 f. z. ^. g' W1058364 ALLEGRO_EDITOR SKILL            axlTransformObject() is moving refdes text when only symbol pin is selected for move
1058940 ALLEGRO_EDITOR INTERFACES       IDF(PTC) out command output wrong angle value
1059037 CIS            PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer
, w, ?1 D0 U& {* x6 s: r1059389 ALLEGRO_EDITOR MANUFACT         about back drill analisys report
; |4 h! O) S5 N, o& M6 ]1059901 CONCEPT_HDL    CORE             Global Property Change and <<OCC_DELETED>> property value.
5 y  v/ p; V8 p/ n: H' \1060428 ADW            DESIGN_INIT      ADW Flow Manager Copy Project fails to complete
/ ~; ]9 {4 g  h% ^& ]( X$ s& o1060589 F2B            PACKAGERXL       Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
5 i; o4 Y5 D  n; d- w6 N1060977 F2B            DESIGNSYNC       back annotate in 16.5 does not bring in already placed nets as global nets
1061223 CONCEPT_HDL    CHECKPLUS        What determines a passthru pin?
1061424 CONCEPT_HDL    CORE             Customer creates <<OCC_DELETED>> property values.
& c( {9 ~& d* r% V0 m1061572 ALLEGRO_EDITOR INTERACTIV       Shortcut keys wont work after "Edit Text" command is finished.
1061659 ALLEGRO_EDITOR DATABASE         Unable to return drawing origin to 00
1062558 APD            DXF_IF           If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
# W" Z" t/ q  L' m1062982 ALLEGRO_EDITOR MODULES          Module containg partitions has been imported to the main design and cant be refreshed.
1063284 PCB_LIBRARIAN  OTHER            PDV Save As is broken
1063658 ALLEGRO_EDITOR SCHEM_FTB        Allegro Import Logic does not remove library defined diffpairs
1063778 CONCEPT_HDL    CHECKPLUS        The hasSynonyms CheckPlus predicate is not returning true for all global signals.
1063924 CONCEPT_HDL    CONSTRAINT_MGR   Highlight the net between DE-HDL 16.5 and Constraint Manager.
1064707 CONCEPT_HDL    CHECKPLUS        Rules Checker core dumps on design
6 z! m/ Z% d; j5 V1065124 PCB_LIBRARIAN  SETUP            PTF properties cannot be deleted from the setup in PDV
2 m$ f0 ?* H$ r1065618 CONSTRAINT_MGR ANALYSIS         DRCs on board but Constraint Manager shows the columns as green.
1065641 PCB_LIBRARIAN  CORE             PDV symbol editor is crashing when deleting a group using delete or CTRL+X
* L9 G9 r1 C2 T( S" j1065745 SIP_LAYOUT     DATABASE         The logic assign net command crashes the application
- y# b6 B0 `7 {6 F1065860 ALLEGRO_EDITOR REPORTS          Design crashes when running a padstack usage report
1066051 ALLEGRO_EDITOR TESTPREP         Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
1066318 CONCEPT_HDL    CREFER           Issue with LOCATION visibility in flattened schematic
# s( \$ [0 V$ X3 ]4 l4 B1067339 CONSTRAINT_MGR ANALYSIS         Relative Propagation Delay analysis in the Partition file seems very inconsitent.
3 U6 r( P2 `/ j' `* M3 D1067984 SIP_LAYOUT     OTHER            layer compare batch fails with write protected file
1068425 F2B            DESIGNVARI       Out of memory message in Variant Editor while ¿change properties� command
  T5 j+ y9 c) O( ^, r7 E1068547 ALLEGRO_EDITOR EDIT_ETCH        Outward Fanout is not fanning out this 4 sided part as intended
+ y) w8 y$ p1 D" |5 r$ V1068966 SIP_LAYOUT     DRC_CONSTRAINTS  DRC update aborts on this design with  ERROR -3000067
1069215 CAPTURE        DATABASE         Capture Crash on usnig a TCL utltiy to correct design
4 z5 ?( V2 D( {' P3 T: q1069517 SIP_LAYOUT     DIE_EDITOR       change die abstract pins tab default action from delete to modify
' \' T- f+ q' `, g  j8 H- J1069915 ALLEGRO_EDITOR EDIT_ETCH        Allegro hangs with when doing spread between voids
1070007 ALLEGRO_EDITOR PLOTTING         Export IPF omits drill figure characters for backdrill holes
1071722 SIP_RF         DIEEXPORT        Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow
3 D  W0 d: f3 p1072067 APD            EXTRACT          When expoting using Extracta oblong pads with anyangle are abnormal
* T$ |; W/ n! x1072791 ALLEGRO_EDITOR DATABASE         Database check cannot fix error and keep report the same issues cause artwork cannot export.
1072806 CIS            EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6
1072843 ALLEGRO_EDITOR PLACEMENT        The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5
5 \. \( |# e  O3 E, l) p, K1072904 SIP_FLOW       SIP_LAYOUT       Probe pins not being mirrored in Die Editor correctly in Chip Down mode.
1073237 SIG_INTEGRITY  GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.
3 d( s* G, P! m7 @8 L) ^, r1 p1073445 ALLEGRO_EDITOR GRAPHICS         'infinite cursor graphics fail -ghost copies as you move cursor
1073464 SCM            SCHGEN           Schgen never completes.
1073587 SIP_LAYOUT     OTHER            axlSpreadsheetSetWorksheet command clears the cells in memory
* }$ }/ s* p  \" t- w% Y6 Q7 n1073745 CONCEPT_HDL    CORE             Import design fails
( m; m* P  K5 q( m% ]& y9 K/ a+ N1073852 ALLEGRO_EDITOR INTERACTIV       While doing a Copy Via use the last 'Copy Origin'
1074279 ADW            DSN_MIGRATION    Design Migration fails purge if there are cells with BODY_TYPE
1074791 CONCEPT_HDL    HDLDIRECT        User gets port exists in schematic but not on symbol message even though the port does not exist
8 p# B/ i; K( a& Y! b3 g% x1 o1075135 ALLEGRO_EDITOR DRAFTING         Ability to edit dimension text block in Instance Parameter
8 |0 t! T* _! P: E1075151 ALLEGRO_EDITOR SHAPE            Cannot change global shape parameter back to thermal width oversize after having used fixed thermal
  }$ `; F9 p8 D1075256 ALLEGRO_EDITOR OTHER            Import > IPF in 16.5 is dropping data.
/ Z0 j0 T7 |9 p; w. v$ S3 B1075853 ALLEGRO_EDITOR REPORTS          please add "PART_NAME" at Extract UI
1075934 ALLEGRO_EDITOR DRAFTING         Able to Changing Dimension Text Block
1075955 CAPTURE        SCHEMATIC_EDITOR ZOOM in 16.6  using key "I" on keyboard in not centered on mouse pointer
1075964 ALLEGRO_EDITOR SHAPE            Shape voiding is not consistent in conjunction with odd angle and arc traces
% c7 y- {, X& V' N# c& s1076086 SIP_LAYOUT     IMPORT_DATA      missing wirebond after import SPD2
& S# I  G* q+ E4 a1076202 ALLEGRO_EDITOR EDIT_ETCH        Allegro add connect causing crash after Hotfix
1076205 CAPTURE        PRINT/PLOT/OUTPU : Printing of User Assigned RefDes
1076536 ALLEGRO_EDITOR DRC_CONSTR       Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top
1076538 CONCEPT_HDL    CORE             Property visibility changes in attribute form not updated in schematic canvas.
1076655 APD            DXF_IF           Dxf does not get offset value if die symbol padstack has offset value
! H1 q* l8 [$ T0 i1 w0 T1 T5 R1076846 ALLEGRO_EDITOR EDIT_ETCH        Grid snapping broken after slide in 16.6
3 @8 f, _) K0 B1076891 ALLEGRO_EDITOR INTERACTIV       Symbol rotation not displayed correctly when defined as a funckey
. K. P3 s4 \$ ^& `1076909 ALLEGRO_EDITOR DRC_CONSTR       Allegro crashes while placing modules from database
6 `6 F5 H  d. r& r) m1077084 CAPTURE        NETGROUPS        Crash on selecting bus when Enable Global ITC is unset
1077169 APD            SHAPE            Shape > Check is producing bogus results.
1077572 ALLEGRO_EDITOR DATABASE         Mechanical symbol created with 16.6 cannot be placed on board.
. `0 d% o3 S& d2 h8 g4 O$ W1077879 ALLEGRO_EDITOR SKILL            Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim
( P3 h: D& a1 w: T7 \7 l6 c% }/ Z9 `1078380 SCM            OTHER            Custom template works in Windows but not Linux
  ]9 |) L) _2 Z, Z6 T2 \6 e1078497 ALLEGRO_EDITOR INTERFACES       Import DXF does not seem to work correctly.
! u1 J4 f0 O% I1078682 ALLEGRO_EDITOR DRC_CONSTR       Unaccetable slowness with Slide
5 O9 _4 Z3 ?2 {1079082 ALLEGRO_EDITOR PLACEMENT        Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping
! d* G0 Y. h, Y3 M9 [2 g1079533 ALLEGRO_EDITOR PLACEMENT        Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"
4 O5 L6 s1 \1 K1079937 CAPTURE        SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text
0 a. b; h4 X; m) B1 N1082582 ALLEGRO_EDITOR GRAPHICS         Allegro hangs on a given testcase using the MMB zoom control
1082981 ALLEGRO_EDITOR SKILL            Allegro crash while change the new symbol type as mechanical.
+ S6 j/ g6 _6 Y0 s1083230 SIP_LAYOUT     SHAPE            Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.
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