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本帖最后由 紫菁 于 2017-9-14 14:38 编辑
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: d# T$ o! }0 C. B3 Y( M4 R- O& S/ @DATE: 04-26-2013 HOTFIX VERSION: 0085 y% X, s. p6 ]9 I* l5 x L
===================================================================================================================================
, J# D& A I cCCRID PRODUCT PRODUCTLEVEL2 TITLE
! d0 L$ l4 G1 [8 @===================================================================================================================================. q9 T, U2 s6 v9 |
876711 allegro_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit5 H2 O0 o q$ c5 H# t
1080386 concept_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation) C" x F& O0 u1 l
1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device9 N. U) O/ R* w+ Y3 m
1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.
0 D: N+ z8 q5 T; r- Q+ l7 T% `1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section
* a8 w: k$ \/ Q* i0 b1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running* ^' g4 y6 `+ d4 d! Z
1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color.
* s) T2 ]; G. Z/ M7 J4 ~1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence$ g7 l- C" g3 K1 b7 \
1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred.
+ h# E" h/ C0 Q7 L1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason
$ S% e5 e3 O2 u$ P- U1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations.$ _% k, Z( K; N: n# _3 f9 Z
1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered?
z" i) J! @3 a! w1 [( q1120414 ADW LRM TDO Cache design issue1 l+ A* l% N0 p E" }, ~
1121044 SIP_LAYOUT skill axlDBAssignNet returns t even when no net name is assigned to via
& b7 C2 {+ e. W1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups
9 @. S9 |' i' x0 m5 D( i1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it. ^" i& s! H) ?( |5 A# z9 K
1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.9 G/ ?( b3 v: l0 D, z3 P
1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced
2 u! Y+ ~# ?) D4 Q$ r6 K1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file.
3 _- v6 E' O; ~0 L2 e5 Z1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable0 f6 c# N9 c& Q1 u* _1 G; L+ Z
1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file" W7 B" h* k h+ N) `9 a% p" S
1123816 CAPTURE PART_EDITOR Movement of pin in part editor$ t4 T. ^$ j1 w, {2 a
1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 50
% r* v, a2 t& [3 ^! s3 tDATE: 04-13-2013 HOTFIX VERSION: 007* g' ^1 B2 w4 w, T! I* k
===================================================================================================================================
3 O- z: L. o. W) TCCRID PRODUCT PRODUCTLEVEL2 TITLE
; T. G# }% k/ G# m===================================================================================================================================' s3 J; g V& [- G) E% Y8 P
1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die
) I5 r4 |5 \5 a5 Z7 z1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.6; K9 G" Z' ?9 A, k+ h% H0 ^
1112295 APD DXF_IF padstacksї offset Y cannot be caught by DXF.% h- c2 Q, j1 T! Y8 I# j' W3 \, O" l
1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components8 P) n9 V, `. j7 V3 u5 S0 P
1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly
5 E# C$ a2 R& p1115491 ALLEGRO_EDITOR SKILL telskill freezes command window1 X$ b" ]2 B* G6 A4 X# p, @" [7 {
1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.
0 K: m! g [7 X( q5 k1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer.
% [7 S) |7 V3 K. u: F5 |1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear
1 D. \2 W g& C, b! \3 v) P1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks# u& K1 W4 w0 ?/ T' W
1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?) d! u }5 s& D v0 W, @- {
1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh
5 a, I) }+ T5 H/ v/ i) q4 T* T! o1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh- W/ A! G7 D. L0 w" g9 X! i6 p
1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors
9 M: `- u6 _8 w0 A1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.6
+ v* n4 v* ^/ H/ ^8 Z+ [1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently8 J' g7 j4 Q0 ?' ^6 m4 F" q0 l: b( Z
1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps
+ e! H3 Y- Z9 A* D1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks
+ P$ Q+ e% g3 o* U+ R1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment.6 [7 l/ O0 Q, u1 K- c
DATE: 03-29-2013 HOTFIX VERSION: 0062 Q8 @( o2 k7 \2 P& M+ g$ L$ r
===================================================================================================================================5 Z L( r$ K( _& F* x
CCRID PRODUCT PRODUCTLEVEL2 TITLE
7 ~- ~8 k0 Z# ~ N===================================================================================================================================
+ j; e% ~2 d1 S; X# P- M' P110139 FIRST_ENCOUNTE GUI Error in Save OA Design form
5 ?. R% D+ K# l' I625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.0 g6 P5 { I0 x: b7 o6 L
642837 Pspice SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep
' k* E6 C) |: Y1 t( Y' @650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".
8 \& w, x+ G; V9 ^* p653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend
- f0 j9 O, j; e( \; A. @2 g( v687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect
" }- a N v0 N4 |% d1 N* G! X787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics
5 g3 w9 C" L1 K( ]825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other
+ C3 M5 P4 H1 b834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming
% L) s6 D! g. i! T1 z! [835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.% S4 Q& D) d/ `& \' [. C
868981 SCM SETUP SCM responds slow when trying to browse signal integrity
- \' l, T+ M5 P+ O871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide. C+ B6 f3 |6 w! ?
873917 CONCEPT_HDL CORE Markers dialog is not refreshed
& d8 c k* w: A: g887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License1 Y; n& G* n& K" F
888290 APD DIE_GENERATOR Die Generation Improvement9 u' q9 p3 W0 P7 _! w J
892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator
9 \! e6 L- ]! D902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice1 ?" ?7 T4 L) s$ q6 `
908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM
/ i( I: @, Q3 \6 ^7 l( `922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols
# r: h1 g. n" \/ X' s923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences
9 H, k8 {8 ?3 l h935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC
* S$ C1 ^9 Y ?% G! A5 d1 W% C945393 FSP OTHER group contigous pin support enhancement1 [* W" `7 U& `6 {$ J/ a; d
969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database
8 I! J9 g# w& G Z: [5 r1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes# k/ L* M9 `; G
1005812 F2B BOM bomhdl fails on bigger SCM Projects
( ]; ] T: Q k' a0 {1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture
0 R8 p ]& _2 s8 G8 ?1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names. y7 [, O+ q; w' l8 Z* W' T0 |
1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net
( H: |; t2 f0 y; r3 O1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical( _4 U( K8 s( N' P! v
1032387 FSP OTHER Pointer to set Mapping file for project based library.
1 B# b1 g. `3 a' H( A' c1 C$ K1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with ї LL PLL_3 does not exist in device instanceї. b! C6 R$ M0 J+ ?* ]% U
1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart
5 g- i+ l- H7 F! P% R7 q1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding1 C% l* ^! V1 D, M5 Q" g9 v; C0 t7 h
1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.
; Y$ d L% e1 y3 \' V( U2 s1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type
! y4 ~* J; l: Y2 V) F, c( e; s1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll8 ^0 a0 j5 b; D3 I3 K7 S. d
1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation
1 B: @- ~- j; o X) T: e1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects/ d- @' c) K2 o5 e' [
1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus
; b v/ ~7 s; Y* ^; ^* @# z1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts
+ q" ?& Q t- U. z V1 k7 v1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs
1 r8 T* M9 t9 z- t% b" l: e1065636 CONCEPT_HDL OTHER Text not visible in published pdf
6 b8 N- P; G0 h ^( s1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings2 l$ {. Y+ E5 Y T+ y0 g2 z5 _
1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary" w* z1 A0 X6 c' G
1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts1 `) J; x. S( P8 S7 G
1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic
* W- `, o% N5 ^+ S9 P) Z1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down: @* j) p D% t( h
1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45, G( h6 V3 L9 s* t6 X. k
1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal7 q) b4 P: I. H2 ^6 l, D5 B
1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check
$ B* j$ [% k8 P" |" _2 Y7 F& Z! C1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.$ D: k) T; [ w7 @2 Q
1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)3 J( t/ q4 W1 y2 x9 A
1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die) ^ E# q2 L4 V! N! L3 `! {, l
1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic
0 G& {! ^ Q) Q! G1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut
7 R% S. k- Z% `. j" [9 e7 e1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects
' r) t+ x7 r4 Q$ P( Y1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format7 T9 F) v6 H$ W2 f6 f1 I: }
1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net; I0 U: n1 j) x2 e' t
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic
& [3 t A" I, L% Z7 `8 p& d- q1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible3 ] ]1 ~) J9 G& O+ B5 R
1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.
% H4 ]2 E) f- H: o7 T. l1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.. q* [8 t' {3 u% o
1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors
% t2 B1 ~" e9 m' `8 }" Z! K, l. h5 F1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.
& |* Q3 S0 ~6 a. K, U( s* I* P8 i0 [1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition
. P9 G# t- Z% b% {0 S1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor
6 Y( @( e: h! q: T( I" w& Y1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options
h. N/ p/ n2 ]& j$ o' A1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5. M% b3 H) m( y) T" y. U
1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.9 x0 t7 H. P8 _# U* S+ q
1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate
# j; a4 Q. p4 r1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3
! A' h7 {: M7 i2 f0 Z. J; r1 H" J1078270 SCM UI Physical net is not unique or not valid
0 d, |+ R3 m( w. d$ A1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted0 Z/ e* r" N" V. S% b* X3 b3 f
1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle
+ Z: b G) }, e. f( S1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs( O0 b" h3 A. S5 n; n7 f% W, B; J, @
1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage"7 d& A. C: q3 _4 o; c
1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters& `9 U( Z4 }5 I; @" @
1080336 CONCEPT_HDL CORE Backannotation error message ehnancement5 T4 Y; q3 q! N: x) s
1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using orcad license
0 m" E& P8 V1 [1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd
F+ Q/ q* h0 t. |5 R: M1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error# j9 o( U6 c% b& s& b
1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.
, v( H% g1 L0 [* f0 g' b2 D6 r- [1081760 FSP CONFIG_SETTINGS Content of їFPGA Input/Output Onchip terminationї columns resets after update csv command( A+ |+ Y/ z* V- ?% V9 Q
1082220 FLOWS OTHER Error SPCOCV-353
% [) P/ L3 h5 i1 V( Q1 J1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.* v/ ~ I* R% M/ o3 ~0 b, p
1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command5 D8 x- d9 Z; G- r% r8 F% T$ l
1082737 CAPTURE GENERAL The їArea selectї icon shows wrong icon in Capture canvas.
: x2 n( S$ V B8 m1 n1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name- L. G3 q4 F0 |. B
1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way
+ u2 W+ v& Y; u# m: r0 E1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher3 S/ O6 a( {6 ?# i
1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI
6 y7 Z) X9 F2 d$ o8 J$ k+ W2 {1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file
) s! I$ M, I( U+ m2 `+ C7 L1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.( w5 ?' A7 v) k/ ^
1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates) F* t* O8 l1 X- b
1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters
& B, x1 |3 h5 I' }2 I$ X: U1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.* Q1 |; u: p! e- x/ e0 v
1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results9 f( S/ r1 ^: ^: Q0 L0 n7 i8 D; `1 k8 a
1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.! j" P: i" L: Y3 b* ~9 d* J
1085891 ALLEGRO_EDITOR INTERACTIV about DRC update
1 A0 o: @8 I' V1 R4 n+ K' h1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO
7 c7 w+ N: P; E+ i. r& O1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working
8 ~( `, K1 N: Z% F) ?- W$ M! O1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.5 e% `$ p# Z- T
1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design
% U+ F6 m4 d" H( S ^5 s' {1086749 ALLEGRO_EDITOR mentor mbs2brd: DEFAULT_NET_TYPE rule is not translated
* H9 P8 w9 k0 R5 h' v6 Z1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins
1 Z: ]/ W6 @: z1 _1 N/ I- ~0 L1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity, n6 t# M% X2 V: H
1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.! `6 ?. O& w% k! l( k
1087221 CONCEPT_HDL OTHER Part manager could not update any parts.
8 o$ V8 n5 C1 A: [4 l. I1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space
% C! r* E% I- H1087295 SIP_LAYOUT EXPORT_DATA Enable "ackage Overlay File for IC" for concurrent co-design dies too! e6 ^/ X3 _5 e- i
1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice6 s$ G- k* X6 {# e/ a' X' U1 s
1088231 F2B PACKAGERXL Design fails to package in 16.5
6 }; P" d* l/ d5 K0 g1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.0 M% z3 c6 o; L& e
1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor8 v* m+ \; u0 }, m, }7 t ~# @
1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager: u- G% q3 `7 F
1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?
; A- M5 s$ W1 \% y* ]1089259 SCM IMPORTS Cannot import block into ASA design( `- @9 R1 {+ T5 i9 t# `
1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form. B% D* @- n( m0 H3 A6 ~
1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project
- U/ Y3 \- F0 M1 i8 g7 p: ]1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory
: h B. {# |% W& S/ H; _2 r3 x1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.
2 u7 a1 q+ Z" j8 B% ?2 M1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165
& V! |; ?/ j. q+ p$ B9 q1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.
s' _8 Q0 H& n* L w( i1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-22
- a, f: L# k! s( S: U9 U' n& O: ~2 y1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.8 Z, C1 J8 P) R) B- M; R% J
1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.
6 Y; F7 P* M2 M1 M. s1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled7 x4 i( W: s5 A9 h7 Z+ x+ S
1091359 CAPTURE GENERAL Toolbar Customization missing description
) s8 v% ` x" Q+ P- g- Q# _1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive: Q$ L( U/ A: K! T; \3 t3 B
1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time8 ~ b) v% D2 T# x$ e, y3 R
1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5
8 ~6 t' z; H9 s9 c# o1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design
6 Q+ ]6 e1 u3 c/ T w/ _8 f# d [1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled" `, }4 y8 \. [& H) G
1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters* U. j( C4 b. U# ~0 {2 X
1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error# T0 {. P& N3 L' a1 _4 ^
1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder7 M" X6 q8 b* r( Q
1093327 CONCEPT_HDL OTHER Getting error SPCODD ї 369 Unable to load physical part in variant editor
' |' X+ I2 Q% z- `/ E1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.) l, o) d+ }# g
1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time
- H, o$ p5 G( X& F1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.+ d4 c/ v, c+ k& K8 `
1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?
9 ^. m9 ^: X) c" ?+ v8 q* b" R$ W8 b1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic' F5 h. J& j3 U; z7 J4 D L
1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5
5 U, `5 j+ i4 R( _0 i7 |; ~1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet! Q% Z8 @0 k* Y. E; N2 C( |
1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die
- ~, C% b i9 p9 L% X0 s1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block
6 p7 o. ~ O0 F1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3% d2 U: D4 c0 Q3 N6 ?
1095861 F2B BOM Using Upper-case Input produces incorrect BOM results
% P& T) o& Y4 v Q1 z0 y1 D* ` @1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import
7 F1 D$ {5 O$ A5 x- {- B* ^5 P. h1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically
' ~+ f; q4 n9 |8 t3 X( q8 \1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias
6 ?& K$ b9 ]8 Z* |1 R: i" C! Q b# e1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate4 x" [0 L8 X9 y$ _ V) K( j
1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors
' J3 z+ _8 l& O M1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL
4 e% j/ |% \( R1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly., n# n1 w) J0 s# j) l- ]: t' M
1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side8 e2 `4 a% h& C8 S
1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command* k) n; j: Z2 [, d D
1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.- f; P* H1 O$ h3 I% K
1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives8 A! s9 y7 \# s
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork E* q9 r$ v# b0 V* ?' h; I
1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts1 g0 I8 n, S: `8 m1 R9 |6 h/ t
1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy% P- G: b$ d/ `7 j$ U8 m
1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.4 @5 z4 | S a5 f& r" a7 w
1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties
$ i4 S+ x ]) f) C6 D% A1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.65 m3 k6 c' o7 p2 F) ^: i
1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad
; M8 ?1 A5 F4 ]6 D; o1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3
8 J1 ^, X8 N+ ?* c1 D2 V2 Q1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad
" [: ~' _5 x; L$ w z: ]6 O1103703 F2B DESIGNSYNC Toolcrash with Design Differences
$ F5 }: u6 c* g* z U8 N( i1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view( l3 A6 L J2 }6 ~" G4 G; J2 |
1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.66 ^" b, N# L0 m2 p/ ~" D# T
1104121 PSPICE AA_OPT їarameter Selectionї window not showing all the components : on WinXP i0 a& z4 B0 }: ?
1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly
0 }2 a# B1 h2 i$ Q) e6 |" R4 P1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM5 J; j7 L8 ^ Y
1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule.
/ c' x8 ]* h. `& d1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.
( H7 t, n$ F6 P" y0 \9 N1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form3 v7 G% y& W& \: n
1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part9 d) `% i F5 A9 x4 _$ N
1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked8 ]1 J! Y: S; X. T9 _/ i
1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax
7 L. Y( Y! ~3 }* J! Z( D, p1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6
3 f J& y2 t1 @7 D4 e1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only6 S4 o5 a$ g% c6 `
1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid& p. b! R( Q1 r
1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.0 e, \2 N9 A$ ~6 V7 s/ l% c4 ~
1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param1 G2 w$ o/ Y, l$ ?: x' n2 `
1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish
2 ]2 M4 _; k2 Y) L- \1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).- d- ~' z0 G. _5 p6 g+ J O
1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke
/ B+ }3 z2 K) |# }8 L1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.
( Q! M3 r% I1 J" r5 Q6 Y1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode. a7 y: c6 L g" v/ S/ p+ P/ r
1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs2 f/ t- d. ~( E$ U1 i3 U$ u' I
1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6: O) m( ]' M# U. B0 D
1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.
0 A# T9 f9 ]& a/ |1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
) e6 d* _ U# @% N- A0 M% j1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6
1 c: d; {" W+ h! v; P, J. V1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset* g. g3 {7 B3 |: B. E
1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters: G; j& J; G0 ]9 ]2 ~) @
1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
; b& F, s1 E T+ H& R1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP
$ i3 @# k6 z, r' y" }0 l- j1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint
: x* R6 f/ }: }' A0 I& T1112774 GRE CORE Allegro GRE not able to commit plan after topological plan9 e. _# k5 b4 h! t5 i+ V+ _
1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.
& e T2 H. r) C: Z6 Q h1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file
! }3 ~7 v3 z, u4 R5 w1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.65 e, o" W7 b+ d* s
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发表于 2013-5-2 11:34
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