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DATE: 05-24-2013 HOTFIX VERSION: 0107 _& k3 q) X( F- ^. g6 q% m
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J3 r0 i/ v+ f1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer9 i+ I- J# m& _5 y. N9 h, ]
1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border
+ F" I; g4 \" q" E1119007 concept_HDL CORE PDF Publish of schematic creates extremely large PDF files4 _4 g6 R% b! ~) Q1 \! t0 x
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
$ }- z" x8 P: G) g+ c2 w5 H1124610 Pspice SIMULATOR Attached design gives "INTERNAL ERROR -- OveRFlow" in SPB116.6* z: w0 h' i' e( u6 r. t& r9 `
1125330 FSP CAPTURE_SCHEMATI FSP generates orcad schematics with components (Resistors) outside page border
3 v) B* o6 W% p$ Z% S1131775 ADW LRM LRM error with local libs & TDA
) \% ~- `4 h- a; y- `* a1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
) w/ ~ i' [9 I1 N% J- k1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo
5 I. C1 a6 `: Q! @& ^& L( f1 R1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
% t6 c' y: T. M+ K1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur
* e8 q4 A, f" l8 B0 l& _5 d1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?
3 |! x& W0 G9 V2 O: h1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.
7 o9 F2 a0 V+ z, q! V8 o8 e. g1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor- H9 ]1 S9 [9 a3 i
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro
. H2 M3 m& f5 w- ~& ~5 A h1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.3 q1 j s3 Z3 x# `* E. O( X
1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.
- V3 C9 ` s# R6 C0 H1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash
. S+ ~3 W# `8 B1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF8 i2 z+ N Y5 a0 D7 e1 f: w* I
1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
- p) J9 V3 R% D, L1 O1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor, r7 l" j* O6 V
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发表于 2013-5-25 09:24
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支持！
反对！
发表于 2013-5-25 10:29
