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http://pan.baidu.com/share/link?shareid=437717&uk=3826038294% p8 _2 m. K; S8 i# g0 Q
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; @* Q; u+ B0 s" K1 sDATE: 05-24-2013 HOTFIX VERSION: 0104 @. I. L- U! e; M4 Y* x
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9 M2 P, P$ o7 {/ Z: r& p% r5 @CCRID PRODUCT PRODUCTLEVEL2 TITLE w, z: U, k5 P+ g
===================================================================================================================================+ j- \9 {8 e: K6 g2 ]
1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer% c; B, K$ |5 R# q
1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border
2 m$ | U; |4 Q* r! A+ l Z% E1119007 concept_HDL CORE PDF Publish of schematic creates extremely large PDF files$ ?: h' I/ ^# x [% r, S! x" D
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
/ Q4 F7 U% k. z3 q0 M1124610 Pspice SIMULATOR Attached design gives "INTERNAL ERROR -- OveRFlow" in SPB116.6
, B! W. s. h: s2 l3 u. q w1125330 FSP CAPTURE_SCHEMATI FSP generates orcad schematics with components (Resistors) outside page border
, _2 q6 M$ x6 ^& u! I1131775 ADW LRM LRM error with local libs & TDA
: c- ^6 p+ d1 o" H& \1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
1 {# I W0 R3 U6 w1 g! f4 c L1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo
& N8 W: K- |& \- d1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM., _0 |) Y! t5 p# K$ [4 C; r
1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur5 W K# U3 W9 C3 H; _
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?
5 J5 b% v! H! `! p3 P1 O+ z! |1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.7 p5 w: N' u# f! A2 r/ M
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor
. t9 X6 n7 j \1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro4 O2 f' I% \4 V, L( t- @
1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.
7 J8 a1 {9 E0 T. y4 Q1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.
- b5 y9 P, l6 I' ?6 t* `' ^1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash
; L1 |8 u! B4 C9 R2 ^+ X7 \1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
* k1 k" ^& B! c1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
6 P; z+ ~9 Y s+ A8 V) \! G6 L* a1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor, @& |$ E7 ^ X9 S
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发表于 2013-5-25 09:24
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支持！
反对！
发表于 2013-5-25 10:29
