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cadence SPB 16.5下载地址（Hotfix更新至044）3 r2 _/ v$ I8 ?: d3 d0 T7 A9 _
& w! l0 j& V$ J# Z6 a2 C; FCadence最新版软件SPB 16.5及其Hotfix下载链接如下：
f: b( }7 E1 P8 l- O+ shttp://dl.vmall.com/c0sfvdb4yy- W, r3 V( E: k* T) L7 b4 U
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Hotfix中只需要安装最新的版本即可。
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( {' @, P& L) P6 JDATE: 06-7-2013 HOTFIX VERSION: 044: p8 x; j( a" q
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
8 ]% D5 d+ z( n# N8 r) i* F===================================================================================================================================5 |$ v0 X# T4 Z( q, _2 s
1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers; |7 o. B0 W- _& Q D
1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer1 G Q x n+ c! S5 S
1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB( ^$ p {6 X: O
1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr.
# |* w: z! q9 ?5 M3 r1106900 concept_HDL COMP_BROWSER Component Browser peRFormance utility should honor CPM directives for include and exclude PPT7 v7 ~ U# E2 Q2 w1 ]0 R7 \
1110323 APD DXF_IF DXF out is offsetting square discrete pads.
' n h$ {1 {% U+ I, \! R- b! d1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files
8 ?+ p9 U7 ?6 g; \1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor8 q, d7 z+ h! s# m" t) ]4 D
1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening.8 R ?0 E. K+ O' ^. J/ y" V
1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically& x6 L" ~6 j0 P* N% E# M- y2 ?
1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one7 q8 ^) X1 h* u$ t) T
1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board
2 r \! b& x8 j* K# ?. i* v3 }0 z1124544 CONCEPT_HDL CORE About Search History of find with SPB16.5- w% s, }/ ^( u, B2 R. n
1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux7 d2 R! b# O7 \1 w" j* ?
1125628 CONCEPT_HDL CORE Crash on doing save hierarchy4 A7 k3 R [7 p$ \+ W2 \' O
1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.! t/ i' `6 n$ z8 w
1130945 SCM SCHGEN SCM Export Schematic does not copy all cells in the library. t( x7 Z8 e4 ]- T2 l$ D! t$ f2 v
1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction.& w. H: s& \% ?% d& e$ ^3 J
1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters
- Z' t# S( k1 ]; g8 z& |1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
: ^0 ~/ X; U/ c/ V1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.0 J/ C! q$ s& e; e( u4 T& V( r
1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command.0 D0 \2 ?- c. S; t( Q; g' w
1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder./ i7 J4 G0 J3 r8 w2 p4 ?
1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top' Y+ @; r/ u- S; f; i! V G3 n, [2 F
1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode.
7 u, A8 m: h1 ^ Q0 _1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.
+ e# J7 \! ?9 M, H- T2 U1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property
/ x4 P5 o( F+ E4 E: d8 }$ r( L1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs
- @/ {. Q0 {4 u" @6 O$ D1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness+ e3 w4 ~+ F0 k! W
1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped" `# `4 t1 Y" u; x i
1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero$ F* ~" M7 V9 B' m" h$ D7 Q3 H; o
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF& K6 @( o. q& E* n* ]: u& K9 r2 ^2 @
1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed
5 q2 e6 ~$ ]1 X. w/ ^) |! l- m! v# C1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP- c8 F3 A6 n5 |0 ]
1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case
/ u2 y: [& b0 [# Y$ H1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL
% V- b; j' j2 I: Y1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.
' r4 F' B5 L9 C& c/ [" d0 _; Z1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added
# }: k% K0 P8 m( b/ q6 Y1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps {* O8 |# j1 N9 G( e1 i
1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail. {. p1 V8 q: O
1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block |
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发表于 2013-6-17 08:20
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