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cadence SPB 16.5下载地址（Hotfix更新至044）* l p( W& e( h4 o# R; S1 p
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Cadence最新版软件SPB 16.5及其Hotfix下载链接如下：( M: W T# w5 l; g4 p5 x9 g Z
http://dl.vmall.com/c0sfvdb4yy, Y) W, n5 Q' f" }5 G$ r6 q. v
* K F, ]3 h3 `8 I6 j6 \Hotfix中只需要安装最新的版本即可。
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DATE: 06-7-2013 HOTFIX VERSION: 044: H2 _ V9 N% b; o0 e( ~+ s
===================================================================================================================================: @. z) F' q) _! ]
CCRID PRODUCT PRODUCTLEVEL2 TITLE
9 q$ k3 V9 \7 Y" ~# d===================================================================================================================================
* f+ F8 i2 R* b, O1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers
/ C, i2 t3 ?& R* V1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
" ~9 R6 m( f( l9 e3 I1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB
) `" |, U$ w' f2 c. g) r' w1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr.$ l' a/ R4 q2 T7 ~! v& Z# X
1106900 concept_HDL COMP_BROWSER Component Browser peRFormance utility should honor CPM directives for include and exclude PPT
/ N" N' Z2 q6 y( n7 d4 {1110323 APD DXF_IF DXF out is offsetting square discrete pads.
2 I% `7 e! O: c+ E4 P( }1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files+ q+ G/ Z' L+ R$ \
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor' v" D1 H6 z9 {, R
1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening.- @7 e V/ a5 ^6 {: f! J. H
1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically
2 c8 F! ~4 u' o, M! v+ t | }) l1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one' S+ c, N6 B: a8 n6 p- ?. Q+ j: L
1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board2 J3 W P& u6 n3 a% C
1124544 CONCEPT_HDL CORE About Search History of find with SPB16.54 {: _' F8 S% c9 ~! f/ E# h
1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux
" c! l4 x8 V v( a6 X g" d1125628 CONCEPT_HDL CORE Crash on doing save hierarchy
# V7 c* }9 E% T3 s1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.! _& v& J; ^# g4 @
1130945 SCM SCHGEN SCM Export Schematic does not copy all cells in the library. a2 G6 O: j7 R. k( @3 ]8 T7 @
1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction.
3 @0 }6 E" r9 G* ]1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters
! b, n# i1 g3 J, h$ L7 ^1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
1 R1 T' D# N: i/ `. W6 ]1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.# z, v$ @4 R# j3 F
1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command.; {2 d6 U1 b6 _& Y
1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder.7 |. F0 d9 B0 p
1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top4 Q0 J5 [5 }1 O) r g
1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode.9 }2 _& V( d& M6 f( N7 Q
1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.: N' @0 L6 A( e- C, \9 E
1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property! R h, |/ R7 [: h0 E' K
1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs5 s- ]; u% D2 t& E* D
1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness ?' |$ Y* F; i+ l! D2 N
1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped
% e8 X, d! p& E! W# g% }1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero' S7 A. D8 _0 @6 |/ {& F
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
& [. g: Y: ` s; f1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed
( f# \0 d z, m, \* l1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP
8 b# i* H j o8 P; Q1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case
2 n& O* g: K2 r# c4 _" f1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL" l4 P2 ^8 I+ G" _# l( F4 r% M
1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.
5 p) V/ {7 m/ R8 W1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added
( S& V7 Y: Z) [& ]7 G2 u1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps& v8 a a R. x. F; V$ Q7 h
1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail
% [3 `+ l$ Y$ d! a& S% R/ q# _1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block |
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发表于 2013-6-17 08:20
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