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cadence SPB 16.5下载地址（Hotfix更新至044）
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Cadence最新版软件SPB 16.5及其Hotfix下载链接如下：6 o& U b( B9 _- l
http://dl.vmall.com/c0sfvdb4yy! F0 G0 @0 Z6 y: A
% |; p# c. f+ {+ }! EHotfix中只需要安装最新的版本即可。
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0 h, h( g4 R3 k, _" ?( c; f$ dDATE: 06-7-2013 HOTFIX VERSION: 0445 J3 D1 p1 p% ]
===================================================================================================================================
( @6 f! c* e' A* B# [6 Z# OCCRID PRODUCT PRODUCTLEVEL2 TITLE
% J6 J) L' @* e) l* M===================================================================================================================================
: u1 ^9 {1 c5 T1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers
! L! I& [* ?8 t+ Z1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer+ \+ ^) h8 F: \/ O, a3 _& T
1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB$ ^' h3 ^2 O, y) h% O( L7 E
1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr.1 X. s% C0 G L
1106900 concept_HDL COMP_BROWSER Component Browser peRFormance utility should honor CPM directives for include and exclude PPT# y! ~" ^1 J d! h4 h
1110323 APD DXF_IF DXF out is offsetting square discrete pads.
& ^/ R4 N8 v: f7 M1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files
1 ?1 c; B0 r, {' E7 v7 q- G1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
& m- m. k( i6 l+ {- r/ P1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening.
8 I1 D+ V5 H: Z/ Y2 Q- e1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically
9 ]- t3 b5 G% V& X P1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one
- R- C9 u) U6 T& K3 [1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board
3 a$ q% D0 N' r7 {$ I1124544 CONCEPT_HDL CORE About Search History of find with SPB16.5. g5 u# b. t# @% w# N1 J
1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux* ?7 T. V" N" y6 a7 }3 A
1125628 CONCEPT_HDL CORE Crash on doing save hierarchy8 x, K1 n- S- E2 X, w$ y
1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.# m1 s/ D0 m# K3 i1 g; ]6 E
1130945 SCM SCHGEN SCM Export Schematic does not copy all cells in the library9 a6 G3 d( `0 k2 M
1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction.
* Z: C: B* B: M3 f1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters5 M& N/ b. O9 ]2 J6 U
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
; }% T' d& ^- ]& j1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.
' ^- o6 [3 l4 L1 ?. m' @1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command.
+ k/ `% J' M2 r& w1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder.
x- Q" K# E* N- ], ~1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top7 M. }' ^# C8 A
1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode.& |3 [( M6 z& |
1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.; g2 H2 K9 P. s& z2 B; c" @7 X
1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property, W" j7 c+ x: Q" y! m5 A
1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs
6 t* }/ n/ y- C) b( g: C! Y1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness( u% L$ _/ l% j3 j
1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped5 @' f+ m( h% |9 _% a' _+ e
1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero2 U J9 c/ e8 z4 H
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
% a5 p/ B$ l! R: F) Y1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed
1 ~* G* [ t% U g1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP
. L) o8 D b! D; N* M6 y1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case+ q: F1 p N# w* B B2 ~/ I% O
1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL
8 ~2 {0 m+ E7 v; g6 A1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed. z- S; y8 W6 Z
1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added8 N2 j* ?+ q& h) V0 o* O! J
1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps
" I2 b4 R# x; X& ^& ]& p$ d q1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail
2 K& @+ f- S! I3 U. I+ m0 R7 t1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block |
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发表于 2013-6-17 08:20
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