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cadence SPB 16.5下载地址（Hotfix更新至044）
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Cadence最新版软件SPB 16.5及其Hotfix下载链接如下：3 Y" p: v+ S: Z- b# Z" C8 O
http://dl.vmall.com/c0sfvdb4yy
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4 Y# Q& a# F8 |) J# j: hHotfix中只需要安装最新的版本即可。* h3 e4 m8 k) c
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DATE: 06-7-2013 HOTFIX VERSION: 044
0 c0 |+ A( m6 A7 M6 U===================================================================================================================================: b# ^# r0 w/ @" z8 G+ L- P" \: U
CCRID PRODUCT PRODUCTLEVEL2 TITLE; n1 g9 h- a# Z6 `/ h0 {9 k" A" @
===================================================================================================================================
- ?9 Z4 d1 X7 m {4 {3 [4 J2 G1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers
; V; x7 ~/ |# W4 }+ l5 w5 d* Z1084716 allegro_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
6 a0 V8 @/ p! o/ V/ V9 i1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB; x4 {- `2 w1 I. V/ D# b
1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr.3 @, g7 K* I5 J2 v
1106900 concept_HDL COMP_BROWSER Component Browser peRFormance utility should honor CPM directives for include and exclude PPT6 b) N: q& c. a: ~
1110323 APD DXF_IF DXF out is offsetting square discrete pads.
: U6 \" K: n7 }8 `1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files/ A/ G" t0 y' @$ m. H
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
7 g2 w+ {. T1 @4 Q1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening.& t! W' t5 |% ^: ~- H
1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically2 K- v4 x a8 {9 E# a9 u
1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one) R7 ?' ^4 S( s7 \9 ?" o+ o
1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board! G# J! w1 K/ r. @1 j$ i. X& b
1124544 CONCEPT_HDL CORE About Search History of find with SPB16.5+ Y1 T" |6 M5 F0 M
1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux8 L: L( n- H; ~. J7 V
1125628 CONCEPT_HDL CORE Crash on doing save hierarchy+ o2 I% Y+ W D5 c0 j
1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.
2 d. l" @' @& Q8 j. L, i' n6 p1130945 SCM SCHGEN SCM Export Schematic does not copy all cells in the library
/ V& k8 j# Y" y0 }/ V! r! M1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction.3 Y; N C$ w- |7 P5 ?. G( B
1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters
# B5 L4 Q6 M! D1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
, {8 S7 d: m3 a0 S; l1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.' o# o4 s6 b1 V: D& Z9 W
1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command.+ h" u- r+ c# z' @
1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder.
& ~% T8 j3 ]- r" b# I1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top- `5 d1 J$ ]4 Q X7 u7 }
1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode.
* P/ b& X6 a, j; c" w# L1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.& S1 E% o5 r5 l2 l
1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property
1 L+ Q2 P6 \+ x1 W& R1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs7 u2 ]6 ^* O- p/ F1 s! w
1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness
, D; }) [2 S0 n1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped% l# z" I: L- W
1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero
6 A8 z- q0 U) \* p& _. i1 }1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
6 \/ u2 d9 m5 s( }# d& g1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed# k8 p3 \; Z+ u$ q7 i# [; q0 Z8 W
1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP# _: E5 Z0 M* o8 v) v. {
1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case
2 m- N' [0 I6 w# b1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL
& T9 i: Z5 \4 \# i V1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.
' L" h* \) O* @% L1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added, h. p: q& j3 y3 T' T+ N0 e8 N7 i6 j
1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps
0 a$ I! U$ e( {8 I/ D1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail: d4 i; {9 K( v
1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block |
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发表于 2013-6-17 08:20
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