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本帖最后由 紫菁 于 2017-9-14 14:13 编辑
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cadence SPB orcad 16.5 最新的升级补丁，版本号16.50.47，修正内容如下：, K m ~8 `5 O2 h1 A7 U
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DATE: 09-6-2013 HOTFIX VERSION: 047
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1095533 concept_HDL CORE changing visibility for $PNN results in crash in windows mode
2 R- P0 V K# h, V1153813 CONCEPT_HDL CORE Spaces should not be allowed in the signal name entry form
2 I: J* u& p" Z0 v9 G1156102 PCB_LIBRARIAN CORE PDV severe peRFormance degradation on Linux platform makes PDV counter productive after some time! a4 |- {4 s/ f, G0 i6 q3 a [
1161781 CONSTRAINT_MGR CONCEPT_HDL SigXp crash when selecting ECset in design
' B4 T; y0 o6 e o; C3 p8 y1163709 CONCEPT_HDL CONSTRAINT_MGR Loosing Diffpairs when reimport block or restore from definitioin+ m6 X. c' c- f1 P F& n
1167887 F2B OTHER Improve message on symbol to schematic generation) m+ ?$ X B9 r# u
1168496 allegro_EDITOR SCHEM_FTB Export Physical Crashes when netreving the board' B9 N6 W9 J/ Q/ s- l8 c9 i% u" _8 l
1168830 ALLEGRO_EDITOR DRC_CONSTR missing DRC-marker for package to package check
0 A, T( v1 c i* d2 y W1169593 CONCEPT_HDL PDF Published PDF file\'s hyperlinks do not work fine when user click 1D10 or 2A10.
' c% [ k6 q7 @ _% A1169984 F2B PACKAGERXL Error Mapping cset when packaging but not in CM Audit+ a! M" Z z: z# R3 F/ J, g
1171136 CONCEPT_HDL CORE Page Number should also be displayed in Import Design Window.
' a/ [) R/ _4 s: q/ f q0 o# z1172597 ALLEGRO_EDITOR DATABASE Board cannot be unlocked using Password used while locking- r- R; ~* b" n/ U# Q6 y4 g
1172938 ALLEGRO_EDITOR PLOTTING Export IPF probrem
5 G3 P/ z m0 \' t6 h0 p; D1173183 ALLEGRO_EDITOR DRC_CONSTR Undesired Same net DRC for overlapping Pin and Via
z8 ~! P6 ]2 y! {6 k0 n6 a- P5 U+ q, C1173829 ALLEGRO_EDITOR MANUFACT Backdrill completes even though a stub exceeds the MAX_PTH_STUB value
1 C/ `3 Y' W2 A/ E1178972 CONSTRAINT_MGR ANALYSIS The Cross-Section\'s parameters was not applied immediately after importing a DCF on the Constraint Manager.
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发表于 2013-9-11 09:53
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发表于 2017-11-15 10:52
