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cadence SPB orcad 16.60.016 Hotfix | 853 mb( t5 |6 w, y* U2 t
DATE: 09-27-2013 HOTFIX VERSION: 016
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===================================================================================================================================7 P& h8 _' X8 d' ?1 A7 C
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CCRID PRODUCT PRODUCTLEVEL2 TITLE1 F5 o! L, z( V* f6 o8 g
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===================================================================================================================================
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548538 CAPTURE NETLIST_allegro Enhancement:Include mechanical parts in Allegro netlist
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0 H E h4 {2 Z1076579 CAPTURE GENERAL Display value only if value exists C( v- P, @' M* ]8 C
$ r, b: i" E9 \. e* g1083904 FSP GUI Need Filter in Change FPGA dialog to select desire FPGA from the long list.3 ?6 g, o0 \2 N" X6 T$ d
% w, p# C( n& y; `" B/ b5 S1089313 ALLEGRO_EDITOR INTERFACES Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility# ^4 j b+ F6 c8 Z* `) H$ Y
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1095728 ALLEGRO_EDITOR EDIT_ETCH Slide to grab adjacent elements when extend selection is enabled
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1102698 SIG_INTEGRITY ASSIGN_TOPOLOGY ECset will map on single ended nets but fails when the two nets are define as a diff pair./ G% v! p/ x. R* m& u5 d9 I6 Y% A
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1104071 SIG_INTEGRITY REPORTS Shape Parasitic value changes for bottom shape for changes in top shape
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) F& \. z3 F0 `5 `5 ]& f1117731 FSP POWER_MAPPING Ability to sort in Power Regulator forms8 ^) o( {" q5 P$ K. {
% ]; N. v! L5 g O1121539 FSP CONFIG_SETTINGS Cannot configure special FPGA pins (temperature diodes)
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. p) R9 Q: z: b' c6 h) A1122721 FSP MODEL_EDITOR Partial copy-paste overwrites the complete cell in XML Editor
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1123238 FSP TERMINATIONS Report functionality for terminations defined in the complete design.
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; {1 [; D9 X( m8 w5 C3 t, X5 P5 O1123364 FSP GUI Clicking on column header should sort the column.# V4 \( S5 k7 ^) u( U* C
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1123403 FSP EXTERNAL_PORTS Improper checkbox selection for 緿o Not Connect?or 縀xternal Port?column' c4 g) y) _0 I# r- E
6 j0 V# K# O- r) G6 T1125611 concept_HDL OTHER display unconnected pin in schematic pdf.) T! G+ I2 ^; ]
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1129871 ALLEGRO_EDITOR INTERACTIV Wire Profile Editor can't read mcmmat.dat in working directory.# N' j% T% b( Q# z: y+ U& g( H
* h; a, l5 _9 y" Q1133688 ALLEGRO_EDITOR GRAPHICS Enhancement request to enable 3D Viewer to show STEP model from .dra file.# p; d; J$ g5 f8 d/ T
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1141747 ALLEGRO_EDITOR GRAPHICS 3D view dooesnot displays height if step_unsupported_prototype variable set, I- h; e$ U5 t& c# [% s3 S
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1142215 SIG_INTEGRITY SIMULATION PULSE_PARAM set on DiffPair wasn't used for designlink simulation.
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1142798 ALLEGRO_EDITOR INTERFACES Step file output is incorrect in step viewer when composed of arcs and line.( l4 r, f7 u; X
+ V8 B- ~4 P+ D& Z1142894 FSP GUI Ability to RMB on a header and select `Hide Column?
2 \6 y7 B. H, w1142940 FSP EXTERNAL_PORTS Issue with checking/unchecking "Do not connect" and "External port" cells" @9 r# H3 D( O' y$ W) O
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1142949 CONCEPT_HDL skill Usage of "Preferences > License Settings?in FSP" @( G" `6 A7 `' m/ d% u
' [ y7 [5 m" e) Z9 w1143091 SIP_LAYOUT SYMB_EDIT_APPMOD symed: When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract8 _0 r9 Q- }4 u" V Z( w
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1144371 CONCEPT_HDL COMP_BROWSER Component Browser search results are inaccurate n$ S! }+ n3 U) J. ?# A+ N% V6 B- c
7 N7 M U) c6 Y1 j& h* p2 P' G1145033 ALLEGRO_EDITOR PLACEMENT When aligning components with options in Placement mode displays no busy indicator
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% a2 _/ Z( y0 K' z) P% B1145286 CONCEPT_HDL CORE Directive required for switching off the console
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4 D- Q2 R* y. {4 s# S* w2 w1145800 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl.+ z% S% F. L" _+ v. U1 V
) [% h2 ?" ]6 ^; z( ]: J1147899 ALLEGRO_EDITOR SHAPE Autovoid two overlapping shapes that share the same net
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1149996 ALLEGRO_EDITOR EDIT_ETCH Routing does not follow the ratsnest 'pin to pin'.$ _' u0 q' H+ K0 W8 _9 G/ ?; g
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1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.* |1 U, K% x- h
8 ^9 z0 D7 g, w0 k$ c3 g H1152577 ALLEGRO_EDITOR DATABASE slide removes cline seg$ q. ?/ @; l$ U8 F
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1152751 CONCEPT_HDL CORE Option to double-click and copy the Netname) Z6 ~: _! K( R) c: k! j
+ E. {2 g- y& ]1153220 ALLEGRO_EDITOR INTERFACES ENH: option to supress header/footer during PDF Export
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+ J6 B4 ^# }, Z5 |2 d% L& P- k1153625 ALLEGRO_EDITOR INTERFACES If Symbol has place bound bottom, the step model shows incorrect placement.. W' f) L. V( b o( W
) ~& R8 A0 O0 R' j1153813 CONCEPT_HDL CORE Spaces should not be allowed in the signal name entry form: ~/ S( @1 e4 w, d
" p# \& z, X, _1153857 CONCEPT_HDL CORE Changing different power symbol should maintain the schematic level properties.
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0 I$ E5 ], j8 N4 e( E1155161 CONCEPT_HDL CORE Add Signal name: Suggestion box overlaps with the typed signal name that is typed* E7 x& ^5 o: d4 T5 G; e
% x' P1 E# `5 o$ p/ j1155922 CONCEPT_HDL OTHER How can I use the batch mode for PDF Publisher and print a variant overlay?7 j# E6 M4 P& R6 T
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1156858 ALLEGRO_EDITOR pads_IN PADS Translator: Missing drill on square PTH padstack6 D: H3 {! b+ v
" Y' E4 I/ \" Q/ O7 p/ [ w& N% J1157362 APD 3D_VIEWER Need a way to color multiple nets in 3D viewer from APD/SiP.: w( | _" M1 B S3 V$ B
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1158130 CONSTRAINT_MGR ANALYSIS Constraint Manager do not display the Cumulative Result in Reflection Simulation
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! r. M. O5 o' `/ j' d* A1158210 ALLEGRO_EDITOR SHAPE SIP Layout happens crash while users move the shape with route keep-out
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) A3 v4 A d2 ]0 _* O1158452 SIG_INTEGRITY GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle
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* n9 z4 K' n6 g$ d" k7 o! y- w1158827 ALLEGRO_EDITOR EDIT_ETCH Slide a via in pad automatically add cline back to via to pin.+ r$ n* P( j' w L3 O6 _) F
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1158871 PCB_LIBRARIAN IMPORT_CSV PIN TEXT is not automatically added when importing the .csv file
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6 _$ f: p* T! }* {2 d' Z8 [/ K; g2 Y1159738 ALLEGRO_EDITOR INTERACTIV Selecting the Cancel button in the Text Edit command does not cancel the text.
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1159878 SIG_EXPLORER OTHER Ecset mapping dont follow topology template
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1159971 ALLEGRO_EDITOR MANUFACT Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file
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o* o3 \1 {! D+ A* K1160017 SIP_LAYOUT DIE_ABSTRACT_IF Add text to clarify shrink operation5 g$ ]9 ?. E* J
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1160507 APD EDIT_ETCH Script not playing back what was recorded when sliding lines/ H& \. ], i% M# z# ~$ P
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1161261 ADW TDO-SHAREPOINT Schema for TDO-SP fails on Japanese OS& {; w3 @' `6 t" M% o6 c* i) M1 n
8 l9 w, W% T. {* V; s' s1161538 CONCEPT_HDL CORE Espice model value edited in DE HDL & then netlisting done, but it doesnt changes the earlier assigned model in Allegro
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7 `) U, F, k. G. V% T C8 S1161636 ALLEGRO_EDITOR DRAFTING need new function for PDFout : hatching shape$ m2 K. ~: [: @8 S3 P9 J9 N
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1161777 ALLEGRO_EDITOR OTHER default line width for PDF output
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+ o; Z$ |" o9 Q' K @6 d1162383 CONCEPT_HDL CHECKPLUS Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.
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' \) k7 p- ^# g3 L: ~7 e1162562 CAPTURE STABILITY Capture crash on second attempt of Pspice netlist creation in 16.6
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1162629 FSP PROCESS "Load Process Option" under Run does not work properly' j) [9 s3 k m7 a- S, f" e
- V( r. g" D' n: F1162686 CONCEPT_HDL CORE Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE0 C, o$ i" _0 O% p8 i- b
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1163149 ALLEGRO_EDITOR DATABASE Autosilk creates Illegal arc to corrupt database
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1163439 ALLEGRO_EDITOR COLOR Duplicate Views Listed in Visibility Tab.7 c, _) N1 Y0 i. |
# h+ K% [4 Y: y4 y: |$ {, V6 Z1163521 CONCEPT_HDL COMP_BROWSER System Architect crahes on replace' I/ A4 w* q) p7 B) a* Q
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1163709 CONCEPT_HDL CONSTRAINT_MGR Loosing Diffpairs when reimport block or restore from definitioin
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- N# G( ^- D5 J9 D1163902 APD EXPORT_DATA Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?/ D# k- m s+ P2 I
' }6 g) l+ N2 P7 f$ R" Z) q# f: e1164337 CONCEPT_HDL CORE Cannot delete attribute filter value in PDF > General > Attribute Filter list
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8 F' a Q0 M7 b5 m( }" l' j F1164365 ALLEGRO_EDITOR INTERACTIV Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol
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1164769 APD VIA_STRUCTURE The replace via structure command does not accept a single canvas pick.# v P" o) S) R |" T
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1165026 ASI_SI GUI EMS3D exist in Via Model Setup of SI base.. S5 l) E. q, s0 O% S' Z
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1165561 CAPTURE DRC File > Check and Save clears waived DRCs, W) I5 [+ h9 _ U% Z
3 E' H4 I1 O8 H1165631 CAPTURE STABILITY Capture crash in the hierarchy tab of Project Manager window. l5 h: n; ^/ P* ~7 b8 d- R; B( m
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1165836 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)
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2 b# a% u. O- d& D1 p3 H! g1165911 FSP PROCESS Editing group name in protocol causes incorrect Process option checked
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) b' G3 }+ A" Q& @1166026 ALLEGRO_EDITOR DATABASE Running DB Doctor removes net name from vias
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1166034 SIP_LAYOUT OTHER SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle( F" w/ p+ C, c' r9 d9 v4 a8 e0 j
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1166074 GRE CORE GRE crashes during planning phases
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6 f; i3 {# J* j3 z2 _1166319 ALLEGRO_EDITOR PLACEMENT Swap not succeed U% }$ L- ~* I
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1166484 SIP_LAYOUT WIREBOND Bondfinger "Align With Wire" problem during move: }1 {# S/ c$ p* q2 s. ~5 `
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1166530 ALLEGRO_EDITOR INTERACTIV Bug: Mirror in Placement Edit resets the options tab for Edit > Move* S9 i% S- d# b' a6 K) j2 A
2 j" ]- j# p! X% I& I: S+ ^4 Z" w1166819 CONCEPT_HDL CORE Cadence DEHDL Text Size Issue
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0 h9 }8 X: K6 B9 s% c& G1167847 CAPTURE PROPERTY_EDITOR Implementation name length greater than 31 character causes capture crash
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n! L8 u) r" J( I" U" ^1167887 F2B OTHER Improve message on symbol to schematic generation
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1168369 F2B DESIGNVARI Variant don縯 appear in increasing order while Annotate.
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1168629 APD OTHER Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD
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1168678 ALLEGRO_EDITOR NC Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.
# X# o9 w3 m: ]
" ^* Q7 S8 v3 z$ l7 ?1168798 ALLEGRO_EDITOR INTERACTIV Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk# B' E! n2 |! u8 v
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1168830 ALLEGRO_EDITOR DRC_CONSTR missing DRC-marker for package to package check
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1168864 ALLEGRO_EDITOR CREATE_SYM Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty
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0 j* {3 D% F8 n* T/ ~0 E0 h1169213 PSPICE SIMULATOR Parametric sweep is giving incorrect reuslts
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1169436 FSP FPGA_SUPPORT Add support for Cyclone V CSX and CST parts
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1170108 ALLEGRO_EDITOR INTERACTIV Enhancement to preserve Rat T location for Topology assigned schedule" E1 b6 F4 v* x$ K: G9 L" w
4 Z3 V5 `( X9 X5 J0 b4 `1170313 SIP_LAYOUT LOGIC scm adding additional pin names and unassigned property to codesign die chips file5 A# M$ ?) B0 I6 g- ^, g$ m
# I# q2 d" O A6 c" J- T1171136 CONCEPT_HDL CORE Page Number should also be displayed in Import Design Window.0 c1 h6 r9 w/ c3 A( X
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1171747 ALLEGRO_EDITOR PLACEMENT Allegro crashes when doing a gate swap between components
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1172183 ALLEGRO_EDITOR INTERACTIV Alignment modules fails on equal spacing
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1173183 ALLEGRO_EDITOR DRC_CONSTR Undesired Same net DRC for overlapping Pin and Via( k. O# m4 l+ q% \1 ~; q, t6 u1 [
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1174067 ALLEGRO_EDITOR DRC_CONSTR Soldermask to shape drc does not show if the layer is a PLANE.
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1174338 ALLEGRO_EDITOR PLACEMENT preview has rotated pads
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1175307 CONSTRAINT_MGR ANALYSIS CMGR fails to report RPD DRC for accuracy 4 - mm* h% U- _3 H7 [& Y" }; t/ N
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1175537 ALLEGRO_EDITOR REPORTS net loop report crashes Allegro. Design specific) }1 z7 N1 } s3 p6 k% [
0 I. T8 b! |& u" w1176126 ALLEGRO_EDITOR INTERFACES 3D viewer doesnot change models units dynamically+ y! M+ f9 ?1 j3 h: y: c
+ d' \7 a' O; H1176281 CONCEPT_HDL CORE Option to Auto-hide excluded modules7 W9 ]7 i% q4 P7 f
9 {/ k/ k* [2 _1 t- r1176413 ALLEGRO_EDITOR MANUFACT Q - testprep parameter settings is not retained, what could be the cause..
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9 r! O+ O9 p f1176791 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl
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1178052 ALLEGRO_EDITOR SHAPE SIP crashes during shape degassing.! ?2 Y3 K7 J0 B& \# G
5 J! E6 p& _' H, n1178158 ALLEGRO_EDITOR INTERFACES Export step file creates step file of same height$ X0 e( [ O" @4 }
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1178201 ALLEGRO_EDITOR GRAPHICS Large oval pads rendered as oblong hexagons in the 3D viewer x9 ~, i3 F/ v1 x' ~: G# ]
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1178671 ALLEGRO_EDITOR GRAPHICS 3D Viewer in package symbol editor not displaying correct place bound shapes.
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1178725 ALLEGRO_EDITOR OTHER With fillets present, rat lines do not point to the closest endpoint.
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' C, m& P/ L% i4 B% ?0 B( k1178972 CONSTRAINT_MGR ANALYSIS The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.& X( G# k/ k& X; b
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1179093 ALLEGRO_EDITOR SHAPE Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas.
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1179109 ALLEGRO_EDITOR OTHER DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version: F2 J+ V# Z7 c3 G2 I- o \
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1179571 ALLEGRO_EDITOR ARTWORK Artwork crash and artwork log report Aparture missing6 L8 v, o7 k) e( c3 m
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1179636 SPECCTRA ROUTE Route Automatic will not start if NET_SHORT are attached to a mec-pin
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1179659 SIP_LAYOUT DIE_EDITOR die edit on co-design die losing c4 bumps
* S/ ?7 {2 g. H7 p2 {% \& `2 u+ W% k0 n: A- a
1180306 ALLEGRO_EDITOR ARTWORK When trying to create Artwork the tool crashes with no error messages just a little X box! ]( p2 U) C' B
1 p( t' g4 f- t& r1180573 ALLEGRO_EDITOR ARTWORK If one layer has warning, all artwork films are "created with warning".
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1180960 SIP_LAYOUT PLACEMENT swap function is not swapping logical paths in sip layout!9 e6 |# ~! v9 Z; Q0 Z! f
z& p! B4 T/ Y( C( ~
1182534 ALLEGRO_EDITOR SKILL axlLayerPrioritySet() not working with v166 s013 and up
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, U( s% ]+ Q3 p& w. I$ N- a1182560 ALLEGRO_EDITOR PLOTTING Creating plot 2nd time casues Allegro to crash6 Z2 T1 q! ~& s- u7 ~* `6 a, L
7 n; M- d2 d* b
1182616 ALLEGRO_EDITOR PLACEMENT Application crashes when attempting to place a high pin count BGA" Z) M2 ^8 z0 ^) \/ E/ _- M5 C, C
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1183752 CONCEPT_HDL CORE Unable to modify location properties within a read-only hierarchical block4 r& w1 x$ ]' A8 Q' b2 ]
) ?5 J1 J* S9 f1183774 SIP_LAYOUT DIE_EDITOR Die Refresh hangs* Z2 G) L) l7 Y* L
; I o2 m. D, w" T& w1184178 CONCEPT_HDL CONSTRAINT_MGR Ecset xnet members lost from electrical class when restore from definition of subblocks7 `/ ?1 R* o) C
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1184787 ALLEGRO_EDITOR EDIT_ETCH Allegro SPB166 s 015 crashes during normal add connect function.
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0 p. r* i, U8 [5 p
Cadence SPB OrCAD 16.60.016 Hotfix/ |# t# p) Z6 u0 w
& g: x" t r* LDownload uploaded: J9 G' I. d$ G. ^
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$ H8 A' O1 A R: pDownload filefactory( Z0 {2 ?& @- c; O( m% a5 b* ]
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发表于 2013-10-5 20:59
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