Cadence SPB OrCAD 16.60.016 Hotfix

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cadence SPB orcad 16.60.016 Hotfix | 853 mb
DATE: 09-27-2013   HOTFIX VERSION: 016
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& x2 `/ Q4 @3 Q( q% D* ?7 |===================================================================================================================================

$ M! c9 Q- O" A0 D7 ZCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
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9 x% K* t; ]+ ~8 g' d2 v===================================================================================================================================
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548538  CAPTURE        NETLIST_allegro  Enhancement:Include mechanical parts in Allegro netlist

( |1 K1 x' r7 F! y' c1076579 CAPTURE        GENERAL          Display value only if value exists
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1083904 FSP            GUI              Need Filter in Change FPGA dialog to select desire FPGA from the long list.

# l  M7 V! }3 Z+ y" Y; x1089313 ALLEGRO_EDITOR INTERFACES       Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility
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  R" u2 P$ T: N2 ^1095728 ALLEGRO_EDITOR EDIT_ETCH        Slide to grab adjacent elements when extend selection is enabled
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' l- x4 }6 U" V5 a6 H/ ]- ~# \8 L1102698 SIG_INTEGRITY  ASSIGN_TOPOLOGY  ECset will map on single ended nets but fails when the two nets are define as a diff pair.
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1104071 SIG_INTEGRITY  REPORTS          Shape Parasitic value changes for bottom shape for changes in top shape

1117731 FSP            POWER_MAPPING    Ability to sort in Power Regulator forms

1121539 FSP            CONFIG_SETTINGS  Cannot configure special FPGA pins (temperature diodes)

' [5 a6 w; V. H1 \1122721 FSP            MODEL_EDITOR     Partial copy-paste overwrites the complete cell in XML Editor

% j% @, h& M0 S5 }+ A. p1123238 FSP            TERMINATIONS     Report functionality for terminations defined in the complete design.

1123364 FSP            GUI              Clicking on column header should sort the column.
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1123403 FSP            EXTERNAL_PORTS   Improper checkbox selection for 緿o Not Connect?or 縀xternal Port?column
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1125611 concept_HDL    OTHER            display unconnected pin in schematic pdf.

1129871 ALLEGRO_EDITOR INTERACTIV       Wire Profile Editor can't read mcmmat.dat in working directory.
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0 F- U8 N0 C: G1133688 ALLEGRO_EDITOR GRAPHICS         Enhancement request to enable 3D Viewer to show STEP model from .dra file.
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1141747 ALLEGRO_EDITOR GRAPHICS         3D view dooesnot displays height if step_unsupported_prototype variable set

1142215 SIG_INTEGRITY  SIMULATION       PULSE_PARAM set on DiffPair wasn't used for designlink simulation.

1142798 ALLEGRO_EDITOR INTERFACES       Step file output is incorrect in step viewer when composed of arcs and line.

8 @# Y4 e8 B4 X& O' c1 p% l1142894 FSP            GUI              Ability to RMB on a header and select `Hide Column?
5 ^" x) k! u3 k- v1142940 FSP            EXTERNAL_PORTS   Issue with checking/unchecking "Do not connect" and "External port" cells

1142949 CONCEPT_HDL    skill            Usage of "Preferences > License Settings?in FSP

1143091 SIP_LAYOUT     SYMB_EDIT_APPMOD symed:  When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract

0 o- `( T: q+ C7 h- J1144371 CONCEPT_HDL    COMP_BROWSER     Component Browser search results are inaccurate
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6 V6 Y, I+ l. N" O1145033 ALLEGRO_EDITOR PLACEMENT        When aligning components with options in Placement mode displays no busy indicator
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4 s- f0 p7 W* s, f) U2 r6 z1145286 CONCEPT_HDL    CORE             Directive required for switching off the console

1 g9 v. S% \! N% H' Z- J1145800 ALLEGRO_EDITOR GRAPHICS         Spurious odd lines are shown in shapes and text that are not part of the design with opengl.

  n9 y& d- z8 y! K; V1147899 ALLEGRO_EDITOR SHAPE            Autovoid two overlapping shapes that share the same net

! j% i( v2 i, q1149996 ALLEGRO_EDITOR EDIT_ETCH        Routing does not follow the ratsnest 'pin to pin'.

% a' s' [8 Z4 w9 g  o1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.
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1152577 ALLEGRO_EDITOR DATABASE         slide removes cline seg

1152751 CONCEPT_HDL    CORE             Option to double-click and copy the Netname
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1153220 ALLEGRO_EDITOR INTERFACES       ENH: option to supress header/footer during PDF Export
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, w$ K! F3 j; b# Z0 l1153625 ALLEGRO_EDITOR INTERFACES       If Symbol has place bound bottom, the step model shows incorrect placement.
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1153813 CONCEPT_HDL    CORE             Spaces should not be allowed in the signal name entry form

; X" [; D" Q) \2 ]2 ?; O1153857 CONCEPT_HDL    CORE             Changing different power symbol should maintain the schematic level properties.

) }4 ^  `5 U) x9 k- S7 W1155161 CONCEPT_HDL    CORE             Add Signal name: Suggestion box overlaps with the typed signal name that is typed

) }, @' a% |! u1155922 CONCEPT_HDL    OTHER            How can I use the batch mode for PDF Publisher and print a variant overlay?

1156858 ALLEGRO_EDITOR pads_IN          PADS Translator: Missing drill on square PTH padstack

1157362 APD            3D_VIEWER        Need a way to color multiple nets in 3D viewer from APD/SiP.
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2 {5 _# _) Y( e; D' i% D1158130 CONSTRAINT_MGR ANALYSIS         Constraint Manager do not display the Cumulative Result in Reflection Simulation
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1158210 ALLEGRO_EDITOR SHAPE            SIP Layout happens crash while users move the shape with route keep-out

1158452 SIG_INTEGRITY  GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle

2 @+ D  [* i2 ]1158827 ALLEGRO_EDITOR EDIT_ETCH        Slide a via in pad automatically add cline back to via to pin.

1158871 PCB_LIBRARIAN  IMPORT_CSV       PIN TEXT is not automatically added when importing the .csv file

2 u' M0 w5 [- ?# a+ e2 C- K1159738 ALLEGRO_EDITOR INTERACTIV       Selecting the Cancel button in the Text Edit command does not cancel the text.

1159878 SIG_EXPLORER   OTHER            Ecset mapping dont follow topology template

1159971 ALLEGRO_EDITOR MANUFACT         Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file
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1160017 SIP_LAYOUT     DIE_ABSTRACT_IF  Add text to clarify shrink operation

5 q6 `! G  d6 @1160507 APD            EDIT_ETCH        Script not playing back what was recorded when sliding lines

/ t  T$ F- {! ^5 v7 I1161261 ADW            TDO-SHAREPOINT   Schema for TDO-SP fails on Japanese OS

1161538 CONCEPT_HDL    CORE             Espice model value edited in DE HDL  & then netlisting done, but it doesnt changes the earlier assigned model in Allegro

1161636 ALLEGRO_EDITOR DRAFTING         need new function for PDFout : hatching shape
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! N  i; S5 N' y1161777 ALLEGRO_EDITOR OTHER            default line width for PDF output
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1162383 CONCEPT_HDL    CHECKPLUS        Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.
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; d: |$ u' M9 P/ Y  R) u1162562 CAPTURE        STABILITY        Capture crash on second attempt of Pspice netlist creation in 16.6

1162629 FSP            PROCESS          "Load Process Option" under Run does not work properly

1162686 CONCEPT_HDL    CORE             Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE
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8 r9 @- e/ L& e# P- k/ Y1163149 ALLEGRO_EDITOR DATABASE         Autosilk creates Illegal arc to corrupt database

1163439 ALLEGRO_EDITOR COLOR            Duplicate Views Listed in Visibility Tab.
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1163521 CONCEPT_HDL    COMP_BROWSER     System Architect crahes on replace

: N/ O8 G4 P: n& T& o1 S1163709 CONCEPT_HDL    CONSTRAINT_MGR   Loosing Diffpairs when reimport block or restore from definitioin
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1163902 APD            EXPORT_DATA      Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?

# e" @; g" K+ y) \5 O' x  y1164337 CONCEPT_HDL    CORE             Cannot delete attribute filter value in PDF > General > Attribute Filter list

1164365 ALLEGRO_EDITOR INTERACTIV       Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol
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; @! P/ A/ O" {0 @) {5 j4 [. |  Q1164769 APD            VIA_STRUCTURE    The replace via structure command does not accept a single canvas pick.

1 V& |$ Y0 a; c1165026 ASI_SI         GUI              EMS3D exist in Via Model Setup of SI base.

1165561 CAPTURE        DRC              File > Check and Save clears waived DRCs

1165631 CAPTURE        STABILITY        Capture crash in the hierarchy tab of Project Manager window
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1165836 SIG_INTEGRITY  GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)

1 Q7 ]5 p( \# r0 ~" R* `: L1165911 FSP            PROCESS          Editing group name in protocol causes incorrect Process option checked

1166026 ALLEGRO_EDITOR DATABASE         Running DB Doctor removes net name from vias
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1166034 SIP_LAYOUT     OTHER            SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle
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, p: x9 @2 C5 {$ m, N( W$ `1166074 GRE            CORE             GRE crashes during planning phases
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* i+ K3 t0 u9 d. H( ]1166319 ALLEGRO_EDITOR PLACEMENT        Swap not succeed

; l* s1 P, t! R/ k% {+ T1 |1166484 SIP_LAYOUT     WIREBOND         Bondfinger "Align With Wire" problem during move

6 r5 G5 V3 a6 ?7 E: }1166530 ALLEGRO_EDITOR INTERACTIV       Bug: Mirror in Placement Edit resets the options tab for Edit > Move
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1166819 CONCEPT_HDL    CORE             Cadence DEHDL Text Size Issue
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1167847 CAPTURE        PROPERTY_EDITOR  Implementation name length greater than 31 character causes capture crash
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. t; S; p  U+ Q/ x, W6 e1167887 F2B            OTHER            Improve message on symbol to schematic generation
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1168369 F2B            DESIGNVARI       Variant don縯 appear in increasing order while Annotate.

1168629 APD            OTHER            Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD
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4 b& w; D5 \3 z% n+ U1168678 ALLEGRO_EDITOR NC               Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.
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7 q& G7 P# y" u1 c, {/ w/ l: I1168798 ALLEGRO_EDITOR INTERACTIV       Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk

1168830 ALLEGRO_EDITOR DRC_CONSTR       missing DRC-marker for package to package check
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0 \: F! E5 E- i5 q1168864 ALLEGRO_EDITOR CREATE_SYM       Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty
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/ F5 k2 s5 x. I  u5 T5 V/ {, i1169213 PSPICE         SIMULATOR        Parametric sweep is giving incorrect reuslts

1169436 FSP            FPGA_SUPPORT     Add support for Cyclone V CSX and CST parts

1170108 ALLEGRO_EDITOR INTERACTIV       Enhancement to preserve Rat T location for Topology assigned schedule
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( v4 z* B4 B. J0 W1170313 SIP_LAYOUT     LOGIC            scm adding additional pin names and unassigned property to codesign die chips file
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3 D: r$ [$ c, B1 P# H: _1171136 CONCEPT_HDL    CORE             Page Number should also be displayed in Import Design Window.

1171747 ALLEGRO_EDITOR PLACEMENT        Allegro crashes when doing a gate swap between components

# P; W, k' A. Q  o, @1172183 ALLEGRO_EDITOR INTERACTIV       Alignment modules fails on equal spacing
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1173183 ALLEGRO_EDITOR DRC_CONSTR       Undesired Same net DRC for overlapping Pin and Via
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3 J% g0 q$ ?' i1174067 ALLEGRO_EDITOR DRC_CONSTR       Soldermask to shape drc does not show if the layer is a PLANE.

# V5 D/ Z5 \/ {1174338 ALLEGRO_EDITOR PLACEMENT        preview has rotated pads

1175307 CONSTRAINT_MGR ANALYSIS         CMGR fails to report RPD DRC for accuracy 4 - mm
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. X9 d# y! K, r& Q+ ]" `  O, Z1175537 ALLEGRO_EDITOR REPORTS          net loop report crashes Allegro. Design specific

1176126 ALLEGRO_EDITOR INTERFACES       3D viewer doesnot change models units dynamically
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1176281 CONCEPT_HDL    CORE             Option to Auto-hide excluded modules

1176413 ALLEGRO_EDITOR MANUFACT         Q - testprep parameter settings is not retained, what could be the cause..
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1176791 ALLEGRO_EDITOR GRAPHICS         Spurious odd lines are shown in shapes and text that are not part of the design with opengl

1178052 ALLEGRO_EDITOR SHAPE            SIP crashes during shape degassing.

1178158 ALLEGRO_EDITOR INTERFACES       Export step file creates step file of same height
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1178201 ALLEGRO_EDITOR GRAPHICS         Large oval pads rendered as oblong hexagons in the 3D viewer

1178671 ALLEGRO_EDITOR GRAPHICS         3D Viewer in package symbol editor not displaying correct place bound shapes.

6 p; ]. ?+ x( `7 p' }1178725 ALLEGRO_EDITOR OTHER            With fillets present, rat lines do not point to the closest endpoint.
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# K5 I% ]8 q8 G/ _/ u3 a  R5 d1178972 CONSTRAINT_MGR ANALYSIS         The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.
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0 |4 Z1 T3 x. F9 C1179093 ALLEGRO_EDITOR SHAPE            Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas.
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7 @8 Q) X% O! ~. u+ L$ N8 U1179109 ALLEGRO_EDITOR OTHER            DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version

1179571 ALLEGRO_EDITOR ARTWORK          Artwork crash and artwork log report Aparture missing

9 C  _9 Q* u. b8 e9 a* g! H1 G1179636 SPECCTRA       ROUTE            Route Automatic will not start if NET_SHORT are attached to a mec-pin
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2 F* |9 w8 l( k7 H; F7 [1179659 SIP_LAYOUT     DIE_EDITOR       die edit on co-design die losing c4 bumps
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1180306 ALLEGRO_EDITOR ARTWORK          When trying to create Artwork the tool crashes with no error messages just a little X box

+ Y8 K6 f, n  o8 i) W1180573 ALLEGRO_EDITOR ARTWORK          If one layer has warning, all artwork films are "created with warning".
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1180960 SIP_LAYOUT     PLACEMENT        swap function is not swapping logical paths in sip layout!
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1182534 ALLEGRO_EDITOR SKILL            axlLayerPrioritySet() not working with v166 s013 and up
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1182560 ALLEGRO_EDITOR PLOTTING         Creating plot 2nd time casues Allegro to crash
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1182616 ALLEGRO_EDITOR PLACEMENT        Application crashes when attempting to place a high pin count BGA

# A% }1 F. T# k; N6 f! P* r9 j1183752 CONCEPT_HDL    CORE             Unable to modify location properties within a read-only hierarchical block
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1183774 SIP_LAYOUT     DIE_EDITOR       Die Refresh hangs

- _$ V6 `" S/ A6 C/ `1184178 CONCEPT_HDL    CONSTRAINT_MGR   Ecset xnet members lost from electrical class when restore from definition of  subblocks
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% ?( B* Y% o0 Q2 E7 U0 i* E1184787 ALLEGRO_EDITOR EDIT_ETCH        Allegro SPB166 s 015 crashes during normal add connect function.
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- Y& Y  y' s) D0 K) U& CCadence SPB OrCAD 16.60.016 Hotfix
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$ _0 u6 d: s0 o3 m0 v( @, ?' ehttp://www.filefactory.com/file/6t9yiqdubs8t/n/ceenS1660016fi.rar
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molin

谢谢，请问下有没有打补丁 的方法？？

pxgood

长假回来就给力了 谢谢了！！！

inspiron1501

前几个补丁跳过了，这次看bug fix，修正了很多，也增强了很多功能，特别是step方面，测试一下，多谢分享！

allanwang

谢谢楼主分享！！！

wxmcumtb

顶。。。。。。。。。。

lgl2466