Cadence SPB OrCAD 16.60.016 Hotfix

suiwinder

cadence SPB orcad 16.60.016 Hotfix | 853 mb
DATE: 09-27-2013   HOTFIX VERSION: 016

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548538  CAPTURE        NETLIST_allegro  Enhancement:Include mechanical parts in Allegro netlist

5 M2 J$ k! I  j) M7 `5 f1076579 CAPTURE        GENERAL          Display value only if value exists
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1083904 FSP            GUI              Need Filter in Change FPGA dialog to select desire FPGA from the long list.
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, _0 a7 e8 K% y6 w+ u: |1089313 ALLEGRO_EDITOR INTERFACES       Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility

# Q! u' _+ H# U, ?3 ]5 [1095728 ALLEGRO_EDITOR EDIT_ETCH        Slide to grab adjacent elements when extend selection is enabled

1102698 SIG_INTEGRITY  ASSIGN_TOPOLOGY  ECset will map on single ended nets but fails when the two nets are define as a diff pair.
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# b% @$ \6 e& Y# N' L) S1104071 SIG_INTEGRITY  REPORTS          Shape Parasitic value changes for bottom shape for changes in top shape

( t8 B$ q. C% a( O9 z& e1 {1117731 FSP            POWER_MAPPING    Ability to sort in Power Regulator forms

- p" m0 x& U# }1 A4 \2 Q1121539 FSP            CONFIG_SETTINGS  Cannot configure special FPGA pins (temperature diodes)

9 z$ q4 _/ J7 b1122721 FSP            MODEL_EDITOR     Partial copy-paste overwrites the complete cell in XML Editor

0 h6 C8 y! Q. Y( J! P! n9 c' j1123238 FSP            TERMINATIONS     Report functionality for terminations defined in the complete design.

; X) J# t4 |) a1 q/ o; q1123364 FSP            GUI              Clicking on column header should sort the column.

/ i0 `# a, w6 N# z2 A, l# f8 B1123403 FSP            EXTERNAL_PORTS   Improper checkbox selection for 緿o Not Connect?or 縀xternal Port?column

1125611 concept_HDL    OTHER            display unconnected pin in schematic pdf.
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1129871 ALLEGRO_EDITOR INTERACTIV       Wire Profile Editor can't read mcmmat.dat in working directory.

- Z  V1 A  ]( `4 s! X5 E) r1133688 ALLEGRO_EDITOR GRAPHICS         Enhancement request to enable 3D Viewer to show STEP model from .dra file.
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1141747 ALLEGRO_EDITOR GRAPHICS         3D view dooesnot displays height if step_unsupported_prototype variable set

1142215 SIG_INTEGRITY  SIMULATION       PULSE_PARAM set on DiffPair wasn't used for designlink simulation.

1 Z/ j! [. a. S/ E1142798 ALLEGRO_EDITOR INTERFACES       Step file output is incorrect in step viewer when composed of arcs and line.

4 d7 T9 _, u" G, S5 Y1142894 FSP            GUI              Ability to RMB on a header and select `Hide Column?
1142940 FSP            EXTERNAL_PORTS   Issue with checking/unchecking "Do not connect" and "External port" cells

+ S2 V/ G: Q) r+ x- B1142949 CONCEPT_HDL    skill            Usage of "Preferences > License Settings?in FSP
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1143091 SIP_LAYOUT     SYMB_EDIT_APPMOD symed:  When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract
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& L3 L- ?: [- u1144371 CONCEPT_HDL    COMP_BROWSER     Component Browser search results are inaccurate
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1145033 ALLEGRO_EDITOR PLACEMENT        When aligning components with options in Placement mode displays no busy indicator
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1145286 CONCEPT_HDL    CORE             Directive required for switching off the console
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1145800 ALLEGRO_EDITOR GRAPHICS         Spurious odd lines are shown in shapes and text that are not part of the design with opengl.

1147899 ALLEGRO_EDITOR SHAPE            Autovoid two overlapping shapes that share the same net

1149996 ALLEGRO_EDITOR EDIT_ETCH        Routing does not follow the ratsnest 'pin to pin'.
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+ ^7 I. R( L# |% @1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.
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$ y+ C- F9 N8 e4 C1152577 ALLEGRO_EDITOR DATABASE         slide removes cline seg
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1152751 CONCEPT_HDL    CORE             Option to double-click and copy the Netname
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1153220 ALLEGRO_EDITOR INTERFACES       ENH: option to supress header/footer during PDF Export
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1153625 ALLEGRO_EDITOR INTERFACES       If Symbol has place bound bottom, the step model shows incorrect placement.

# z  o) D/ p# ^- J  m1153813 CONCEPT_HDL    CORE             Spaces should not be allowed in the signal name entry form

1153857 CONCEPT_HDL    CORE             Changing different power symbol should maintain the schematic level properties.

1155161 CONCEPT_HDL    CORE             Add Signal name: Suggestion box overlaps with the typed signal name that is typed

2 X: Y! N# V9 s- L% T, s1155922 CONCEPT_HDL    OTHER            How can I use the batch mode for PDF Publisher and print a variant overlay?
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1156858 ALLEGRO_EDITOR pads_IN          PADS Translator: Missing drill on square PTH padstack
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' k4 ~6 r3 y; O$ G5 F% l1157362 APD            3D_VIEWER        Need a way to color multiple nets in 3D viewer from APD/SiP.
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1158130 CONSTRAINT_MGR ANALYSIS         Constraint Manager do not display the Cumulative Result in Reflection Simulation
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1 n4 a6 H. v: I: X% W2 l. I1158210 ALLEGRO_EDITOR SHAPE            SIP Layout happens crash while users move the shape with route keep-out
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5 R3 ], V; ]5 Y5 z! y1158452 SIG_INTEGRITY  GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle

1158827 ALLEGRO_EDITOR EDIT_ETCH        Slide a via in pad automatically add cline back to via to pin.

1158871 PCB_LIBRARIAN  IMPORT_CSV       PIN TEXT is not automatically added when importing the .csv file
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1159738 ALLEGRO_EDITOR INTERACTIV       Selecting the Cancel button in the Text Edit command does not cancel the text.

" A5 ^. ]) H. h; S: e9 B0 b/ K5 ]1159878 SIG_EXPLORER   OTHER            Ecset mapping dont follow topology template
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  O  `9 t' b3 a) \1159971 ALLEGRO_EDITOR MANUFACT         Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file
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1160017 SIP_LAYOUT     DIE_ABSTRACT_IF  Add text to clarify shrink operation

1160507 APD            EDIT_ETCH        Script not playing back what was recorded when sliding lines

1161261 ADW            TDO-SHAREPOINT   Schema for TDO-SP fails on Japanese OS

4 N1 H& g# H& N/ l8 t9 ~, W* U& R! \1161538 CONCEPT_HDL    CORE             Espice model value edited in DE HDL  & then netlisting done, but it doesnt changes the earlier assigned model in Allegro

0 |( D- y3 `( Q1161636 ALLEGRO_EDITOR DRAFTING         need new function for PDFout : hatching shape
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1161777 ALLEGRO_EDITOR OTHER            default line width for PDF output

1162383 CONCEPT_HDL    CHECKPLUS        Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.
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1162562 CAPTURE        STABILITY        Capture crash on second attempt of Pspice netlist creation in 16.6

7 C. a5 b+ u( ?3 [0 f# }3 F1162629 FSP            PROCESS          "Load Process Option" under Run does not work properly
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9 q( s$ K2 ]$ C" R1162686 CONCEPT_HDL    CORE             Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE

1163149 ALLEGRO_EDITOR DATABASE         Autosilk creates Illegal arc to corrupt database
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1163439 ALLEGRO_EDITOR COLOR            Duplicate Views Listed in Visibility Tab.

3 ~& |' v, D, j% j+ z+ T1163521 CONCEPT_HDL    COMP_BROWSER     System Architect crahes on replace
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' P/ C; e# R" J8 y1163709 CONCEPT_HDL    CONSTRAINT_MGR   Loosing Diffpairs when reimport block or restore from definitioin

# r( M3 z* e+ n9 P1163902 APD            EXPORT_DATA      Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?

1164337 CONCEPT_HDL    CORE             Cannot delete attribute filter value in PDF > General > Attribute Filter list
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1164365 ALLEGRO_EDITOR INTERACTIV       Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol
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1164769 APD            VIA_STRUCTURE    The replace via structure command does not accept a single canvas pick.
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1165026 ASI_SI         GUI              EMS3D exist in Via Model Setup of SI base.
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1165561 CAPTURE        DRC              File > Check and Save clears waived DRCs
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1165631 CAPTURE        STABILITY        Capture crash in the hierarchy tab of Project Manager window

1165836 SIG_INTEGRITY  GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)
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$ B' d- G8 z5 t1165911 FSP            PROCESS          Editing group name in protocol causes incorrect Process option checked

& J9 M4 V% L5 M% M& s9 O! z% {. Q1166026 ALLEGRO_EDITOR DATABASE         Running DB Doctor removes net name from vias

1166034 SIP_LAYOUT     OTHER            SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle

1166074 GRE            CORE             GRE crashes during planning phases

/ j5 ]1 K5 C7 t& Z/ D( A6 \$ _1166319 ALLEGRO_EDITOR PLACEMENT        Swap not succeed

1166484 SIP_LAYOUT     WIREBOND         Bondfinger "Align With Wire" problem during move
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& y7 u3 z$ R$ I. E. ^1166530 ALLEGRO_EDITOR INTERACTIV       Bug: Mirror in Placement Edit resets the options tab for Edit > Move
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, @+ Z4 s1 q3 I+ C2 i& L1166819 CONCEPT_HDL    CORE             Cadence DEHDL Text Size Issue
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) v: J; h% W, G6 s# ^+ [' x. E/ m1167847 CAPTURE        PROPERTY_EDITOR  Implementation name length greater than 31 character causes capture crash
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1167887 F2B            OTHER            Improve message on symbol to schematic generation

  t/ ~1 e8 W( ^; X; b1168369 F2B            DESIGNVARI       Variant don縯 appear in increasing order while Annotate.

/ v, Y* r8 @+ z% t1 G) T0 |1168629 APD            OTHER            Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD

9 l' ?7 g4 h/ D+ W1 T4 X5 n. V1168678 ALLEGRO_EDITOR NC               Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.

1168798 ALLEGRO_EDITOR INTERACTIV       Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk
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1168830 ALLEGRO_EDITOR DRC_CONSTR       missing DRC-marker for package to package check

: Q* |" x# e+ p3 _1 y1168864 ALLEGRO_EDITOR CREATE_SYM       Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty
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1169213 PSPICE         SIMULATOR        Parametric sweep is giving incorrect reuslts

" i. Y; B* U0 B6 J1169436 FSP            FPGA_SUPPORT     Add support for Cyclone V CSX and CST parts
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; ?9 v% L" ]$ {- v) m8 B, C1170108 ALLEGRO_EDITOR INTERACTIV       Enhancement to preserve Rat T location for Topology assigned schedule

1170313 SIP_LAYOUT     LOGIC            scm adding additional pin names and unassigned property to codesign die chips file
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  O* X1 e& y- j( Z  y* e! a0 m9 D, v1171136 CONCEPT_HDL    CORE             Page Number should also be displayed in Import Design Window.
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8 h# Q! i0 Q& H  Q1171747 ALLEGRO_EDITOR PLACEMENT        Allegro crashes when doing a gate swap between components

% e2 D6 j  B$ l- R0 }# g: W8 h1172183 ALLEGRO_EDITOR INTERACTIV       Alignment modules fails on equal spacing

; B* l8 [& k) s1173183 ALLEGRO_EDITOR DRC_CONSTR       Undesired Same net DRC for overlapping Pin and Via
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! W) n+ \% \: \1 J9 U3 o1174067 ALLEGRO_EDITOR DRC_CONSTR       Soldermask to shape drc does not show if the layer is a PLANE.

1174338 ALLEGRO_EDITOR PLACEMENT        preview has rotated pads

1175307 CONSTRAINT_MGR ANALYSIS         CMGR fails to report RPD DRC for accuracy 4 - mm

2 w% P9 ^2 ^3 G% |: c! q) Z1175537 ALLEGRO_EDITOR REPORTS          net loop report crashes Allegro. Design specific

: h, P& T$ F: z+ [" m; H1176126 ALLEGRO_EDITOR INTERFACES       3D viewer doesnot change models units dynamically
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1176281 CONCEPT_HDL    CORE             Option to Auto-hide excluded modules

9 F( E% `, o+ e1176413 ALLEGRO_EDITOR MANUFACT         Q - testprep parameter settings is not retained, what could be the cause..
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/ g7 U% Z3 p% y5 `& q3 s+ \1176791 ALLEGRO_EDITOR GRAPHICS         Spurious odd lines are shown in shapes and text that are not part of the design with opengl
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3 {7 ]2 v8 d: s' E) y1178052 ALLEGRO_EDITOR SHAPE            SIP crashes during shape degassing.
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. D+ \* }, @* Y( u" H' m1178158 ALLEGRO_EDITOR INTERFACES       Export step file creates step file of same height

2 o. W/ S7 ?$ l' `9 e7 L) P1178201 ALLEGRO_EDITOR GRAPHICS         Large oval pads rendered as oblong hexagons in the 3D viewer

1178671 ALLEGRO_EDITOR GRAPHICS         3D Viewer in package symbol editor not displaying correct place bound shapes.
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1178725 ALLEGRO_EDITOR OTHER            With fillets present, rat lines do not point to the closest endpoint.

: G0 `5 F. Q$ }+ }1178972 CONSTRAINT_MGR ANALYSIS         The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.

1179093 ALLEGRO_EDITOR SHAPE            Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas.

1179109 ALLEGRO_EDITOR OTHER            DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version

1179571 ALLEGRO_EDITOR ARTWORK          Artwork crash and artwork log report Aparture missing
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8 p( g5 y# x! [3 ]+ ~  F& x( _2 f: @1179636 SPECCTRA       ROUTE            Route Automatic will not start if NET_SHORT are attached to a mec-pin

2 J! \8 N6 C. X) h' a1179659 SIP_LAYOUT     DIE_EDITOR       die edit on co-design die losing c4 bumps
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1180306 ALLEGRO_EDITOR ARTWORK          When trying to create Artwork the tool crashes with no error messages just a little X box
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1180573 ALLEGRO_EDITOR ARTWORK          If one layer has warning, all artwork films are "created with warning".

, B" Q" F/ q, K3 l2 [8 q& F1180960 SIP_LAYOUT     PLACEMENT        swap function is not swapping logical paths in sip layout!
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1182534 ALLEGRO_EDITOR SKILL            axlLayerPrioritySet() not working with v166 s013 and up
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7 [  Z- B. E$ r1182560 ALLEGRO_EDITOR PLOTTING         Creating plot 2nd time casues Allegro to crash
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1182616 ALLEGRO_EDITOR PLACEMENT        Application crashes when attempting to place a high pin count BGA
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8 M+ J, P1 }, y' E9 u1183752 CONCEPT_HDL    CORE             Unable to modify location properties within a read-only hierarchical block

1183774 SIP_LAYOUT     DIE_EDITOR       Die Refresh hangs

1184178 CONCEPT_HDL    CONSTRAINT_MGR   Ecset xnet members lost from electrical class when restore from definition of  subblocks

) T! E! ?! p0 ~+ \& c1184787 ALLEGRO_EDITOR EDIT_ETCH        Allegro SPB166 s 015 crashes during normal add connect function.
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Cadence SPB OrCAD 16.60.016 Hotfix
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# `. n. l3 z/ ]2 GDownload uploaded
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molin

谢谢，请问下有没有打补丁 的方法？？

pxgood

长假回来就给力了 谢谢了！！！

inspiron1501

前几个补丁跳过了，这次看bug fix，修正了很多，也增强了很多功能，特别是step方面，测试一下，多谢分享！

allanwang

谢谢楼主分享！！！

wxmcumtb

顶。。。。。。。。。。

lgl2466