Cadence SPB OrCAD 16.60.016 Hotfix

suiwinder

cadence SPB orcad 16.60.016 Hotfix | 853 mb
8 Q. ?5 u6 B8 ` DATE: 09-27-2013   HOTFIX VERSION: 016

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6 Z8 `! y$ h- _% sCCRID   PRODUCT        PRODUCTLEVEL2   TITLE

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548538  CAPTURE        NETLIST_allegro  Enhancement:Include mechanical parts in Allegro netlist
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. Q% n2 k* F* O3 k5 _0 U( T3 T1076579 CAPTURE        GENERAL          Display value only if value exists

2 }- u* p$ \3 z( J5 D2 G5 r5 w1083904 FSP            GUI              Need Filter in Change FPGA dialog to select desire FPGA from the long list.

1089313 ALLEGRO_EDITOR INTERFACES       Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility

1095728 ALLEGRO_EDITOR EDIT_ETCH        Slide to grab adjacent elements when extend selection is enabled
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1102698 SIG_INTEGRITY  ASSIGN_TOPOLOGY  ECset will map on single ended nets but fails when the two nets are define as a diff pair.

1104071 SIG_INTEGRITY  REPORTS          Shape Parasitic value changes for bottom shape for changes in top shape
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/ ]! G5 _/ S+ n5 z! y1 g5 X8 x1117731 FSP            POWER_MAPPING    Ability to sort in Power Regulator forms
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1121539 FSP            CONFIG_SETTINGS  Cannot configure special FPGA pins (temperature diodes)

9 h) h7 z1 A0 v9 a  p2 T# f1122721 FSP            MODEL_EDITOR     Partial copy-paste overwrites the complete cell in XML Editor

+ ]9 z/ c( a  v6 a( p1123238 FSP            TERMINATIONS     Report functionality for terminations defined in the complete design.

1123364 FSP            GUI              Clicking on column header should sort the column.
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/ H+ x/ k" Q. P3 a; J1123403 FSP            EXTERNAL_PORTS   Improper checkbox selection for 緿o Not Connect?or 縀xternal Port?column

1125611 concept_HDL    OTHER            display unconnected pin in schematic pdf.

1129871 ALLEGRO_EDITOR INTERACTIV       Wire Profile Editor can't read mcmmat.dat in working directory.
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1133688 ALLEGRO_EDITOR GRAPHICS         Enhancement request to enable 3D Viewer to show STEP model from .dra file.

1141747 ALLEGRO_EDITOR GRAPHICS         3D view dooesnot displays height if step_unsupported_prototype variable set
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% N: W8 g* }" O; F1142215 SIG_INTEGRITY  SIMULATION       PULSE_PARAM set on DiffPair wasn't used for designlink simulation.

1142798 ALLEGRO_EDITOR INTERFACES       Step file output is incorrect in step viewer when composed of arcs and line.

1142894 FSP            GUI              Ability to RMB on a header and select `Hide Column?
) `9 m" t7 _3 ]! {) ^7 E: @1142940 FSP            EXTERNAL_PORTS   Issue with checking/unchecking "Do not connect" and "External port" cells
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: ], s6 D$ t- X0 c1142949 CONCEPT_HDL    skill            Usage of "Preferences > License Settings?in FSP
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1143091 SIP_LAYOUT     SYMB_EDIT_APPMOD symed:  When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract
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1144371 CONCEPT_HDL    COMP_BROWSER     Component Browser search results are inaccurate

1145033 ALLEGRO_EDITOR PLACEMENT        When aligning components with options in Placement mode displays no busy indicator
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1145286 CONCEPT_HDL    CORE             Directive required for switching off the console

1 X8 Y' f. H2 }. h! `1145800 ALLEGRO_EDITOR GRAPHICS         Spurious odd lines are shown in shapes and text that are not part of the design with opengl.
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1147899 ALLEGRO_EDITOR SHAPE            Autovoid two overlapping shapes that share the same net

* Q$ \8 _9 n( E9 E0 J, p1149996 ALLEGRO_EDITOR EDIT_ETCH        Routing does not follow the ratsnest 'pin to pin'.
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( O7 ]& }  ^/ v- f7 p1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.

1152577 ALLEGRO_EDITOR DATABASE         slide removes cline seg

' K  [7 W  w: T/ \- S# o/ x! E9 x1152751 CONCEPT_HDL    CORE             Option to double-click and copy the Netname
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1153220 ALLEGRO_EDITOR INTERFACES       ENH: option to supress header/footer during PDF Export
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& m8 [, d+ h; h  g) E  F" A1153625 ALLEGRO_EDITOR INTERFACES       If Symbol has place bound bottom, the step model shows incorrect placement.

1153813 CONCEPT_HDL    CORE             Spaces should not be allowed in the signal name entry form
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" ?8 D; Y! e, X: j- {' c9 i+ w0 Y1153857 CONCEPT_HDL    CORE             Changing different power symbol should maintain the schematic level properties.
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1155161 CONCEPT_HDL    CORE             Add Signal name: Suggestion box overlaps with the typed signal name that is typed

' A' N# J5 f' s+ q. t1155922 CONCEPT_HDL    OTHER            How can I use the batch mode for PDF Publisher and print a variant overlay?

( P" }; ^- @5 v0 V- h0 h8 E0 _! A1156858 ALLEGRO_EDITOR pads_IN          PADS Translator: Missing drill on square PTH padstack

1157362 APD            3D_VIEWER        Need a way to color multiple nets in 3D viewer from APD/SiP.

1 j% e0 w6 `  m2 o9 o: {8 U1158130 CONSTRAINT_MGR ANALYSIS         Constraint Manager do not display the Cumulative Result in Reflection Simulation
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1158210 ALLEGRO_EDITOR SHAPE            SIP Layout happens crash while users move the shape with route keep-out

, E/ r! q3 g4 X3 ~' r' l1158452 SIG_INTEGRITY  GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle
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1158827 ALLEGRO_EDITOR EDIT_ETCH        Slide a via in pad automatically add cline back to via to pin.

2 U4 @% ~' U' D4 \0 N0 N1158871 PCB_LIBRARIAN  IMPORT_CSV       PIN TEXT is not automatically added when importing the .csv file
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1159738 ALLEGRO_EDITOR INTERACTIV       Selecting the Cancel button in the Text Edit command does not cancel the text.

1159878 SIG_EXPLORER   OTHER            Ecset mapping dont follow topology template
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4 A$ b5 `6 A/ U4 B% ?% U1159971 ALLEGRO_EDITOR MANUFACT         Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file
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/ s, R# U1 m# O* ]3 u0 D9 W5 t1160017 SIP_LAYOUT     DIE_ABSTRACT_IF  Add text to clarify shrink operation
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1160507 APD            EDIT_ETCH        Script not playing back what was recorded when sliding lines
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  S# T% Z# l9 D$ @) {1161261 ADW            TDO-SHAREPOINT   Schema for TDO-SP fails on Japanese OS

, A) I' D+ ]9 n, z' @! C1161538 CONCEPT_HDL    CORE             Espice model value edited in DE HDL  & then netlisting done, but it doesnt changes the earlier assigned model in Allegro

' V- v1 s+ v/ L6 K9 _1161636 ALLEGRO_EDITOR DRAFTING         need new function for PDFout : hatching shape
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+ j& ?* L9 f6 C. u1161777 ALLEGRO_EDITOR OTHER            default line width for PDF output

1162383 CONCEPT_HDL    CHECKPLUS        Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.
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0 N, \$ L8 D- k1162562 CAPTURE        STABILITY        Capture crash on second attempt of Pspice netlist creation in 16.6
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1162629 FSP            PROCESS          "Load Process Option" under Run does not work properly
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* Y( [) y1 A& H  W1162686 CONCEPT_HDL    CORE             Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE
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3 L. F5 f# H1 H9 e1 {5 t6 p- y1163149 ALLEGRO_EDITOR DATABASE         Autosilk creates Illegal arc to corrupt database

1163439 ALLEGRO_EDITOR COLOR            Duplicate Views Listed in Visibility Tab.
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! d6 q6 N' a0 i' a' U) N1163521 CONCEPT_HDL    COMP_BROWSER     System Architect crahes on replace

1163709 CONCEPT_HDL    CONSTRAINT_MGR   Loosing Diffpairs when reimport block or restore from definitioin
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1163902 APD            EXPORT_DATA      Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?

; e" v: R8 x: P" V7 f) s+ p1 ^  z1164337 CONCEPT_HDL    CORE             Cannot delete attribute filter value in PDF > General > Attribute Filter list

1164365 ALLEGRO_EDITOR INTERACTIV       Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol
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! I: }. E6 R/ D# {. X1164769 APD            VIA_STRUCTURE    The replace via structure command does not accept a single canvas pick.
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1165026 ASI_SI         GUI              EMS3D exist in Via Model Setup of SI base.

! K& e+ V$ V' y& {0 V1165561 CAPTURE        DRC              File > Check and Save clears waived DRCs
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, I( |" d4 Q/ {( \  O- s, a1165631 CAPTURE        STABILITY        Capture crash in the hierarchy tab of Project Manager window
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1165836 SIG_INTEGRITY  GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)

1165911 FSP            PROCESS          Editing group name in protocol causes incorrect Process option checked
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1166026 ALLEGRO_EDITOR DATABASE         Running DB Doctor removes net name from vias

0 o) b" n" U0 Q) S& |/ e3 m1166034 SIP_LAYOUT     OTHER            SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle
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1166074 GRE            CORE             GRE crashes during planning phases
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1166319 ALLEGRO_EDITOR PLACEMENT        Swap not succeed
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  t# R: z4 ~, [6 {1166484 SIP_LAYOUT     WIREBOND         Bondfinger "Align With Wire" problem during move
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1166530 ALLEGRO_EDITOR INTERACTIV       Bug: Mirror in Placement Edit resets the options tab for Edit > Move

1166819 CONCEPT_HDL    CORE             Cadence DEHDL Text Size Issue

1167847 CAPTURE        PROPERTY_EDITOR  Implementation name length greater than 31 character causes capture crash
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' C. ?9 `2 M0 a+ d: i1167887 F2B            OTHER            Improve message on symbol to schematic generation

' ^- ]+ R6 X0 ]8 ]8 x1168369 F2B            DESIGNVARI       Variant don縯 appear in increasing order while Annotate.

1168629 APD            OTHER            Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD
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1168678 ALLEGRO_EDITOR NC               Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.
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! O0 l5 e0 e' D1168798 ALLEGRO_EDITOR INTERACTIV       Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk

1168830 ALLEGRO_EDITOR DRC_CONSTR       missing DRC-marker for package to package check

1168864 ALLEGRO_EDITOR CREATE_SYM       Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty

1169213 PSPICE         SIMULATOR        Parametric sweep is giving incorrect reuslts

1169436 FSP            FPGA_SUPPORT     Add support for Cyclone V CSX and CST parts

6 ~/ n+ j* g9 W) G1 e1170108 ALLEGRO_EDITOR INTERACTIV       Enhancement to preserve Rat T location for Topology assigned schedule
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1170313 SIP_LAYOUT     LOGIC            scm adding additional pin names and unassigned property to codesign die chips file
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. Q3 N% ?4 [3 ^9 Z7 |* S( }  o! y1171136 CONCEPT_HDL    CORE             Page Number should also be displayed in Import Design Window.
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4 r' }9 \4 Q- ^$ q, Z. W* I1171747 ALLEGRO_EDITOR PLACEMENT        Allegro crashes when doing a gate swap between components
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1172183 ALLEGRO_EDITOR INTERACTIV       Alignment modules fails on equal spacing

1173183 ALLEGRO_EDITOR DRC_CONSTR       Undesired Same net DRC for overlapping Pin and Via
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1174067 ALLEGRO_EDITOR DRC_CONSTR       Soldermask to shape drc does not show if the layer is a PLANE.
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8 y1 R4 E$ c0 ~3 O( }+ l! {8 a1174338 ALLEGRO_EDITOR PLACEMENT        preview has rotated pads

6 c( G2 [+ {- Y9 S' k3 A! A& w1175307 CONSTRAINT_MGR ANALYSIS         CMGR fails to report RPD DRC for accuracy 4 - mm

1 k6 q3 h1 ^4 Y9 G: W* P1175537 ALLEGRO_EDITOR REPORTS          net loop report crashes Allegro. Design specific

5 F1 V- N. V. G4 I( b1176126 ALLEGRO_EDITOR INTERFACES       3D viewer doesnot change models units dynamically
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1176281 CONCEPT_HDL    CORE             Option to Auto-hide excluded modules
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1176413 ALLEGRO_EDITOR MANUFACT         Q - testprep parameter settings is not retained, what could be the cause..
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* `; I2 m3 Y. s  x4 n2 w1176791 ALLEGRO_EDITOR GRAPHICS         Spurious odd lines are shown in shapes and text that are not part of the design with opengl
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6 ^" t/ ~+ K  _0 K6 n+ j: i- M1178052 ALLEGRO_EDITOR SHAPE            SIP crashes during shape degassing.

1178158 ALLEGRO_EDITOR INTERFACES       Export step file creates step file of same height

1178201 ALLEGRO_EDITOR GRAPHICS         Large oval pads rendered as oblong hexagons in the 3D viewer
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* V2 A8 A4 g& V8 y1178671 ALLEGRO_EDITOR GRAPHICS         3D Viewer in package symbol editor not displaying correct place bound shapes.

* a* i- ?4 `) v  U7 T: j4 Y2 S0 L6 r1178725 ALLEGRO_EDITOR OTHER            With fillets present, rat lines do not point to the closest endpoint.
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3 D5 b; U  P! M: c1 w1178972 CONSTRAINT_MGR ANALYSIS         The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.

1179093 ALLEGRO_EDITOR SHAPE            Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas.
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1179109 ALLEGRO_EDITOR OTHER            DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version
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# K% r9 p7 y- }4 a1179571 ALLEGRO_EDITOR ARTWORK          Artwork crash and artwork log report Aparture missing

1179636 SPECCTRA       ROUTE            Route Automatic will not start if NET_SHORT are attached to a mec-pin
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1179659 SIP_LAYOUT     DIE_EDITOR       die edit on co-design die losing c4 bumps

& f( R# F8 M( ?# j# R! r% T1180306 ALLEGRO_EDITOR ARTWORK          When trying to create Artwork the tool crashes with no error messages just a little X box
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1180573 ALLEGRO_EDITOR ARTWORK          If one layer has warning, all artwork films are "created with warning".
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1180960 SIP_LAYOUT     PLACEMENT        swap function is not swapping logical paths in sip layout!

1182534 ALLEGRO_EDITOR SKILL            axlLayerPrioritySet() not working with v166 s013 and up
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1182560 ALLEGRO_EDITOR PLOTTING         Creating plot 2nd time casues Allegro to crash

1182616 ALLEGRO_EDITOR PLACEMENT        Application crashes when attempting to place a high pin count BGA
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1183752 CONCEPT_HDL    CORE             Unable to modify location properties within a read-only hierarchical block
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/ W  ]- G( H5 R! F1183774 SIP_LAYOUT     DIE_EDITOR       Die Refresh hangs

1184178 CONCEPT_HDL    CONSTRAINT_MGR   Ecset xnet members lost from electrical class when restore from definition of  subblocks

1 d+ }! B+ G. z% h1 g- k, W1184787 ALLEGRO_EDITOR EDIT_ETCH        Allegro SPB166 s 015 crashes during normal add connect function.

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0 I2 m  V+ B5 i* T% ^/ X+ mCadence SPB OrCAD 16.60.016 Hotfix

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molin

谢谢，请问下有没有打补丁 的方法？？

pxgood

长假回来就给力了 谢谢了！！！

inspiron1501

前几个补丁跳过了，这次看bug fix，修正了很多，也增强了很多功能，特别是step方面，测试一下，多谢分享！

allanwang

谢谢楼主分享！！！

wxmcumtb

顶。。。。。。。。。。

lgl2466