|
|
2#
楼主 |
发表于 2013-10-29 17:11
|
只看该作者
/ ?: S% F* l% T& {8 R% `DATE: 10-25-2013 HOTFIX VERSION: 0183 H0 _+ ~1 H' o# d3 t1 q
===================================================================================================================================
3 }5 h9 w6 m# A w& K2 K8 LCCRID PRODUCT PRODUCTLEVEL2 TITLE& I, a& P1 y, t0 `+ z6 |" m5 U
===================================================================================================================================# x4 [( j6 K0 i* [4 S* \3 j
1118303 CONCEPT_HDL CONSTRAINT_MGR can not prdefinedefault units in HDL
$ g: T6 z$ u2 T& J1174901 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapesand text that are not part of the design with opengl
9 c6 ], H2 p5 E( s% C1176990 CONCEPT_HDL OTHER DEHDL BOM tooldoesn縯 see similar names.
" S) Z. @, u$ } S1179665 GRE CORE Plan TopologicalCrashes after around 8 hours of routing.
# x& H+ }. E: r; n/ y1188193 CONCEPT_HDL CHECKPLUS CheckPlus notrecognizing PIN as a base object.* Y4 h/ |/ l/ `
1189100 SCM OTHER Replace part inSCM using ADW as library fails
# U# o! |& [0 j3 z8 l1189507 SCM SCHGEN ERROR(SPCOCN-2009): Package error after second schgen run with Preservemode.
4 Z' ^% v) x1 X1 ]+ u/ q t1192391 CONSTRAINT_MGR CONCEPT_HDL Restore from definition deletes localobjects in other blocks
/ e- Q" o8 D, l+ L4 b1194597 FSP OTHER Pin definitionproblem) V- _9 S2 u2 d* R% @5 [ n
1195202 SIP_LAYOUT LEFDEF_IF Cannot add .leffiles in IC Library Manager. Getting warning message WARNING(SPMHLD-52)9 v) j# {) r" R
1195309 GRE CORE GRE crashingduring Plan Spatial.
* x4 G- \' B& S0 {1197262 ALLEGRO_EDITOR MANUFACT Angular Dimension created in symbol isplaced w.r.t. board origin and angle is blank3 @/ l m8 q. a
1198521 CONCEPT_HDL OTHER Cadence DEHDLissue - Note for Hotfix_SPB16.60.016_wint_1of1
* E+ E y! j* q2 I1199219 ALLEGRO_EDITOR INTERFACES Question on STEP Model export which usesPLACE_BOUND layer for any symbols that do not have STEP model mapped
9 O( H! D* Q2 d0 e: u' n1199235 ALLEGRO_EDITOR SCHEM_FTB capture's behavior is redundant whilecreating pcb editor netlist
6 w- }7 ]( M& n5 V3 j1199323 GRE IFP_INTERACTIVE Crash whenimporting logic
2 ^1 t0 M! N$ A& g+ D: S) q! ]1199368 SIP_LAYOUT DIE_EDITOR Refresh of dieabstract in die editor with this design takes over two hours) |! c3 d6 R+ s! P ~
1199760 ALLEGRO_EDITOR DATABASE Allegr won't display Soldermask Toplayer |
|
[复制链接]
/1 
发表于 2013-10-29 17:10
收藏
淘帖
支持！
反对！
发表于 2013-10-29 22:30
