|
EDA365欢迎您登录!
您需要 登录 才可以下载或查看,没有帐号?注册
x
本帖最后由 pzt648485640 于 2013-11-19 08:22 编辑 % i7 S, X" ^3 m. ~
$ V) E; T: J, o3 W7 ^0 S1 Mhttp://pan.baidu.com/share/link? ... 9&uk=2033524562
" U; Z X1 W+ U4 O7 f; [
# c: y2 k" v a: z( F0 S& J/ N3 M9 b: K' z {1 U, P% f
DATE: 11-15-2013 HOTFIX VERSION: 019
& g1 w$ W v8 |# G7 _
) {6 _" `- J$ F8 M2 b- C3 D: T===================================================================================================================================
/ o \2 ]/ d. g6 k8 V' k
' Z( e' S# {( f* F! L: lCCRID PRODUCT PRODUCTLEVEL2 TITLE
9 T) G" |0 z1 B: L
* @# ]# G3 H: V, _7 _- M6 s6 z===================================================================================================================================
% a% H% ^( y5 E7 l! M7 x8 g" ~. j1 w) G( v- C) x% B
1176155 concept_HDL CORE Graphics remnants with 16.6 QIR 38 F1 k" {6 q# y/ g* d+ b! { [
. b# R2 R( u0 [+ v
1178272 CONCEPT_HDL OTHER Verilog netlist does not include split blocks correctly4 T4 Z9 u! }5 m
$ A7 j3 q1 W0 l/ M- c- R8 j1190782 FSP FPGA_SUPPORT Support for Altera > 5SGXEA9N2F45 device.& A0 ?( O; Y% E
5 Q+ {7 Z, |2 C/ H1194140 ADW LRM SYNC_PROPERTIES is not resolving issues a based sync_properties settings
8 X& T+ L$ [. W9 ^( C6 Q+ C, ^, Q5 b$ [; r: ]- C( U5 ?: K
1195744 APD EDIT_ETCH Diff_Pair routing fails on certain Uvias in the pair.
b" \7 d/ I/ j/ x( j
2 Z Y) B5 b$ ]* }. b$ w h1196704 allegro_EDITOR INTERFACES ENH: During ipc2581 export checkboxes corresponding to ¿Miscellaneous Image Layers¿ should automatically get selected
+ v I4 l; _& h+ ]7 E& A* d, B; r* j; ?
1198340 ALLEGRO_EDITOR OTHER Multiple -product option on the Allegro command line does not access the second -product" Z& p: x( Q4 d2 Z E
8 O) Z- ]# A- R5 d9 W
1198596 ALLEGRO_EDITOR INTERFACES When copper thickness is increased for the outer layers, step Viewer does not show correct component position.
6 t5 j' e0 k! Z2 n
9 V4 p8 m1 k. P3 w1199673 PCB_LIBRARIAN OTHER Component Browser fails to load footrpints if they are set with UNC path# n) K- b4 _ |4 _4 M2 I( c
" X6 \" u' G# x% C& N
1199889 ALLEGRO_EDITOR DATABASE Allegro crashing with latest hotfix.5 n% ` m" c9 _8 l6 p
$ L0 w9 f1 g# g1200303 ALLEGRO_EDITOR GRAPHICS 3D Viewer does not update after changing STEP model mapping
/ Y% V$ M3 i/ E0 r- C. ]) k" W5 J
1200449 ALLEGRO_EDITOR REPORTS Allegro crashes when generating Net Loop Report.
4 T% K# m0 g; O4 k! o+ W9 ]8 ~: p7 ^, u$ t
1200915 ALLEGRO_EDITOR DATABASE Reducing accuracy of this specific design crashes Allegro; Q' v3 ^& {! @% g- h: N
% ^: G+ w* X7 H ^" q
1201011 ADW COMPONENT_BROWSE Component Browser crashes in DB mode
. ?- h/ }0 F" ]* K7 a% [& \$ u8 K
1201376 ALLEGRO_EDITOR INTERFACES Allegro hangs when trying to map a specific STEP model to a package drawing.( S. F; m6 b( l7 g& e
) S0 M4 [$ X. j8 x4 _1201897 SIP_LAYOUT IMPORT_DATA BGA Pin Colors not matching the Colors defined in the Symbol Spreadsheet after updating.
2 y/ ^( S! d$ I0 S% `6 e: S6 Q% R1 h V3 W
1202709 ALLEGRO_EDITOR INTERFACES STEP File generated from Allegro is not overwritten when the variable "set ads_textrevs
9 w. L9 ]1 _; w2 z# \2 I% B7 B/ s
1202820 ALLEGRO_EDITOR INTERFACES Different xml generation for same step model on S106 and S017
) c" L* v1 @ ?- O, \: ?1 R2 U( w k+ o) Q! X j' q2 V
1202842 ALLEGRO_EDITOR INTERFACES Step model invisible for one pin dra in allegro 16.6 symbol editor2 y2 A: c, p' I' w
6 w1 P9 y# U: O) a0 Q# S" c1202983 ALLEGRO_EDITOR SHAPE Shape voiding creates DRC with Route Keepout( E: C6 ?% g0 v) m- D
0 r, g5 q+ a, ?- x! x2 }' V! [& c1203125 ALLEGRO_EDITOR OTHER Exporting STEP file with External copper enabled does not show all copper when viewed with Solid Edge or Inventor
: a: y2 [# m& _. f }$ {
+ M; L' V! o6 k. c; {$ G: G- g1203236 ALLEGRO_EDITOR INTERFACES IPC2581 output with crosshatched shape is not correct
( d2 ~0 q* P+ a' S( O9 r7 k) D0 Q- H n0 X5 v5 H
1203995 CONCEPT_HDL CHECKPLUS CheckPlus rule, local_signal_no_offpage_body, getting an incorrect failure.* k5 g# F* L' z: d" O9 o& y3 Y
8 H8 ^8 V8 g: y3 T1204629 ALLEGRO_EDITOR skill axlUIDataBrowse crashes the editor or returns error
+ w. p F( {! H1 y
2 Q. K; Q: D3 @1204640 SIP_LAYOUT DIE_EDITOR Concurrent co-design update fails( Q6 e- g/ Z" K* ~6 {7 k& f. H
# K) X% s- f# _1204881 SIP_LAYOUT BGA_GENERATOR Pin numbers are messed up after deleting a pin at a staggered bga) R! O# g7 p' {4 T5 |
) a. L2 t. p ]( K1204885 CONCEPT_HDL CONSTRAINT_MGR Cant assign discrete models after the wrong model was removed., t7 g$ z; F% U r5 r% o
. c+ V) S5 z) u- U
1205374 ALLEGRO_EDITOR OTHER pdf out command creates incorrect drill Symbol Characters placement in pdf file when setting film mirrored.
9 X; k c t5 o% J! ^/ w# c7 ~5 \9 u
1205729 SIP_LAYOUT DIE_EDITOR update of codesign db fails on exit from die editor, a3 E2 K$ U! {5 J- I
4 j' y/ p8 }' a7 y& x. W$ `9 w1205801 ALLEGRO_EDITOR OTHER Tool crash when do export IPF.* D! x9 J5 v+ W4 S0 [2 t; k3 b
a2 u/ A1 Z6 v, X3 m5 a
1205881 CONSTRAINT_MGR OTHER In CMGR , Objects > Create crashes Allegro
# w9 J* I( ^: ^) e& C' T! g% o5 g7 I `# P& Y5 J) z9 a# V
4 g' U; ?; @1 R& G: v l
|
评分
-
查看全部评分
|