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http://dl.vmall.com/c0fu1auqa8) Z" k6 s" n# `9 q; |6 u; w1 b
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7 I: Y2 z0 \) ?& {+ E; fDATE: 02-14-2014 HOTFIX VERSION: 023
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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- j5 h9 J9 ]5 ~( b1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.
' D# ?4 R2 _% e8 q6 @1202715 SPIF OTHER Objects loose module group attribute after Specctra/ i" D: W# ]2 T& E
1203443 ADW LRM LRM takes a long time to launch for the first time
# {4 v8 A1 l& c& Z+ Q, g1207204 CONCEPT_HDL CORE schematic tool crashed during save all, ?' v. g& D% S0 s! d+ \, R
1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter9 Z' B* s ^4 M4 ~& R" k
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA2 K6 D1 k# r# {% R% I0 M
1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side
0 o6 A1 r: `5 }) K; z1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr
2 O5 _, ]: g/ y! |% _3 y' ^1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.
. }6 i# `8 L* C7 v* \" Y1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
/ w. f$ V9 w7 T3 J& v7 j: S1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.
! H2 \5 p; H* [: ?' y8 i7 Z1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7: F+ M4 d" r$ x8 t( G2 y# [8 ^
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's
0 y8 d# } g0 z$ l; k' E1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.
% T* c1 Q, x+ h6 g: Q1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes, ]0 U1 q9 X( |! K
1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form) O, b8 C/ X5 H; A% y
1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
, Y- a- U, }% [' B1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
8 H) b) o- {6 I8 c1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.4 A7 Q* B$ i& x8 l- P
1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.5 d: M* s5 T5 h
1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
( J' L' L+ t. Z$ Q! V) y1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues
, {5 `' m, Z; i# j, l* n1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File1 m6 x% J9 l- V% L n4 ^
1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
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发表于 2014-2-18 16:44
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