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http://dl.vmall.com/c0fu1auqa8
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' p0 h7 i b$ gDATE: 02-14-2014 HOTFIX VERSION: 023
) G% L" B: e8 d+ \7 g===================================================================================================================================
% C. w: i! l6 G0 ]4 QCCRID PRODUCT PRODUCTLEVEL2 TITLE& ~6 q' r% X% l3 c2 \ ]- \# G
===================================================================================================================================
8 R0 v2 R" S& K; L0 f1 N0 c1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.
& N1 ^! h9 C7 C" }! {; J( E0 I2 T1202715 SPIF OTHER Objects loose module group attribute after Specctra
" q1 g( u. Y" F1203443 ADW LRM LRM takes a long time to launch for the first time
1 v+ r$ E# ^3 ] ~! x1207204 CONCEPT_HDL CORE schematic tool crashed during save all6 s5 j5 |) c7 K
1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter
6 a/ q2 Y2 X6 @1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA" K5 }9 @$ S' J- k9 v6 [1 s- j! [7 |! g
1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side
$ Y% M3 z! |8 c. U% \% a1 D1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr
9 Q+ k- H }# ?% u5 `& b# B1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.
' v$ |* D3 v1 C$ i' l1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
7 u$ L- n+ d7 g' e6 a6 ?, V1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.
& r" L7 X* \0 h5 ~% s6 H1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7' D& t. G( C1 ]# R a# j
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's
& l# i9 | j# _2 I7 W% {1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.. s9 y! Z9 V8 C- \* P
1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes" X* [: [9 n C) m/ x8 H. M
1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form
@7 u6 K! O% a; `/ d1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
9 l2 a6 C- K5 c) o5 ^- i1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
& _2 h# Y5 U5 k+ |1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.
+ q, `' n# C0 m0 O' j4 N: d1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.% D; I; x" w9 V; q* b
1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol; N2 P% X/ a/ ?! S
1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues
0 a3 j# x0 ~: L: }$ d# T1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File2 B/ z# t; W5 d5 ^
1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
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发表于 2014-2-18 16:44
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