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http://dl.vmall.com/c0fu1auqa8
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6 B; w7 I' I4 M, y" |' dDATE: 02-14-2014 HOTFIX VERSION: 023% A3 v4 E1 |# d# H, f" l! d+ t4 A+ I( ^
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4 ^0 p, S5 S. f0 UCCRID PRODUCT PRODUCTLEVEL2 TITLE
& j8 e' T9 I* ^: e===================================================================================================================================
( L; e9 @7 g7 W" p- f* {1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.
5 w+ k# A9 x. D% s% w1 \. m! H+ Q1202715 SPIF OTHER Objects loose module group attribute after Specctra
) z* G" m0 F) v( f8 j& y1203443 ADW LRM LRM takes a long time to launch for the first time
6 @/ e& V, I- l' \1207204 CONCEPT_HDL CORE schematic tool crashed during save all
4 p, E$ o$ ]9 t5 U7 k' x4 T1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter$ o7 w) Q& x, c0 e. s4 v+ X& b
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA
, Q8 i# A- P$ U" K t% m1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side
& B. \# ^4 ]6 N9 O+ c: M; k1 p1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr
1 c, |# i% l p+ {' t- i# z1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.0 L4 I2 b( j( o w. ?+ E. X
1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
4 B, O* m* D+ T# n( O# L8 a S( X1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.
/ g: u6 K$ ^: @+ u% c5 m1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7
7 m3 f2 x' W% q6 }1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's
+ m3 E' e# ~6 R! _1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.9 v6 r' G, M" `3 g* M
1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes1 v$ c# L5 Z# s
1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form
, o( l7 T* K% }! c' I) T1 J. A1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
4 a& {8 F5 ]# \" e R, z9 k' P1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
u, _7 U x; |8 k/ T m5 ~$ U1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.
G# y, R% u2 |; X1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.( _5 P" O- y- F; b
1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
2 Y. P3 r9 ]) L( b1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues
& r% B/ \; C/ B9 M0 ~. H3 M0 I( K1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File
( W6 A5 ^" u# G* \- M# R1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
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发表于 2014-2-18 16:44
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