|
|
http://dl.vmall.com/c0fu1auqa8# P* k. [$ |7 r: N
W0 E6 h- O" O1 }& n$ w
, K0 k6 Y: v( E( E7 ]* t
0 v7 E6 g+ k ?
DATE: 02-14-2014 HOTFIX VERSION: 0232 | g ] e# |
===================================================================================================================================$ S% M3 ~7 z7 F6 F0 G M$ N- F
CCRID PRODUCT PRODUCTLEVEL2 TITLE
( C) A+ ^5 a3 v" P5 b9 B G===================================================================================================================================5 \) W: V" B) Z5 I9 q$ r; ]- W
1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.) F# _( B5 r1 w! O: n% @% N
1202715 SPIF OTHER Objects loose module group attribute after Specctra
* @ m- [; b% ^* k7 k+ G, n0 M2 i1203443 ADW LRM LRM takes a long time to launch for the first time
9 u5 `, K3 }$ @: k* R1207204 CONCEPT_HDL CORE schematic tool crashed during save all! m# s. e: ]9 A6 J$ a! c
1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter+ M6 Q1 o/ M1 B1 @, L
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA
& m8 y+ B+ q0 t# Q; l# D1 E1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side; l9 y- Z/ w7 ^# F8 z f9 t, O9 _3 I
1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr
7 q$ G. S5 h! }/ f/ h1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.
2 [- K2 d) ?5 K C( {1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
/ s% O2 N( E' T y4 y l9 {1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.: _' ], e4 O9 S; |# C7 [2 w
1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7, t4 N+ I" W0 @: `' p
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's- t. [ f Z, c/ |) o: D8 g$ a. N; W
1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.$ W, e5 C6 q# A) W& I+ |8 g8 d8 c
1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes8 U' ]" Z1 P5 I% Q* v( C( E; } y, }6 y
1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form4 U- o" x0 @1 ~: F. \2 P+ i
1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect., D+ L, X9 v. s1 y2 U* q0 }6 q
1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX/ t2 ]( }4 c. y" d o1 Y
1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.( Q4 {+ W, x! N
1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.
, W. n5 t* N/ _1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol' y5 g2 Y i, O, v! y! ^, h
1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues5 m- q6 `. `1 A+ V3 c
1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File
+ a% @8 s% e) E0 q7 J; R- N) _, {# a1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
|
/1 
发表于 2014-2-18 16:44
收藏
淘帖
支持！
反对！
楼主
