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你的网络表没有问题
6 X* I `$ A6 E5 s********************************************************************************
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* Netlisting the design % Z* X+ y. h. K; \3 Y. @9 K- E' q
*
7 M+ T1 v3 F# S! {4 v3 x********************************************************************************
$ ^( X% W3 F; q" JDesign Name:$ q% N0 N, c# q2 f( Z0 T
c:\documents and settings\administrator\桌面\wenjian1\yanli2.dsn
1 V9 R1 b/ S; C3 }3 WNetlist Directory:
) Q3 g. o x- e8 }, Xc:\documents and settings\administrator\桌面\wenjian1\allegro2 S1 A& U% P6 e2 m }0 t P+ v P
Configuration File:8 T3 g' m' |$ b0 h ?% y
D:\Cadence\SPB_15.2\tools\capture\allegro.cfg
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% G$ u" Y" ~/ I2 A3 X7 {7 a, LSpawning... "D:\Cadence\SPB_15.2\tools\capture\pstswp.exe" -pst -d "c:\documents and settings\administrator\桌面\wenjian1\yanli2.dsn" -n "c:\documents and settings\administrator\桌面\wenjian1\allegro" -c "D:\Cadence\SPB_15.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"* ~4 Z& { i% h4 t6 w# f
#1 Warning [ALG0016] Part Name "CAP_0_CPCYL1/D.300/LS.200/.034_10UF" is renamed to "CAP_0_CPCYL1/D.300/LS.200/.034_".+ ?: z0 S" h& \- C
#2 Warning [ALG0016] Part Name "CAP NP_0_RAD/.200X.100/LS.100/.031_30P" is renamed to "CAP NP_0_RAD/.200X.100/LS.100/.".0 V1 p. {9 I7 Z; G i$ K
#3 Warning [ALG0016] Part Name "CAP NP_1_RAD/.200X.100/LS.100/.031_30P" is renamed to "CAP NP_1_RAD/.200X.100/LS.100/.".) `( t% i8 V6 w% r' {
#4 Warning [ALG0016] Part Name "4 HEADER_0_SIP/TM/L.400/4_4 HEADER" is renamed to "4 HEADER_0_SIP/TM/L.400/4_4 HEA".
8 e8 N4 v5 |1 d. [' b3 ]% c" r0 V: |8 x#5 Warning [ALG0016] Part Name "8 HEADER_0_SIP/TM/L.800/8_8 HEADER" is renamed to "8 HEADER_0_SIP/TM/L.800/8_8 HEA".# a+ z9 k. x* X! F4 A+ Y
#6 Warning [ALG0016] Part Name "SW PUSHBUTTON_0_RAD/.400X.200/LS.300/.034_RESET" is renamed to "SW PUSHBUTTON_0_RAD/.400X.200/L".6 u1 L# p. X" Z1 F
#7 Warning [ALG0016] Part Name "8051_DIP.100/40/W.600/L2.050_8051" is renamed to "8051_DIP.100/40/W.600/L2.050_80".& f' {% D+ z! R; P
#8 Warning [ALG0016] Part Name "74LS373_DIP.100/20/W.300/L1.075_74LS373" is renamed to "74LS373_DIP.100/20/W.300/L1.075".! j7 r u. Z9 h- N- i5 I! c6 {
#9 Warning [ALG0016] Part Name "27512_DIP.100/28/W.600
) J9 s8 V( W# q$ r) ~0 A" e7 Q/L1.400_27512" is renamed to "27512_DIP.100/28/W.600/L1.400_2".
( S6 O& a, p- L; `#10 Warning [ALG0016] Part Name "CRYSTAL_0_RAD/.400X.150/LS.300/.034_12M" is renamed to "CRYSTAL_0_RAD/.400X.150/LS.300/".
- p) F; p3 J# E- B, E) x: iScanning netlist files ...
5 V* w K. h. F3 f1 {Loading... c:\documents and settings\administrator\桌面\wenjian1\allegro/pstchip.dat$ W9 w0 x6 U$ c
Loading... c:\documents and settings\administrator\桌面\wenjian1\allegro/pstchip.dat
5 b7 k: l p% I4 {/ M5 v; p+ q* MLoading... c:\documents and settings\administrator\桌面\wenjian1\allegro/pstxprt.dat0 |7 }; P2 S0 Y) j6 x* Y( b i
Loading... c:\documents and settings\administrator\桌面\wenjian1\allegro/pstxnet.dat
5 U- ^. |, `( t) k% `packaging the design view...+ c+ S, ~* M% i9 ?
/ q6 q7 {9 Y4 d" T& p6 @Exiting... "D:\Cadence\SPB_15.2\tools\capture\pstswp.exe" -pst -d "c:\documents and settings\administrator\桌面\wenjian1\yanli2.dsn" -n "c:\documents and settings\administrator\桌面\wenjian1\allegro" -c "D:\Cadence\SPB_15.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
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7 V, X6 P3 @- W$ u( m就是出现一些警告,你要注意改一下,生不成ALLEGRO文件可能是你的PCB库做的问题 |
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