Hotfix_SPB16_60_032_补丁发布

wangye_123 · 发表于 2014-7-31 09:06

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DATE: 07-25-2014 HOTFIX VERSION: 032
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
381127  SPECCTRA    CROSSTALK       Specctra xtalk reports aren't correct
616770  allegro_EDITOR COLOR          Remove the APPLY button in the Color Dialog window.
982944  ALLEGRO_EDITOR COLOR          seperate the Etch to the Shape and the the Cline in the visibility window
982995  ALLEGRO_EDITOR INTERACTIV    Shown infomation for the selected physical symbols
1024832 Pspice       PROBE          Shows wrong data & header when exporting trace to .txt
1063258 PSPICE       AA_OPT          curve fit fails with error  same data works in 16.5 Simulation error: out of range of data
1112360 PSPICE       AA_OPT          Advacne analysis gives runtime error while using Optimizer in attached design
1154323 PCB_LIBRARIAN  VERIFICATION    Con2con is choosing incorrect Primitive from Chips file and failing FTB Checks
1184690 concept_HDL CORE          Weird behavior of genview for split hierarchical blocks
1212577 PSPICE       MODELEDITOR    IBIS translation fails without any information in log file
1213204 ALLEGRO_EDITOR PLACEMENT       Place Manually with existing fixed net behaving incorrectly
1213837 ALLEGRO_EDITOR INTERACTIV    When copying a stacked via the temp highlight does not display on the last layer of the stack.
1216519 SPECCTRA    ROUTE          Autorouter will not add BB via between uvia within the BGA area
1220655 PSPICE       DEHDL_NETLISTER  Support for automatic addition for Power source and Ground Node for Globals  in DEHDL PSpice netlisting
1223018 CAPTURE       OTHER          Diff pair Auto Setup not working for the buses.
1225689 PSPICE       AA_SMOKE       Smoke analysis crashes with attached testcase
1232124 CONCEPT_HDL COMP_BROWSER    unable to generate ppt_options.dat file in first go
1235059 PCB_LIBRARIAN  IMPORT_CSV    pin_delays not being imported into PDV
1238815 CAPTURE       OTHER          Capture doesn?t retain more than 191 library in add part/capture.ini under part selector configured libraries
1239241 ALLEGRO_EDITOR INTERACTIV    Via replacement doesn't replace with correct via but right padstack name.
1240201 ALLEGRO_EDITOR EDIT_ETCH       RPD DRC unresolved evenif HUD turns Green
1240314 PSPICE       SIMULATOR       Getting internal error,oveRFlow for the second run
1242805 ALLEGRO_EDITOR DRC_CONSTR    no_drc_progress_meter variable hangs allegro after running update drc
1243267 ADW          TDA             URL to TDO-SharePoint should be defined in CPM File
1244857 ADW          TDA             Policy File Variables not working correctly in policy file
1245779 CONCEPT_HDL CONSTRAINT_MGR Obsolete objects in DEHDL CM
1246811 CIS          EXPLORER       Option to keep the part type tree in CIS explorer expanded on every invoke
1246964 PSPICE       PROBE          Simulation Crashes in 16.6 but running successfully in 16.5
1248782 CONCEPT_HDL CORE          Display winning physical bus names (occurrence mode) in the the lower block of an Hierarchical design
1249238 CONCEPT_HDL CORE          Uprev from 16.3 splatters text around sch page
1249692 ALLEGRO_EDITOR GRAPHICS       3D Viewer is wrong when resizing its window.
1249850 ALLEGRO_EDITOR SHAPE          With shape_rki_autoclip Route Keepin to Shape DRC is created
1250683 ALLEGRO_EDITOR INTERACTIV    devpath corrupts if edited from user preferences.
1252059 ALLEGRO_EDITOR INTERACTIV    Preference Editor is unable to delete a previous path entry for library paths
1253563 SIP_LAYOUT    DEGASSING       Not getting degassing voids when close to shape in center of design
1254319 ALLEGRO_EDITOR GRAPHICS       ENH: Functionality to change the 3D Model color for more realistic view
1254562 ALLEGRO_EDITOR DATABASE       Unable to delete a subclass that exist only on classes Package Keepout, Package Keepin and Route Keepin.
1255169 CONCEPT_HDL OTHER          ADW (BPc) Packager should report the specific corrupt directive in the .cpm file
1255573 ALLEGRO_EDITOR DRC_CONSTR    Need soldermask DRC checks when same net via and smd pad overlaps
1257950 CONSTRAINT_MGR SCHEM_FTB       Changing xnet name on Allegro CM.
1258165 F2B          DESIGNVARI    changing visibility of Probe_number in variant schematic changes it to $Porbe_number
1258274 PCB_LIBRARIAN  VERIFICATION    con2con crash with no notification or error message
1258860 CAPTURE       PROJECT_MANAGER  Bug: Text Editor (File> New> VHDL File) filters characters from Text
1258872 CONCEPT_HDL CORE          Objects are copied (instead of moved) when moved from sheet to sheet
1259284 CONCEPT_HDL PDF             HDL_POWER ( global) net does not get transferred to the published pdf
1259375 CONCEPT_HDL CORE          Help link to cdnUsers.org needs to be changed
1259860 ALLEGRO_EDITOR INTERACTIV    Edit > Mirror does not display asymmetrical pad correctly when the footprint is attached to cursor.
1260002 ALLEGRO_EDITOR INTERACTIV    Alt sym hard is not obeyed when using Edit > Move > Mirror
1260006 ALLEGRO_EDITOR PLACEMENT       funckey r iange 90 rotation issue
1260667 ALLEGRO_EDITOR EDIT_ETCH       Allegro crashes when running AICC command on few Diff Pair traces.
1260763 CONCEPT_HDL CORE          Export Physical fails with $TEMP entry in Setup-Tools
1260847 SIP_LAYOUT    SYMB_EDIT_APPMOD Border texts seen as triangles.
1260948 ALLEGRO_EDITOR SHAPE          Dynamic ground shape is shorting to via of a different net at layer 4 & 5 in this design
1262011 ALLEGRO_EDITOR PLACEMENT       Key Properties on Component Instance/ Definition on available to use with Quickplace by Property
1262322 ALLEGRO_EDITOR PADS_IN       Pads_in can not translate route keepout which specified for the all layers.
1262626 CONCEPT_HDL CORE          PROBE NUMBER attributes lost from the nets after upreving the design
1263592 PCB_LIBRARIAN  VERIFICATION    Unable to check in Schematic Model due to pc.db file
1263685 ALLEGRO_EDITOR INTERACTIV    Editing Photo Width value from non zero to zero allegro gives warning- Value must be greater or greater to zero
1263704 ALLEGRO_EDITOR EDIT_ETCH       Bug - AiTR wrongly deletes blind vias and do reroutes.
1265120 ALLEGRO_EDITOR SHAPE          Require voids in dynamic shapes to use pad value
1265275 ALLEGRO_EDITOR DRC_TIMING_CHK When XNETS are dissolved by removing the Models all Physical and Spacing NetClass associations are lost
1265633 PSPICE       SIMULATOR       Bias point result is different in consecutive simulation run of the attached project
1266349 ALLEGRO_EDITOR PLACEMENT       Rotating symbol while placement show wrong angle of rotation than the placed angle when Angle is set in Design Parameter
1267541 PSPICE       PROBE          pspice.exe does not exit when run from command line
1267707 ALLEGRO_EDITOR PLACEMENT       Mirror Command - preselect/postselect bug with general edit mode
1268299 PSPICE       STABILITY       Pspice crash on attached design
1270879 ALLEGRO_EDITOR COLOR          Color view save creates .color file using older extension
1271295 SIP_LAYOUT    DIE_STACK_EDITOR Die stack editor support needed for large variant combination designs.
1271385 CONCEPT_HDL CORE          Locked property can still be added
1271853 APD          OTHER          When using the beta "shape to cline" command, add improved messages and partial completion of individual segs in error.
1272197 CONCEPT_HDL CORE          concepthdl_menu.txt contains invalid Variants menu
1272318 CAPTURE       GEN_BOM       BOM_IGNORE not working for Capture BOM on hierarchical designs.
1272743 ALLEGRO_EDITOR PADS_IN       PADS Library Translator does not open the Options dialog window.
1273517 F2B          PACKAGERXL    Netrev error - ERROR(40) Object not found in database
1274000 ALLEGRO_EDITOR DATABASE       PCB layer can't be removed
1274530 ALLEGRO_EDITOR INTERACTIV    Add Circle radius value changes next time using this command
1274697 PSPICE       AA_MC          pspiceaa crashes when running Advanced analysis monte carlo for the attached design
1275154 CONCEPT_HDL CORE          Hierarchical Blocks lose ref designators when moved to another page
1275724 GRE          CORE          AiDT delete another clines
1275831 ALLEGRO_EDITOR DRC_CONSTR    Waived DRCs return when using multi-thread DRC check
1275834 CONCEPT_HDL CORE          ERROR (SPCOCD-569) on global bus
1276334 ALLEGRO_EDITOR PADS_IN       PADS Library Import problem with outlines
1277062 ALLEGRO_EDITOR PLACEMENT       Swapping parts from top to bottom Orientation changes
1278746 ALLEGRO_EDITOR DRC_CONSTR    Package to package DRC allows place_bound_top in 0 spacing has drc in 16.6 version.
1278804 CONCEPT_HDL COPY_PROJECT    Copy project crashes
1279362 ALLEGRO_EDITOR INTERACTIV    User skill file makes Allegro Icons gone away
1279619 ALLEGRO_EDITOR DRC_CONSTR    Netgroup in a Netclass doesn't inherit Spacing Cset
1279815 CONCEPT_HDL CORE          Text > Change and RMB Editor does not allow multiple text edits
1279876 ALLEGRO_EDITOR DATABASE       Using the Curved option in Fillets results in a pad to shape DRC
1280435 F2B          BOM             BOMHDL with variant repeats the PART_NUMBER value
1281669 CONCEPT_HDL COMP_BROWSER    Match Any radio button in Component Browser didn't work.
1282001 ALLEGRO_EDITOR DRC_CONSTR    Updating the DRCs on this design cause the DRC count to change on every update
1282480 SIP_LAYOUT    WIREBOND       Info on the Wire Count property needs to be updated indicating that it is a User Defined Property
1283952 ALLEGRO_EDITOR PLOTTING       Published pdf does not show dotted or phantom lines
1283957 ALLEGRO_EDITOR INTERACTIV    Replace padstack in "Single Via Replace Mode" is changing netname of the vias with the latest hotfix of Allegro 16.6
1285588 ALLEGRO_EDITOR DRC_CONSTR    Dynamic phase control has wrong analysis result when add rectangle test bead in Clines.
1286743 ALLEGRO_EDITOR SHAPE          Getting copper islands in the design after running the Delete Plating Bar command
1287215 ALLEGRO_VIEWER OTHER          Allegro viewer plus does not support constraint regions
1288808 APD          LOGIC          Derive Assignment stalls out or won?t finish and appears to run out of database room.
1289251 ALLEGRO_EDITOR SCHEM_FTB       Pin escapes (clines and vias) not inheriting new net name from a pin with a new net name.
1289293 F2B          DESIGNVARI    Warning 04: Cannot merge the variant properties on variant instance C119 component with same canonical path not present
1289809 SCM          VERILOG_IMPORT User not able to import a verilog netlist into SCM
1290696 CONCEPT_HDL CORE          Copying a net name repeatedly causes it to go off grid
1291162 CONCEPT_HDL CREFER          crefer crashes when selecting generate cross refernece for all nets selected
1291285 SIP_LAYOUT    IMPORT_DATA    Replacing a Die with the Die Text in Wizard causes some Clines to Shift, creating new DRCs.
1291658 ALLEGRO_EDITOR INTERACTIV    Cannot add Frectangle to Group
1292180 ALLEGRO_EDITOR SKILL          Allegro Crash while performing query contents of "Maximum_Cavity_Size" with the skill command 'axlDBGetPropDictEntry'
1292210 CONCEPT_HDL CORE          DEHDL crash if design was opened with -nonetlistuprev option.
1292278 SIP_LAYOUT    WIREBOND       When creating Wirebonds by Importing a Wirebond File, (wbt) the wirebonds are not on the correct Die layer
1292282 SIP_LAYOUT    INTERACTIVE    Getting Multiple GUIs when the Wirebond Import is open and we select outside the command GUI.
1293381 SIP_LAYOUT    IMPORT_DATA    Import SPD2 error
1293889 CONCEPT_HDL PAGE_MGMT       page name regression result deleted by netassembler
1294124 ALLEGRO_EDITOR INTERACTIV    Samsung Mobile division wants to disappear the grids in the display window when zoom-out function executes in the allegr
1294749 ALLEGRO_EDITOR ARTWORK       Null pad is flagged as an error that break Thales automatic tape out
1294777 ALLEGRO_EDITOR SYMBOL          Mechanical symbols missed on STEP result

DATE: 06-20-2014 HOTFIX VERSION: 031
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
726553  FSP          CAPTURE_SCHEMATI Method to select bus bit?s order while generating Capture design from FSP.
1257631 FSP          DE-HDL_SCHEMATIC Schematic Generation selects incorrect symbol version
1273456 ALLEGRO_EDITOR PLACEMENT       Place module instance causes Allegro to crash
1277099 ALLEGRO_EDITOR INTERACTIV    Clines and pins are disconnected even though they are at the same x, y coordinate.
1280913 ALLEGRO_EDITOR EDIT_ETCH       Add Connect should be able to be made by go straight even though the cursor is not exist on straight line
1282491 ADW          PURGE          ADW PURGE is removing Page Name data in DEHDL
1283045 ALLEGRO_EDITOR DATABASE       Ecset not getting downreved.
1283138 SIP_LAYOUT    IC_IO_EDITING symed app mode chooses wrong text block sizes for I/O driver inst names
1283227 PDN_ANALYSIS PCB_STATICIRDROP Enhancement request to add 32 bit files for IRdrop
1284656 CONCEPT_HDL CREFER          Crefer fails on large design
1285814 CONCEPT_HDL CORE          DEHDL crash on opening the Design
1285967 ALLEGRO_EDITOR EDIT_ETCH       Slide via in circle pad

DATE: 06-12-2014 HOTFIX VERSION: 030
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
982961  ALLEGRO_EDITOR PLACEMENT       Show the Rats when one selects physical symbols to place them
1138680 FSP          POWER_MAPPING Ability to assign decoupling capacitors in spreadsheet like application
1243410 SIG_EXPLORER EXTRACTTOP    Circuit topology extract failed in case of CLASS
1262977 ALLEGRO_EDITOR TECHFILE       When importing a certain tech file into an empty .brd Allegro crashes.
1267558 ALLEGRO_EDITOR INTERFACES    Arc part of symbol pin missing in 3D view of step model
1268252 ALLEGRO_EDITOR GRAPHICS       step place bound issue(3D View)
1270450 ALLEGRO_EDITOR INTERACTIV    footprint add line on line crash
1270962 CONCEPT_HDL PDF             PDF Publisher command line does not print pdf file if  double back slash is present
1270964 ALLEGRO_EDITOR mentor          Mentor translation crashes with no errors in log file
1270999 MODEL_INTEGRIT TRANSLATION    ibis2signoise Issue
1271543 ALLEGRO_EDITOR PAD_EDITOR    Library import reporting missing padstacks
1272099 ALLEGRO_EDITOR GRAPHICS       Plotting does not fill shapes
1272406 ALLEGRO_EDITOR DRC_TIMING_CHK SKILL command 'axlDBTextBlockFindName' returns 1 when nil is expected
1272748 ALLEGRO_EDITOR GRAPHICS       3D viewer crashes on this specific testcase
1272793 ALLEGRO_EDITOR GRAPHICS       3D view doesnot displays hole with offset correctly
1272863 ALLEGRO_EDITOR INTERFACES    Ability to find the origin of STEP File in order to place it exactly where it needs to be on footprint during mapping.
1273264 ADW          COMPONENT_BROWSE hyperlinks not recognized in the component browser
1273304 CONCEPT_HDL PDF             Publish PDF from commandline does not work if there are spaces in the Path
1274661 CONCEPT_HDL CORE          I can't copy a property from one component to another
1275237 ALLEGRO_EDITOR DATABASE       Allegro Crash on running DBDOCTOR for a board
1275345 CONCEPT_HDL CREFER          The Xref information page number values are incorrect
1275748 APD          IMPORT_DATA    WireBond starts away from the Die Pin after importing Die using Die Text In Wizard
1276270 CONCEPT_HDL CORE          DEHDL crash by Zoom In > Ctrl+A > Move
1277735 SIP_LAYOUT    IMPORT_DATA    sip layout spd2 translator issues with offset die and mirroring
1279258 CONSTRAINT_MGR OTHER          Import logic stops with error
1279694 ALLEGRO_EDITOR SKILL          axlCNSSpacingMin('via nil) crashes Allegro PCB Editor

DATE: 05-23-2014 HOTFIX VERSION: 029
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1209461 FSP          DE-HDL_SCHEMATIC Hierarchical Block Size not automatically adjusting to text needs
1217832 SIG_EXPLORER SIMULATION    S-param generated by SigXP doesn't match with HSPICE/ADS.
1263575 CONCEPT_HDL CORE          Copy-Pate makes Components Off-Grid
1267602 SPIF          OTHER          Route Automatic hangs
1268022 FSP          PROCESS       FSP is not respecting the use banks for attached design.
1268587 ALLEGRO_EDITOR INTERFACES    Enh. Preserve relation between hole and padstack in IPC-2581
1268918 SIP_LAYOUT    DIE_ABSTRACT_IF  SiP - DIE export from co-design object to XDA results in missing data
1269232 CONCEPT_HDL INFRA          While pspice uprev the design crashes
1269825 SIG_INTEGRITY  SIGNOISE       PCB SI hangs when running crosstalk simulations
1270963 ALLEGRO_EDITOR GRAPHICS       Add Circle lint font hidden/Phantom has resolution problem
1270990 ALLEGRO_EDITOR GRAPHICS       Allegro response is slow when added circle
1271655 ALLEGRO_EDITOR MANUFACT       Dimension option causes a generic crash, reproducible in any design
1272495 ALLEGRO_EDITOR MANUFACT       Filtered Part numbers in IPC-2581 still pass actual part number for references onutide of BOMItem
1272839 ALLEGRO_EDITOR MANUFACT       Kindly explain the drill legend behavior when padstack rotation is 45 degrees and mirrored ?
1274518 ALLEGRO_EDITOR ARTWORK       Artwork does not create void correctly.

DATE: 05-10-2014 HOTFIX VERSION: 028
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1199256 ALLEGRO_EDITOR INTERACTIV    DFA bubble does not appear when moving a symbol to within another symbols dfa bounds on specific symbols
1220196 ALLEGRO_EDITOR OTHER          create xsection chart results in ERROR(SPMHA1-73): Text line is outside of the extents.
1259520 ALLEGRO_EDITOR EDIT_ETCH       Allegro will crash when adding connections to a differential pair.
1260446 ALLEGRO_EDITOR VALOR          Creating odb output the xhatch shapes where arcs are will become inverted. Difference in the geoms.out extraction?
1261313 ALLEGRO_EDITOR INTERFACES    Step mapping does not show all Available Packages
1261356 CONCEPT_HDL CREFER          crefer is crashing with generate for all nets option
1261514 ALLEGRO_EDITOR ARTWORK       Exporting raster artwork with overlaping voids fails.
1261735 ALLEGRO_EDITOR ARTWORK       Presence of Smaller shapes inside bigger shapes is crashing artwork generation.
1262019 ALLEGRO_EDITOR INTERFACES    Artwork control form hangs if we close PDF publisher gui
1262246 CONSTRAINT_MGR ANALYSIS       Constraint manager shows ALL PASS when Adding members to a NetClass and adding parallelism rule
1262560 APD          WIREBOND       bondwire can't connect to GND ring directly
1263275 CONSTRAINT_MGR OTHER          Import of constraint file hangs in this design
1263358 SIP_LAYOUT    OTHER          SiP Layout - Void adjacent Layer enhancement to merge voiding for PADS without changing shape params
1264109 ADW          LRM             LRM error - WARNING(SPDWREV-7): Unable to read the design
1265580 APD          MANUFACTURING Icp_soldermask_allow_pins cannot create correct solder mask when the pin rotate.
1266391 APD          LOGIC          SPB16.6 Derive assignment : want to select 1 DRC marker only.
1266687 ALLEGRO_EDITOR SKILL          The SKILL p
1267267 SIP_LAYOUT    WIZARDS       Attempting to create a die using the die text in wizard but the tool is not creating the correct die outline
1267308 SIP_LAYOUT    OTHER          When updating a BGA with the Symbol Spreadsheet tool it will start, update a few pins then stop.
1267639 ALLEGRO_EDITOR PARTITION       Allegro crashes when partition is created and opened from a location that contains "!" in its path.
1267704 SIP_LAYOUT    STREAM_IF       Cannot import stream file, the tool starts scanning the file and never stops.
1267907 CONCEPT_HDL CORE          Ctrl+RMB Context Menu Option doesn't work.

DATE: 04-25-2014 HOTFIX VERSION: 027
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
308701  CONSTRAINT_MGR OTHER          Needs to delete user defined schedule in CM
481674  ALLEGRO_EDITOR PADS_IN       No board file saved from PADS_in
982929  ALLEGRO_EDITOR EDIT_ETCH       can't route on NC pin and other that are not pin.
1012783 FSP          OTHER          Need Undo Command in FSP
1017381 ALLEGRO_EDITOR DRC_CONSTR    Need Dynamic Phase to be able to measure back to the Drive Pins.
1072673 PCB_LIBRARIAN  GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
1073231 CONCEPT_HDL CORE          Copy-paste of signal names goes off-grid in Windows mode.
1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups
1116498 CIS          LINK_DATABASE_PA link database with modified part results in Capture crash
1118632 ALLEGRO_EDITOR GRAPHICS       Text display refresh issue while in Edit > text command
1155821 SIG_INTEGRITY  LIBRARY       Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode
1157372 ALLEGRO_EDITOR DRC_CONSTR    Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
1171951 ALLEGRO_EDITOR CREATE_SYM    Jumper has a limited of count when it add to list.
1180871 CAPTURE       LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings
1185575 SIP_LAYOUT    DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
1185772 PCB_LIBRARIAN  CORE          VALID_PACK_TYPE warning when cell was opened in PDV
1192377 CAPTURE       SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
1202654 ALLEGRO_EDITOR GRAPHICS       Zoom using mouse wheel shall maintain the center co-ordinates
1208031 ALLEGRO_EDITOR INTERACTIV    Snap to Pin for via during Copy command do not snap to connect point everytime
1208478 PSPICE       PROBE          Attached project gives overflow error with marching ON.
1210015 CONCEPT_HDL CORE          The value of $PN should be not turned on spin or rotate symbol
1210425 CONCEPT_HDL CORE          When moving a circuit tool reports that connectivity has changed
1215858 ALLEGRO_EDITOR SHAPE          Force update does not void cline with the shape
1215906 ALLEGRO_EDITOR SHAPE          Dynamic shape fill smooth failed when copying to other layers
1216358 CONCEPT_HDL CORE          Can we improve our export BOM function to check if user did export physical function before exporting BOM?
1217364 CONCEPT_HDL OTHER          Netlist reports fail because error: GScald failed.
1217529 CONCEPT_HDL CORE          ADW checks do not catch single quotes in PTF values
1217556 F2B          PACKAGERXL    signal name change not sent to Allegro after packaging
1219283 ALLEGRO_EDITOR DRC_CONSTR    Show constraint is inconsistent when displaying region information
1220078 F2B          PACKAGERXL    Export Physical crashes when ALL the part pins are added
1220393 CONSTRAINT_MGR CONCEPT_HDL    HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
1220540 ALLEGRO_EDITOR GRAPHICS       Need an option to see the pads inside the internal plane shapes
1220936 CONCEPT_HDL CORE          About crash by vpadd/vpdelete command on Linux
1221059 ALLEGRO_EDITOR DRC_CONSTR    Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
1221182 ADW          TDA             Team Design with SAMBA
1222442 CONSTRAINT_MGR UI_FORMS       Duplicate pin pairs appear in DiffPair
1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened
1223533 ALLEGRO_EDITOR GRAPHICS       Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
1223680 CONSTRAINT_MGR ECS_APPLY       Improve ECSet mapping by allowing user to address ambiguity of Parts
1224156 SIG_INTEGRITY  SIGWAVE       Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
1224417 ALLEGRO_EDITOR PLOTTING       Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
1224704 F2B          DESIGNVARI    There is no lock for the variant.dat file - multiple users can open the editor
1224968 ALLEGRO_EDITOR INTERACTIV    Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.
1224982 CONCEPT_HDL PDF             commandline publishpdf does not work when there are spaces in the path
1225114 CAPTURE       GENERAL       H-pins added after netgroup pin get color as of netgroup pin
1225494 CAPTURE       DRC             Different DRC results for Entire design and selection
1226153 ALLEGRO_EDITOR INTERFACES    Export STEP should include PART_NUMBER property
1226235 ALLEGRO_EDITOR EDIT_ETCH       Enhancement to include Pin_delay of descrete forming Xnet
1226372 CAPTURE       GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet
1226477 CONCEPT_HDL CORE          DE HDL縮 `Allowed Global Shorts�  function is inconvenient for Global Signal
1226813 SIP_LAYOUT    LEFDEF_IF       ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
1227453 ALLEGRO_EDITOR SHAPE          Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
1227461 ALLEGRO_EDITOR SHAPE          Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
1227469 CIS          DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration
1227780 CAPTURE       ANNOTATE       Inconsistent behaviour when annotating heterogeneous part
1227831 CONCEPT_HDL CORE          Pin text and H-block name in upper case
1227954 CONCEPT_HDL OTHER          supress check for global signals when wires are unconnected to pins
1228190 ALLEGRO_EDITOR OTHER          Unable to close the 'usage' window during license selection
1228899 CONSTRAINT_MGR INTERACTIV    Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
1228934 ALLEGRO_EDITOR EDIT_ETCH       The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
1229316 ALLEGRO_EDITOR EDIT_ETCH       When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
1229545 CONSTRAINT_MGR OTHER          Allegro indicate bundle scheduled nets in CM
1230056 ALLEGRO_EDITOR GRAPHICS       Bug: 3D View of Mechanical Symbol with the drill hole defined
1230432 CONCEPT_HDL CORE          No Description information in BOM
1231148 F2B          DESIGNVARI    The variant.dat file is not updated with library PTF changes
1231625 F2B          DESIGNSYNC    VDD at command line needs to support sch2sch and test variable to write out report files
1231697 CONCEPT_HDL CORE          If any locked files exist force a pop-up dialog restricting certain commands
1231767 CONCEPT_HDL OTHER          Unable to find under the search options single bit vector nets
1231961 ALLEGRO_EDITOR SHAPE          Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
1232100 CONCEPT_HDL SKILL          Unable to execute the SKILL commands in viewer mode
1232336 CONSTRAINT_MGR CONCEPT_HDL    cmFeedback takes 5hrs to complete during Import Physical
1232710 F2B          DESIGNVARI    Dehdl crash while moving component in variant viewer mode
1233894 F2B          PACKAGERXL    The page data is missing in the pst* and PCB files
1235785 CONCEPT_HDL CREFER          cref_from_list custom text is not subsitituted in complex hierarchy
1235928 CAPTURE       SCHEMATIC_EDITOR OleObject modifications not saved
1236065 CAPTURE       PART_EDITOR    Mirrored part after being edited get pin name locations incorrect
1236071 ALLEGRO_EDITOR SHAPE          Airgap for Octagonal Pads ignores DRC Value when Thermal set
1236072 CONCEPT_HDL CORE          Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
1236161 CONCEPT_HDL CORE          Import Design shows the current project pages
1236432 ALLEGRO_EDITOR PADS_IN       pads_in doesnot translate via and shape in some instances.
1236557 CONCEPT_HDL PDF             Running Publish PDF on command line in linux doesn't output progress until completion
1236589 CONCEPT_HDL PDF             Enhancement license failure error should appear in pdfpuplisher  log file
1236644 ALLEGRO_EDITOR EDIT_ETCH       create fanout deletes shape
1236689 ALLEGRO_EDITOR GRAPHICS       Graphics displays extraneous lines when panning or zooming
1236781 F2B          PACKAGERXL    Export Physical produces empty files
1237331 PSPICE       ENVIRONMENT    pspice.exe <cir file name> - hangs when run
1237400 CIS          EXPLORER       Capture hangs on 2 consecutive runs of `refresh symbol from lib� command
1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
1237862 CONSTRAINT_MGR OTHER          A way to remove the RAVEL markers from the Constraint Manager.
1238852 CAPTURE       GENERAL       signal list not updated for buses
1238856 FSP          DE-HDL_SCHEMATIC FSP schematic generation crashes
1239079 ALLEGRO_EDITOR INTERACTIV    The 16.6 Padstack > Replace function leaves old padstack.
1239706 CONSTRAINT_MGR ANALYSIS       The reflection result on a differential signal in the CM when Measurement location is DIE
1239763 PSPICE       PROBE          Cannot modify text label if right y axis is active
1240276 ALLEGRO_EDITOR GRAPHICS       Printing to PDF from SigXp is giving unreadable images
1240356 CAPTURE       IMPORT/EXPORT Can縯 import SDT schematic to Capture.
1240502 F2B          PACKAGERXL    Corrupt cfg_package does not stop PackagerXL from completing
1240607 ALLEGRO_EDITOR OTHER          Footprint of screw hole got shift in DXF file
1240670 ALLEGRO_EDITOR PLACEMENT       Select multiple parts and Rotate makes them immovable
1240773 CAPTURE       DRC             DRC check reports error for duplicate NetGroup Reference in complex hierarchy
1240845 SIG_EXPLORER EXTRACTTOP    Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms
1241634 ALLEGRO_EDITOR OTHER          Netshort for pad-pad connect not working
1241776 CONCEPT_HDL CORE          In hierarchal design not all pages are getting printed.
1241788 CONSTRAINT_MGR CONCEPT_HDL    Issues with changing focus in Constraint manager using keys on keyboard
1242683 ALLEGRO_EDITOR INTERACTIV    Color View Save replaces file without warning
1242818 ALLEGRO_EDITOR PLACEMENT       Placement edit mirror option places component on wrong side
1242847 ALLEGRO_EDITOR GRAPHICS       Need an option to suppress Via Holes in 3D Viewer
1242923 ADW          COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results
1243609 CONCEPT_HDL CORE          autoprop for occurrence properties
1243682 F2B          DESIGNVARI    after undocking variant icon cannot be redocked back to GUI
1243686 ALLEGRO_EDITOR GRAPHICS       Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
1243715 CAPTURE       PART_EDITOR    Pin name positioning get changed after rotating or mirroring
1244945 CONCEPT_HDL PDF             PDF Publisher does not include image when file is not located in the root folder
1245568 CONCEPT_HDL CORE          Dual unselect needed for wires attached to other net/source and property is not deselected when component is
1245819 F2B          PACKAGERXL    wrong injected properties information passed during packaging of the design
1245916 SCM          CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?
1246347 CONSTRAINT_MGR CONCEPT_HDL    DEHDL crash if environment variable path has trailing backslash character
1246896 ALLEGRO_EDITOR DFA             DFA_UPDATE on Linux reports err message if the path has Upper case characters
1247019 SIP_LAYOUT    DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown
1247037 CAPTURE       LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number
1247089 CONCEPT_HDL CORE          Group Align or Distribute > Left/Center/Right crashes DEHDL
1247163 CONCEPT_HDL PDF             Physical Net Names in PDF not maintained
1247462 CONCEPT_HDL CORE          Text issue while moving with bounding box
1247464 ALLEGRO_EDITOR UI_FORMS       When using the define B/B via UI the end layer dropdown arrow is partially covered
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
1250270 CONCEPT_HDL CORE          Part Manager Update places wrong parts
1251206 ALLEGRO_EDITOR ARTWORK       Aperture command cannot create appropriate aperture automatically from design.
1251356 ALLEGRO_EDITOR INTERFACES    Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
1251845 ALLEGRO_EDITOR EXTRACT       Crosshatch arcs do not extract correctly
1252143 APD          OTHER          When using the beta "shape to cline" command the tool is removing the shape instead of converting it.
1252737 SIP_LAYOUT    OTHER          SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies
1253424 SCM          SCHGEN          Export Schematics Crashes System Architect
1253508 ALLEGRO_EDITOR INTERFACES    Bug - Export IPC2581 exports Crosshatch shapes as filled
1253554 SIP_LAYOUT    OTHER          SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
1254578 SPIF          OTHER          Specctra crash with Error -1073741819 for Auto router
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error
1254676 GRE          IFP_INTERACTIVE  Rake Lines disappear when Auto-Interactive Breakout is enabled.
1255067 SIG_INTEGRITY  REPORTS       Allegro hangs on Net Parasitc Report generation
1255267 ALLEGRO_EDITOR SKILL          axlDBGetPropDictEntry does not return a list of all objects
1255383 SIP_LAYOUT    IC_IO_EDITING cant move bumps or driver in app mode
1255703 ALLEGRO_EDITOR SKILL          axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
1255759 ALLEGRO_EDITOR INTERFACES    Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool
1256597 GRE          CORE          Allegro GRE crashes while running Plan Spatial, on a particular design
1256650 ASI_PI       GUI             PFE - Cannot generate model file error when using company decap library
1256837 SIP_LAYOUT    DIE_EDITOR    Open and close of die editor takes too long
1257732 CONSTRAINT_MGR OTHER          Bug - Export Analysis Results in CM makes Allegro crash
1257755 ALLEGRO_EDITOR OTHER          Editing time in Display > Status seems to be logging wrong time
1258029 APD          WIREBOND       The bondwire lost after import the wire information
1258979 APD          NC             NC Drill: There is difference of number of drills.
1259484 SIP_LAYOUT    OTHER          SiP - calc min airgap calculate minimum airgap beta feature improvement
1259677 CONCEPT_HDL CORE          hier_write -forcereset cause component prop change.
1259913 ALLEGRO_EDITOR UI_FORMS       Unable to save setting of "use secondary step models in 3D viewer"
1261758 ALLEGRO_EDITOR EDIT_ETCH       Auto Interactive Delay tune (AiDT) is deleting clines
1262543 ALLEGRO_EDITOR MANUFACT       merge shape results in moved void
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss

DATE: 03-28-2014 HOTFIX VERSION: 026
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1190942 CONCEPT_HDL CORE          Cannot copy locked .xcon files
1226085 F2B          PACKAGERXL    Winning net NC shorted with loosing net due to PACK_SHORT
1244894 SCM          SYSTEM_OBJECT Get packaging error when adding a pullup/pulldown resistor
1247432 CONSTRAINT_MGR OTHER          PCB Editor crash
1248560 F2B          DESIGNVARI    Variant Editor > Help about for S024 says unreleased ?
1248712 SIP_LAYOUT    WIREBOND       Changing the charecteristics of a Bond Finger causes it to shift position
1248839 ALLEGRO_EDITOR OTHER          16.6 S023/024 crashes on Logic Change Parts command.
1249000 SIP_LAYOUT    DIE_EDITOR    unexpected shift of instances/pins by co-design die editor
1249186 ALLEGRO_EDITOR INTERFACES    Bug - Export IPC2581 ignores property UNUSED_PADS_IGNORE
1249272 SIP_LAYOUT    IMPORT_DATA    film resistor pins/pads are created on the wrong layer. Always synthesized on top cond layer regardless of config file
1249792 ALLEGRO_EDITOR INTERACTIV    Cannot place rectangular shape as per included width and height.
1249801 ALLEGRO_EDITOR INTERFACES    Bug - Arcs in IPC2581 export are corrupted
1251006 ALLEGRO_EDITOR INTERFACES    IDX does not recognize PKG_PIN_ONE property
1252142 ALLEGRO_EDITOR INTERFACES    Remove inappropriate Conductivity specs from the dielectric layers from the IPC-2581 output
1253047 ALLEGRO_EDITOR SCRIPTS       Bug: SAV file when creating symbol

DATE: 03-13-2014 HOTFIX VERSION: 025
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1194646 CONCEPT_HDL GLOBALCHANGE    Global Update > Global Component Change does not work
1227843 SIG_EXPLORER EXTRACTTOP    Cannot extract the topology correctly.
1231510 ALLEGRO_EDITOR INTERFACES    IDX exchanges with CREO 5.0 issues
1233030 SIG_INTEGRITY  GEOMETRY_EXTRACT Net Parasitic of ground Connection
1236961 SIP_LAYOUT    OTHER          Moving component using Place Manual -H causes mirror_geometry.
1241456 ALLEGRO_EDITOR EDIT_ETCH       When creating Die pins or changing their attributes an oval is placed on the pin
1242461 SIP_LAYOUT    OTHER          SiP Layout - DIE is being mirrored when placing
1242682 CONCEPT_HDL PDF             PDF Pubisher crash DEHDL on design
1242685 SIG_INTEGRITY  SIGNOISE       Incorrect net name was displayed/output if the net include consecutive underscore.
1243357 ALLEGRO_EDITOR INTERFACES    Ability to add any new name
1243758 ADW          COMPONENT_BROWSE I don't see an option to switch between database and cache mode
1244325 ALLEGRO_EDITOR INTERFACES    Merge all the BOMItems with same part number into one single entry in IPC2581B.
1245363 CONCEPT_HDL CORE          Design Entry HDL program crashes upon save
1245790 ALLEGRO_EDITOR PADS_IN       Bug: PADS Translation with 16.6s023 gives parse error
1246343 ALLEGRO_EDITOR SKILL          axlAirGap command is broken in s022
1246419 CONSTRAINT_MGR OTHER          Netrev fails with  SPMHGE-268 on existing design
1246878 CONCEPT_HDL CORE          Changing Symbol in Variant Editor makes schematic page crash
1246884 ALLEGRO_EDITOR GRAPHICS       Infinite cursor disappears from the canvas after step package mapping GUI is closed.
1247016 ALLEGRO_EDITOR INTERFACES    STEP Model of connector cannot be zoomed sufficiently after mapping it to symbol dra file.
1247107 ALLEGRO_EDITOR INTERFACES    Incorrect Spelling in IPC-2581 EntryFillDesc field
1247177 SIP_LAYOUT    WIREBOND       Bondfingers not aligning to wire when tack point on the other wire end is moved from center
1247400 ALLEGRO_EDITOR INTERFACES    option to Export optimized PDF in color

DATE: 02-28-2014 HOTFIX VERSION: 024
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1207753 CONCEPT_HDL OTHER          The Variant Name with a dash is represented by #2d
1234991 ADW          TDA             Team Design does not remove deleted page files from zip files
1235919 CONCEPT_HDL PDF             DNI crosses are not printed on the correct components
1238007 ALLEGRO_EDITOR PARTITION       Import partition removes properties from RKO that were on the exported partition
1238140 CONCEPT_HDL CORE          Design Entry HDL Crashing
1238195 ALLEGRO_EDITOR DATABASE       Via's losing net idenity after being mofifed or replaced.
1238478 ALLEGRO_EDITOR ARTWORK       IPC-2581 negative artwork layers does not recognize shape bounding box value
1238483 ALLEGRO_EDITOR ARTWORK       IPC-2581 not drawing negative artwork  correctly with traces in voids.
1239070 SIP_LAYOUT    WIREBOND       When importing wirebond data onto a Die rotated 90 degrees the WB data is placed in the wrong locations
1239433 SIP_LAYOUT    WIREBOND       Need the Wirebonds to lock to the die aftter importing wirebond data
1239952 ALLEGRO_EDITOR SYMBOL          Allegro crashes with a component rotation of 45 or 135.
1240205 SIP_LAYOUT    DIE_EDITOR    Crash occurs when trying to "oops" for a moved driver in co-design die editor in SiP
1240288 ALLEGRO_EDITOR INTERFACES    Why are some of the mechanical holes not showing up in Step output of thi design, while others are ?
1240305 ALLEGRO_EDITOR INTERFACES    STEP Export gives some errors which are not documented
1240425 ALLEGRO_EDITOR DATABASE       Export ODB is not working on 16.6 HF 22
1240879 ALLEGRO_EDITOR NC             NC ROUTE file is not correct using hot fix 22 of v166
1241904 ALLEGRO_EDITOR INTERFACES    IDX baseline import displays false DRC with Package_height Offset until DRC update is run.
1242266 ALLEGRO_EDITOR INTERFACES    IPC2581 crash on HF22 and HF23
1242433 ALLEGRO_EDITOR INTERFACES    ipc-2581B incorrect LayerRef values in BOTTOM side RefDes elements
1242988 ALLEGRO_EDITOR SKILL          Allegro crashes on skill command axlDesignFlip
1243845 FSP          FPGA_SUPPORT    FSP design created in 16.6 s018 will not open in 16.6 s021

DATE: 02-14-2014 HOTFIX VERSION: 023
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1120183 F2B          DESIGNVARI    Variant Editor Filter returns incorrect results.
1202715 SPIF          OTHER          Objects loose module group attribute after Specctra
1203443 ADW          LRM             LRM takes a long time to launch for the first time
1207204 CONCEPT_HDL CORE          schematic tool crashed during save all
1222101 CONCEPT_HDL CORE          Pins are shorted on a block by the Block's title delimiter
1223709 FSP          FPGA_SUPPORT    Need FSP model of Altera 5AGZME3E3H29C4 FPGA
1224025 ALLEGRO_EDITOR INTERFACES    The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side
1225591 F2B          PACKAGERXL    Aliased net signals starting with equals sign are not resolved correctly in cmgr
1226480 ALLEGRO_EDITOR EDIT_ETCH       Routing time is took to double increase when using the Add Connect because DRC is Allowed.
1229234 FLOWS       PROJMGR       Can't open the part table file from Project Setup
1229555 ALLEGRO_EDITOR ARTWORK       IPC-2581 not recognizing pin offsets correctly.
1229610 FSP          FPGA_SUPPORT    New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7
1229664 ALLEGRO_EDITOR SHAPE          Shape not voiding different net pins causing shorts with no DRC's
1232601 ALLEGRO_EDITOR MANUFACT       Cannot add test point to via on trace.
1232772 ALLEGRO_EDITOR DATABASE       When applying a place replicate module Allegro crashes
1233216 SIP_LAYOUT    DIE_ABSTRACT_IF  Allow more than 2 decimal places for the shrink facor in the add codesign form
1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
1233977 ALLEGRO_EDITOR INTERFACES    single shape copied and rotated fails to create when importing IDX
1234357 SIP_LAYOUT    SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.
1234450 ALLEGRO_EDITOR INTERFACES    clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.
1235587 PSPICE       MODELEDITOR    PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
1236571 ALLEGRO_EDITOR GRAPHICS       Allegro display lock up and panning issues
1237415 ALLEGRO_EDITOR INTERFACES    Multidrill pad is exported with single Drill in the STEP File
1237807 ALLEGRO_EDITOR SCHEM_FTB       The line feed code of netview.dat

DATE: 02-7-2014 HOTFIX VERSION: 022
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
192358  ALLEGRO_EDITOR PADS_IN       Pad_in does not translate some copper shapes
222141  ALLEGRO_EDITOR PADS_IN       PADS_IN: Extra shapes are created when importing PADS design
274314  ALLEGRO_EDITOR PADS_IN       PAD_in boundary defined for flooded area be translated DYN
413919  ALLEGRO_EDITOR PADS_IN       pads_in cannot import width of refdes.
609053  ALLEGRO_EDITOR PADS_IN       "Mils to oversize" of "pads in" did not work correctly for MM data.
666214  CONCEPT_HDL OTHER          Option to increase Line thickness in publishpdf utility
738482  ALLEGRO_EDITOR GRAPHICS       Export image creates black image with Nvidia GeForce 8400M GS Graphics card
982950  CONCEPT_HDL OTHER          change the mouse button for the stroke to have same function with in pcb editor
1020886 SIP_LAYOUT    LEFDEF_IF       a quicker way to promote die pins (by importing macro_pin list)
1032678 CIS          VIEW_DATABASE_PA View Database Part gives incorrect result in complex design with variants.
1033864 ALLEGRO_EDITOR PADS_IN       pads_in doesnot translates teardrops present in design
1054862 CONCEPT_HDL OTHER          Option to increase Line thickness in publishpdf utility
1055252 FSP          PROCESS       Add a synthesis option to target a group to contiguous or consecutive banks
1100772 CONSTRAINT_MGR OTHER          In Constraint Manager > DRC > Spacing the Show Element DRC totals are wrong.
1135020 CIS          DESIGN_VARIANT Variant list is showing wrong results for hierarchical designs
1138951 SIP_LAYOUT    DIE_ABSTRACT_IF  Fix die abstract r/w to properly support pinnumbers on ports
1140042 CONSTRAINT_MGR OTHER          Diff_Pair lengths and analysis are lost after closing and opening Constraint Manager.
1143662 ALLEGRO_EDITOR INTERACTIV    Enhancement Request for RMB - Snap Pick to  options increased to include Pin edge
1147961 PSPICE       SIMULATOR       Simulation produces no output data
1150874 ALLEGRO_EDITOR PADS_IN       Dimensions in PADS are not translated correctly during pads_in translation
1154184 CONSTRAINT_MGR CONCEPT_HDL    Difference in the way topology is extracted in 16.3 versus 16.6
1154770 CAPTURE       PROPERTY_EDITOR  Variant Name property doesn't show value in Variant View mode
1158350 CONCEPT_HDL CORE          Need a warning Message while importing a 16.3 sub-design in a 16.6 Design
1162347 ALLEGRO_EDITOR EDIT_ETCH       Enh- Allow new option in Move command such that it allows stretching etch using only 45/90 degree segments directly
1165553 ALLEGRO_EDITOR INTERACTIV    Subclass list invoked from the status window does not represent correct colors.
1168079 FSP          MODEL_EDITOR    Clicking OK or Save As in rules editor allows user to overwrite the master with no warning
1172043 SCM          OTHER          : in pin name causes SCM to crash
1172207 CAPTURE       STABILITY       Capture crash while adding new part from Spreadsheet
1172743 ADW          TDA             Allowed character set for the check-in comments is too limited
1174099 SIP_LAYOUT    WIREBOND       Option to reconnect wire based on 縫in name� in the Wire Bond Replace
1177672 APD          IMPORT_DATA    Netlist-in wizard didn縯 provide detail information about what columns have been ignored by import process
1177714 CONCEPT_HDL RF_LAYOUT_DRIVEN RF component's LOCATION property can not be set to invisible
1177820 CONSTRAINT_MGR INTERACTIV    Done the Allegro command when attempting to launch CM
1178586 ALLEGRO_EDITOR EDIT_SHAPE    Number of digits displayed after the decimal point of Shape Creation function does not match the Accuracy of BRD
1179688 PSPICE       STABILITY       pspice crash for particular HOME variable vlaue
1179827 SIP_LAYOUT    OTHER          SiP Layout - Spreadsheet to Symbol export - enable field to add Keywords for data fields to excell cells
1179879 SIP_LAYOUT    STREAM_IF       Data file corrupt when exporting Stream data from SiP database.
1180164 F2B          BOM             BOM csv data format converts to excel formats
1180477 ALLEGRO_EDITOR INTERFACES    IPC-356 output is listing a duplicate location in the comment section
1180932 SIP_LAYOUT    OTHER          SiP Layout - Symbol to Spreadsheet add option for writing to existing spreadsheet
1181377 ALLEGRO_EDITOR INTERACTIV    Pick Releative does not work correctly with RMB-Move Vertex
1181516 ALLEGRO_EDITOR DRC_CONSTR    Getting a "Thru Pin to Route Keepout Spacing" when there should not be one.
1181739 GRE          CORE          Running Plan > Spatial crashes GRE
1181935 ALLEGRO_EDITOR DATABASE       Enh. Property that allows internal C-C DRC errors
1182185 SIP_LAYOUT    OTHER          SiP Layout - Import symbol spreadsheet - suppress Family for the font in the XML spreadsheet
1182566 SIP_LAYOUT    OTHER          SiP Layout - Spreadsheet to symbol - Enhance ability of spreadsheet exchange to allow for a portion of a full pin map
1182599 CONSTRAINT_MGR DATABASE       CM Prop Delay Actuals do not update after Z Axis option is turned ON or OFF and Analyze is run.
1182892 CAPTURE       SCHEMATIC_EDITOR Pspice marker rotation before placement
1183682 ALLEGRO_EDITOR DRC_CONSTR    Implement Nodrc_Sym_Pin_Soldermask & Nodrc_Sym_Pin_Pastemask to symbol level
1185445 SIP_LAYOUT    DIE_ABSTRACT_IF  Die abstract export needs to be able to select xda file type when browsing
1185932 ALLEGRO_EDITOR SHAPE          Soldermask in solder mask void DRC
1185946 CONCEPT_HDL CORE          Ericsson perfomance testing report 5 sept 2013
1187213 FLOWS       PROJMGR       Unable to lock the directive: backannotate_forward
1187444 ALLEGRO_EDITOR DRC_CONSTR    With this design Database check prompts error "SPMHGE-47: Error in call to batch DRC"
1187597 ALLEGRO_EDITOR DRC_CONSTR    No Package to Package Spacing DRC error, when symbol overlap sideways at 45 degree.
1187723 FSP          PROCESS       Synthesis can fail depending on component placement
1188164 SIP_LAYOUT    OTHER          SiP Layout - Spreadsheet interfaces Import Export and Add Component - include Keyword for NET_GROUP
1188245 CONCEPT_HDL CORE          INFO(SPCOCN-2055): You cannot run the CHANGE command in a read only schematic
1190927 CONCEPT_HDL CORE          Check sheet does not report shorted signal/power nets if power symbol is connected to a pin
1191497 ALLEGRO_EDITOR INTERACTIV    ENH: Adding names to the text block parameters numbers
1192005 SIP_LAYOUT    IMPORT_DATA    Import SPD2 is missing 1 smart metal shape from file
1192204 ALLEGRO_EDITOR EXTRACT       Need ability to extract vias that are labeled as microvia
1193063 ALLEGRO_EDITOR MANUFACT       TestPrep log displays "Pin is not accessible from bottom". The component is through hole.
1193418 ALLEGRO_EDITOR GRAPHICS       3D Viewer can`t export image  in both SPB166S015 and SPB165S047
1194305 SIP_LAYOUT    EXPORT_DATA    export package overlay creates file with no package info
1194418 APD          IMPORT_DATA    issue when do File->import->netlist-in wizard
1195279 F2B          PACKAGERXL    Ptf files are not being read when packaging with Cache
1195374 ALLEGRO_EDITOR INTERACTIV    Modules are not showing up in Tools > Module reports
1196603 SIP_LAYOUT    EXPORT_DATA    Change form for "Write Package Overlay..." to better support longer lists of routing layers
1197302 CONSTRAINT_MGR UI_FORMS       Inconsistancy in selection of object for Spacing Constraint Worksheet
1197399 CAPTURE       OTHER          Draw toolbar disappears when using Print Preview
1197543 ADW          TDA             TDO does not correctly show deleted pages
1198033 CONCEPT_HDL CORE          Signals do not get highlighted when Show Physical Net Name is option enabled
1198468 ALLEGRO_EDITOR GRAPHICS       3D_step model does not show the correct view in 3D_Viewer when symbols have multiple place_bounds.
1198617 CIS          GEN_BOM       Mech parts are showing with Part reference in CIS BOM
1199764 ALLEGRO_EDITOR SHAPE          Allegro crashes when trying to delete small island on POWER layer.
1200232 ALLEGRO_EDITOR INTERACTIV    Moving all items including board outline which is made of lines does not move the board outline in General Edit Mode.
1200748 ALLEGRO_EDITOR INTERACTIV    Additional pin edge vertex object to snap pick
1201056 ALLEGRO_EDITOR DATABASE       Unsupported functionality strip design creates a .SAV file
1201638 CIS          PART_MANAGER    Part retains previous linking inside the subgroup
1201834 ALLEGRO_EDITOR PLOTTING       Bug: Import Logo command changes resulting imported object
1202406 SIP_LAYOUT    OTHER          enable the dynamic display of component pin names for co-design dies in Sip Layout
1202431 CONCEPT_HDL PDF             The publishpdf -variant option should have a "no graphics" option
1202717 ALLEGRO_EDITOR DATABASE       About Warning(SPMHA1-108):Illegal line segment ... end points.
1203459 CONSTRAINT_MGR INTERACTIV    Object Report has no mechanism to output information for a specific design.
1204544 F2B          DESIGNVARI    Variant Editor does not warn on save if no write permissions are on the file
1205500 FSP          CONSTRAINTS MAPP FSP FPGA port mapping VHDL syntax
1205952 ALLEGRO_EDITOR GRAPHICS       Step Model for Mechanical Part is visible in 3D viewer only when Etch Top Subclass is enabled
1206103 SIP_LAYOUT    IC_IO_EDITING add port name property to pins, and add Skill access I/O driver cell data
1206546 CAPTURE       ANNOTATE       User assigned refdes are resetting when 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom�
1206561 ALLEGRO_EDITOR GRAPHICS       Not all mechanical symbols made with Step files are displayed in the 3D View
1207125 SIG_INTEGRITY  ASSIGN_TOPOLOGY  ECSet mapping wrong for 2 bit in a 4bit bus
1207386 CAPTURE       GENERATE_PART Altera pin file not generating the part properly
1207629 CAPTURE       TCL_INTERFACE Bug: GetMACAddresses tcl command not working
1207994 CAPTURE       TCL_INTERFACE TCL pdf export in 16.6 fills DOT type pins with black color
1208017 F2B          DESIGNVARI    sch name is not same when updating Schematic View while backannotating Variant
1209363 ALLEGRO_EDITOR INTERFACES    When placing pins using the polar command the tool returns 4500.00 for 45 degrees.
1209769 CONCEPT_HDL CORE          Top DCF gate information missing
1210194 CONCEPT_HDL CONSTRAINT_MGR HDL crashes with Edit Via List dialog box
1210442 CONCEPT_HDL INFRA          Save design gives ERROR(SPCOCN-1995): Non synchronized constraint property found in schematic page
1210685 ASI_PI       GUI             User can't edit padstack in PowerDC-lite
1210744 SIG_INTEGRITY  SIGWAVE       SigWave: FFT Mode Display unit seems not to be correct
1210829 CAPTURE       NETLIST_VERILOG  Shorted port is missing from verilog file
1210850 CONCEPT_HDL CORE          DE-HDL backannotation crashing after instantiating specific cell from Ericsson BPc Library
1211620 ADW          COMPONENT_BROWSE Component Browser Performance
1212102 ALLEGRO_EDITOR INTERACTIV    Shape edit boundary adds arc mirrored to the highlighted preview.
1213294 CONCEPT_HDL SECTION       DE-HDL windows mode multiple section fails to section first contactor pin from column of individual pins
1213402 APD          DATABASE       The old "ix 0 0" fix  is now causing the features to lose nets entirely.
1213694 ALLEGRO_EDITOR PARTITION       Via connected to Dummy Net pin in Partition gets connected to shape on the board after importing partition
1214247 CONSTRAINT_MGR UI_FORMS       Selecting the "All" folder in Spacing Constraints in CM does not automatically select the first column for editing
1214320 SIG_INTEGRITY  SIGNOISE       signoise command with -L and -k option
1214433 CONCEPT_HDL CORE          Genview does not update sym_1 with ports added to the schematic
1214909 ALLEGRO_EDITOR NC             NC Drill Legend show extra rows for drills
1214916 SIP_LAYOUT    OTHER          package design integrity check for via-pin alignment with fix enabled hangs
1215954 SIG_INTEGRITY  SIMULATION    Cycle.msm does not exist error when simulating extracted net
1216328 CAPTURE       STABILITY       Capture crash
1216993 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crash on SPB16.50.049
1217450 F2B          BOM             ERROR 233: Output file path does not exist
1217612 ALLEGRO_EDITOR INTERACTIV    Replace padstack will not replace padstacks that have multiple alphabetic characters in the pin name - AB21-AB37
1217823 ALLEGRO_EDITOR INTERACTIV    Compose shape fails with SPMHIS-473
1217887 ALLEGRO_EDITOR INTERFACES    An undo option to be made available in the STEP Package Mapping window
1218665 ALLEGRO_EDITOR INTERFACES    In step viewer, the bottom side parts are placed above the pcb board surface
1219053 PSPICE       PROBE          PSpice crash with the attached Design
1219067 ALLEGRO_EDITOR EDIT_ETCH       dynamic fillets behavior is unstable
1219095 ALLEGRO_EDITOR MANUFACT       Design Cross section chart is tapered for two layer board
1219126 ALLEGRO_EDITOR SKILL          Skill issue with axlRefreshSymbol()
1220701 ALLEGRO_EDITOR INTERACTIV    View > Windows > Worldview (showhide view command) fails with command not found
1221057 ALLEGRO_EDITOR REPORTS       Units in Cross section report for spacing is not synced with the design
1221139 ALLEGRO_EDITOR EDIT_ETCH       Delay tune is not tuning differential pair
1221157 SIP_LAYOUT    IMPORT_DATA    import spd2/na2 file is not importing data correctly into sip
1221163 SIG_INTEGRITY  GEOMETRY_EXTRACT Simulation aborts with severe convergence issue when coupled vias is enabled.
1221416 ALLEGRO_EDITOR DATABASE       strip design for function type
1221931 ALLEGRO_EDITOR DATABASE       Fatal software error when embedding component
1222105 CONCEPT_HDL CORE          Moving Pins around the edge of a Block causes the text of the pin to change its text size.
1222124 APD          DATABASE       Same Net DRC's exhibiting inconsistent behavior.
1222272 SIG_EXPLORER EXTRACTTOP    Cannot extract net or open SigXplorer after selecting a netgroup
1222329 ALLEGRO_EDITOR SHAPE          STEP-Model  Symbol which has place bound bottom is on Top
1223183 SIP_LAYOUT    BGA_GENERATOR Getting an incorrect error message when using the BGA generator with a long BGA name.
1223662 ALLEGRO_EDITOR REFRESH       Allegro crashes when trying to refresh symbol
1223932 CONCEPT_HDL CORE          DEHDL block desend does not find 1st page if its not page1
1223940 CONSTRAINT_MGR UI_FORMS       Unable to change CLOCK name in Setup/Hold Worksheet under Timing in CM.
1224127 SIG_INTEGRITY  IRDROP          Is the old static IRDrop in 16.6 officially supported?
1225492 PCB_LIBRARIAN  CORE          PDV expand vector pins resizes symbol outline to maximum height again
1225546 CONSTRAINT_MGR ECS_APPLY       nets where the referenced ECS maps correctly in constraints manager for front end but not in back end
1226405 ALLEGRO_EDITOR INTERFACES    File > Export > IDF ask for filter config file eventhough it is created in same session and stored in parent folder
1226448 PDN_ANALYSIS PCB_STATICIRDROP License failure about PDN Analysis with XL and GXL
1228721 SIP_LAYOUT    OTHER          File Export Netlist Spreadsheet enhance sort to be a natural method per Jedec according to customer

DATE: 12-20-2013 HOTFIX VERSION: 021
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1214932 ALLEGRO_EDITOR OTHER          Allegro will crash when performing show dimension on linear dimensions.
1215045 ALLEGRO_EDITOR SKILL          Successive file open / ipc calls crashes Allegro 16.6
1215115 ALLEGRO_EDITOR NC             drawing name doesn't display in the ncdrill.log file
1216028 SIP_LAYOUT    PLACEMENT       Design will not update embedded component symbols.
1218451 ALLEGRO_EDITOR DRC_CONSTR    Route Keepout to Pin DRC created even after adding Void in RKO shape
1218636 ALLEGRO_EDITOR SCHEM_FTB       netin process will rotate embedded symbols
1218706 CONSTRAINT_MGR CONCEPT_HDL    NCC associations get deleted from FE CM

DATE: 12-4-2013 HOTFIX VERSION: 020
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1116426 F2B          PACKAGERXL    Packaging in 16.6 increased by 3 folds compared to 16.3
1190095 CONCEPT_HDL CORE          In Windows mode select the part and click on version placed selected version +1.
1199410 CONSTRAINT_MGR CONCEPT_HDL    Constraint Differences Report window hangs in 16.6-s016
1199425 CONSTRAINT_MGR CONCEPT_HDL    Import Physical fails (the cmfeeback.exe has stopped working) in 16.6-s016
1199700 PSPICE       NETLISTER       Netlist fails on addition of netgroup
1200936 CONCEPT_HDL PDF             publishpdf fails if UNC paths are provided from the command line
1202391 CONSTRAINT_MGR OTHER          Getting 'An Invalid argument was encountered' when generating Net Class-Class report in CM
1202587 CONCEPT_HDL CREFER          Crefer schematic reports cannot be deleted on Linux.
1203143 GRE          CORE          GRE crashes on running Plan > Spatial
1206019 ALLEGRO_EDITOR INTERACTIV    Allegro needs to be restrated to read steppath with 16.6 S017
1207050 ALLEGRO_EDITOR INTERACTIV    Refresh Padstack fails on Warning
1207178 CONCEPT_HDL CORE          Aqua color on wire does not matches icon color
1208152 F2B          DESIGNASSC    ERROR: Dictionary File: cmdict.l could not be found
1208276 APD          STREAM_IF       Stream in fails to import what Allegro exported
1208345 ALLEGRO_EDITOR SKILL          Why axlChangeLayer not working for shapes on this attached skill file?
1208351 ALLEGRO_EDITOR SKILL          axlFilmCreate do not define the IPC2581 domain correctly.
1208467 PCB_LIBRARIAN  VERIFICATION    con2con mangles cell data after checking cell having syntax errors on part_table
1208579 SIG_INTEGRITY  GEOMETRY_EXTRACT Incorrect traces are extracted when void area is less than anl_min_void_area setting
1209347 ALLEGRO_EDITOR PARTITION       Import partition that has diametral dimensions will crash Allegro
1209897 ALLEGRO_EDITOR PADS_IN       Pads_in will not translate design.
1209902 PCB_LIBRARIAN  CORE          PDV crashes reading part
1210183 PSPICE       SIMULATOR       SimSrvr crash with ORPROBE-3211 RPC Server unavailable Message
1210408 ALLEGRO_EDITOR EDIT_ETCH       AiBT hangs when doing interactive breakout on bundles using latest hotfix.
1210443 ALLEGRO_EDITOR INTERFACES    Allegro Design Publisher does not create fully searchable PDF for some of the text that are present or certain layers
1210876 CONCEPT_HDL ARCHIVER       Archiver wrongfully deletes directories.
1211839 CONSTRAINT_MGR DATABASE       Topology can't be extracted correctly.
1212709 ALLEGRO_EDITOR DATABASE       No connect can`t be detected in SPB165S048
1213752 CONSTRAINT_MGR OTHER          "Show Constraint Difference Report" option at File > Import > Logic does not retain the last setting

DATE: 11-15-2013 HOTFIX VERSION: 019
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1176155 CONCEPT_HDL CORE          Graphics remnants with 16.6 QIR 3
1178272 CONCEPT_HDL OTHER          Verilog netlist does not include split blocks correctly
1190782 FSP          FPGA_SUPPORT    Support for Altera > 5SGXEA9N2F45 device.
1194140 ADW          LRM             SYNC_PROPERTIES is not resolving issues a based sync_properties settings
1195744 APD          EDIT_ETCH       Diff_Pair routing fails on certain Uvias in the pair.
1196704 ALLEGRO_EDITOR INTERFACES    ENH: During ipc2581 export checkboxes corresponding to 縈iscellaneous Image Layers� should automatically get selected
1198340 ALLEGRO_EDITOR OTHER          Multiple -product option on the Allegro command line does not access the second -product
1198596 ALLEGRO_EDITOR INTERFACES    When copper thickness is increased for the outer layers, step Viewer does not show correct component position.
1199673 PCB_LIBRARIAN  OTHER          Component Browser fails to load footrpints if they are set with UNC path
1199889 ALLEGRO_EDITOR DATABASE       Allegro crashing with latest hotfix.
1200303 ALLEGRO_EDITOR GRAPHICS       3D Viewer does not update after changing STEP model mapping
1200449 ALLEGRO_EDITOR REPORTS       Allegro crashes when generating Net Loop Report.
1200915 ALLEGRO_EDITOR DATABASE       Reducing accuracy of this specific design crashes Allegro
1201011 ADW          COMPONENT_BROWSE Component Browser crashes in DB mode
1201376 ALLEGRO_EDITOR INTERFACES    Allegro hangs when trying to map a specific STEP model to a package drawing.
1201897 SIP_LAYOUT    IMPORT_DATA    BGA Pin Colors not matching the Colors defined in the Symbol Spreadsheet after updating.
1202709 ALLEGRO_EDITOR INTERFACES    STEP File generated from Allegro is not overwritten when the variable "set ads_textrevs
1202820 ALLEGRO_EDITOR INTERFACES    Different xml generation for same step model on S106 and S017
1202842 ALLEGRO_EDITOR INTERFACES    Step model invisible for one pin dra in allegro 16.6 symbol editor
1202983 ALLEGRO_EDITOR SHAPE          Shape voiding creates DRC with Route Keepout
1203125 ALLEGRO_EDITOR OTHER          Exporting STEP file with External copper enabled does not show all copper when viewed with Solid Edge or Inventor
1203236 ALLEGRO_EDITOR INTERFACES    IPC2581 output with crosshatched shape is not correct
1203995 CONCEPT_HDL CHECKPLUS       CheckPlus rule, local_signal_no_offpage_body, getting an incorrect failure.
1204629 ALLEGRO_EDITOR SKILL          axlUIDataBrowse crashes the editor or returns error
1204640 SIP_LAYOUT    DIE_EDITOR    Concurrent co-design update fails
1204881 SIP_LAYOUT    BGA_GENERATOR Pin numbers are messed up after deleting a pin at a staggered bga
1204885 CONCEPT_HDL CONSTRAINT_MGR Cant assign discrete models after the wrong model was removed.
1205374 ALLEGRO_EDITOR OTHER          pdf out command creates incorrect drill Symbol Characters placement in pdf file when setting film mirrored.
1205729 SIP_LAYOUT    DIE_EDITOR    update of codesign db fails on exit from die editor
1205801 ALLEGRO_EDITOR OTHER          Tool crash when do export IPF.
1205881 CONSTRAINT_MGR OTHER          In CMGR , Objects > Create crashes Allegro

DATE: 10-25-2013 HOTFIX VERSION: 018
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1118303 CONCEPT_HDL CONSTRAINT_MGR can not prdefine default units in HDL
1174901 ALLEGRO_EDITOR GRAPHICS       Spurious odd lines are shown in shapes and text that are not part of the design with opengl
1176990 CONCEPT_HDL OTHER          DEHDL BOM tool doesn縯 see similar names.
1179665 GRE          CORE          Plan Topological Crashes after around 8 hours of routing.
1188193 CONCEPT_HDL CHECKPLUS       CheckPlus not recognizing PIN as a base object.
1189100 SCM          OTHER          Replace part in SCM using ADW as library fails
1189507 SCM          SCHGEN          ERROR(SPCOCN-2009): Package error after second schgen run with Preserve mode.
1192391 CONSTRAINT_MGR CONCEPT_HDL    Restore from definition deletes local objects in other blocks
1194597 FSP          OTHER          Pin definition problem
1195202 SIP_LAYOUT    LEFDEF_IF       Cannot add .lef files in IC Library Manager. Getting warning message WARNING(SPMHLD-52)
1195309 GRE          CORE          GRE crashing during Plan Spatial.
1197262 ALLEGRO_EDITOR MANUFACT       Angular Dimension created in symbol is placed w.r.t. board origin and angle is blank
1198521 CONCEPT_HDL OTHER          cadence DEHDL issue - Note for Hotfix_SPB16.60.016_wint_1of1
1199219 ALLEGRO_EDITOR INTERFACES    Question on STEP Model export which uses PLACE_BOUND layer for any symbols that do not have STEP model mapped
1199235 ALLEGRO_EDITOR SCHEM_FTB       capture's behavior is redundant while creating pcb editor netlist
1199323 GRE          IFP_INTERACTIVE  Crash when importing logic
1199368 SIP_LAYOUT    DIE_EDITOR    Refresh of die abstract in die editor with this design takes over two hours
1199760 ALLEGRO_EDITOR DATABASE       Allegr won't display Soldermask Top layer

DATE: 10-10-2013 HOTFIX VERSION: 017
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
735992  ADW          LIB_FLOW       Create Test Schematic does not use the correct package type
1121403 FSP          PROCESS       "Assign to Pin" not getting obeyed by Synthesis.
1141844 RF_PCB       DISCRETE_LIBX_2A ADS Lib Translation Pin Soldermask/Pastemask missing
1169269 ALLEGRO_EDITOR DRAFTING       Dimension placed on package symbol moves to different place when it is placed on brd file.
1170488 ALLEGRO_EDITOR MANUFACT       Dimension text(on .psm) move to different position, when it is placed on .brd.
1173345 CIS          CRYSTAL_REPORTS  Crystal Report - Display Parameter dialog for export option
1181759 SCM          LVS             SCM Crash when doing update all that executing import physical command.
1182499 ALLEGRO_EDITOR OTHER          Step export to include through hole padstacks (all pins and via) drill.
1184682 CONCEPT_HDL CONSTRAINT_MGR Net Constraint not transferring to layout from schematic
1185524 F2B          PACKAGERXL    Enhancement User would like notification of pack_short in pxl.log
1185902 ALLEGRO_EDITOR SHAPE          Update shapes dont clear some diffpairs in HF15
1186152 ADW          LRM             Part Status for Deleted Part in LRM is distinguished with other part status
1186387 ALLEGRO_EDITOR OTHER          DXF cannot catch offset value in s047 hotfix.
1186805 ALLEGRO_EDITOR OTHER          Exported STEP file missing multiple components placed on board
1186818 ALLEGRO_EDITOR COLOR          Custom color not retained during dehilight
1187196 CONCEPT_HDL CORE          TOC not populating (page 1)
1187667 F2B          PACKAGERXL    Existing hard LOCATION property in drawing was left unchanged
1188264 ALLEGRO_EDITOR MODULES       Some fillets not regenerated in module created from a board file.
1190144 ALLEGRO_EDITOR OTHER          Fillet shape is not genrated around cline
1190210 F2B          BOM             The bomhdl.exe fails - MFC Application has Stopped Working
1190618 ALLEGRO_EDITOR GRAPHICS       Enhancement for Visible grid
1190813 ALLEGRO_EDITOR INTERFACES    3rd party netlist file in TEL format fails syntax check but imports successfully
1190895 ALLEGRO_EDITOR EDIT_ETCH       Route delay meter displays violation when sliding diff pair
1190908 F2B          OTHER          DE-HDL aborts if dummy net is being cross-probed from PCB Editor
1190990 CONCEPT_HDL CORE          Mismatch in .csa and .csb files
1191008 CONCEPT_HDL CORE          Remove Binary File feature doesn't work
1191514 SCM          PACKAGER       Packaging error PKG-100
1191517 ALLEGRO_EDITOR DRAFTING       Metric +tolerance when using dual dimensions is not displayed correctly
1192561 ALLEGRO_EDITOR GRAPHICS       Padstack with offset is not showing correctly in the 3D Viewer.
1192916 ALLEGRO_EDITOR EDIT_ETCH       Wrong static phase values are shown in the dynamic timing meter for certain Diff pairs compared to CM.
1194197 ALLEGRO_EDITOR OTHER          Step export to include through hole padstacks.
1194239 PSPICE       DEHDL          Associate Model does not launch from DE-HDL
1194736 PSPICE       SIMULATOR       Design causes RPC failure when run consectively
1195139 ALLEGRO_EDITOR PLACEMENT       Components disappears from board file once they moved

DATE: 09-27-2013 HOTFIX VERSION: 016
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
548538  CAPTURE       NETLIST_ALLEGRO  Enhancement:Include mechanical parts in Allegro netlist
1076579 CAPTURE       GENERAL       Display value only if value exists
1083904 FSP          GUI             Need Filter in Change FPGA dialog to select desire FPGA from the long list.
1089313 ALLEGRO_EDITOR INTERFACES    Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility
1095728 ALLEGRO_EDITOR EDIT_ETCH       Slide to grab adjacent elements when extend selection is enabled
1102698 SIG_INTEGRITY  ASSIGN_TOPOLOGY  ECset will map on single ended nets but fails when the two nets are define as a diff pair.
1104071 SIG_INTEGRITY  REPORTS       Shape Parasitic value changes for bottom shape for changes in top shape
1117731 FSP          POWER_MAPPING Ability to sort in Power Regulator forms
1121539 FSP          CONFIG_SETTINGS  Cannot configure special FPGA pins (temperature diodes)
1122721 FSP          MODEL_EDITOR    Partial copy-paste overwrites the complete cell in XML Editor
1123238 FSP          TERMINATIONS    Report functionality for terminations defined in the complete design.
1123364 FSP          GUI             Clicking on column header should sort the column.
1123403 FSP          EXTERNAL_PORTS Improper checkbox selection for 緿o Not Connect� or 縀xternal Port� column
1125611 CONCEPT_HDL OTHER          display unconnected pin in schematic pdf.
1129871 ALLEGRO_EDITOR INTERACTIV    Wire Profile Editor can't read mcmmat.dat in working directory.
1133688 ALLEGRO_EDITOR GRAPHICS       Enhancement request to enable 3D Viewer to show STEP model from .dra file.
1141747 ALLEGRO_EDITOR GRAPHICS       3D view dooesnot displays height if step_unsupported_prototype variable set
1142215 SIG_INTEGRITY  SIMULATION    PULSE_PARAM set on DiffPair wasn't used for designlink simulation.
1142798 ALLEGRO_EDITOR INTERFACES    Step file output is incorrect in step viewer when composed of arcs and line.
1142894 FSP          GUI             Ability to RMB on a header and select `Hide Column�
1142940 FSP          EXTERNAL_PORTS Issue with checking/unchecking "Do not connect" and "External port" cells
1142949 CONCEPT_HDL SKILL          Usage of "Preferences > License Settings� in FSP
1143091 SIP_LAYOUT    SYMB_EDIT_APPMOD symed:  When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract
1144371 CONCEPT_HDL COMP_BROWSER    Component Browser search results are inaccurate
1145033 ALLEGRO_EDITOR PLACEMENT       When aligning components with options in Placement mode displays no busy indicator
1145286 CONCEPT_HDL CORE          Directive required for switching off the console
1145800 ALLEGRO_EDITOR GRAPHICS       Spurious odd lines are shown in shapes and text that are not part of the design with opengl.
1147899 ALLEGRO_EDITOR SHAPE          Autovoid two overlapping shapes that share the same net
1149996 ALLEGRO_EDITOR EDIT_ETCH       Routing does not follow the ratsnest 'pin to pin'.
1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.
1152577 ALLEGRO_EDITOR DATABASE       slide removes cline seg
1152751 CONCEPT_HDL CORE          Option to double-click and copy the Netname
1153220 ALLEGRO_EDITOR INTERFACES    ENH: option to supress header/footer during PDF Export
1153625 ALLEGRO_EDITOR INTERFACES    If Symbol has place bound bottom, the step model shows incorrect placement.
1153813 CONCEPT_HDL CORE          Spaces should not be allowed in the signal name entry form
1153857 CONCEPT_HDL CORE          Changing different power symbol should maintain the schematic level properties.
1155161 CONCEPT_HDL CORE          Add Signal name: Suggestion box overlaps with the typed signal name that is typed
1155922 CONCEPT_HDL OTHER          How can I use the batch mode for PDF Publisher and print a variant overlay?
1156858 ALLEGRO_EDITOR PADS_IN       PADS Translator: Missing drill on square PTH padstack
1157362 APD          3D_VIEWER       Need a way to color multiple nets in 3D viewer from APD/SiP.
1158130 CONSTRAINT_MGR ANALYSIS       Constraint Manager do not display the Cumulative Result in Reflection Simulation
1158210 ALLEGRO_EDITOR SHAPE          SIP Layout happens crash while users move the shape with route keep-out
1158452 SIG_INTEGRITY  GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle
1158827 ALLEGRO_EDITOR EDIT_ETCH       Slide a via in pad automatically add cline back to via to pin.
1158871 PCB_LIBRARIAN  IMPORT_CSV    PIN TEXT is not automatically added when importing the .csv file
1159738 ALLEGRO_EDITOR INTERACTIV    Selecting the Cancel button in the Text Edit command does not cancel the text.
1159878 SIG_EXPLORER OTHER          Ecset mapping dont follow topology template
1159971 ALLEGRO_EDITOR MANUFACT       Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file
1160017 SIP_LAYOUT    DIE_ABSTRACT_IF  Add text to clarify shrink operation
1160507 APD          EDIT_ETCH       Script not playing back what was recorded when sliding lines
1161261 ADW          TDO-SHAREPOINT Schema for TDO-SP fails on Japanese OS
1161538 CONCEPT_HDL CORE          Espice model value edited in DE HDL  & then netlisting done, but it doesnt changes the earlier assigned model in Allegro
1161636 ALLEGRO_EDITOR DRAFTING       need new function for PDFout : hatching shape
1161777 ALLEGRO_EDITOR OTHER          default line width for PDF output
1162383 CONCEPT_HDL CHECKPLUS       Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.
1162562 CAPTURE       STABILITY       Capture crash on second attempt of pspice netlist creation in 16.6
1162629 FSP          PROCESS       "Load Process Option" under Run does not work properly
1162686 CONCEPT_HDL CORE          Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE
1163149 ALLEGRO_EDITOR DATABASE       Autosilk creates Illegal arc to corrupt database
1163439 ALLEGRO_EDITOR COLOR          Duplicate Views Listed in Visibility Tab.
1163521 CONCEPT_HDL COMP_BROWSER    System Architect crahes on replace
1163709 CONCEPT_HDL CONSTRAINT_MGR Loosing Diffpairs when reimport block or restore from definitioin
1163902 APD          EXPORT_DATA    Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?
1164337 CONCEPT_HDL CORE          Cannot delete attribute filter value in PDF > General > Attribute Filter list
1164365 ALLEGRO_EDITOR INTERACTIV    Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol
1164769 APD          VIA_STRUCTURE The replace via structure command does not accept a single canvas pick.
1165026 ASI_SI       GUI             EMS3D exist in Via Model Setup of SI base.
1165561 CAPTURE       DRC             File > Check and Save clears waived DRCs
1165631 CAPTURE       STABILITY       Capture crash in the hierarchy tab of Project Manager window
1165836 SIG_INTEGRITY  GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)
1165911 FSP          PROCESS       Editing group name in protocol causes incorrect Process option checked
1166026 ALLEGRO_EDITOR DATABASE       Running DB Doctor removes net name from vias
1166034 SIP_LAYOUT    OTHER          SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle
1166074 GRE          CORE          GRE crashes during planning phases
1166319 ALLEGRO_EDITOR PLACEMENT       Swap not succeed
1166484 SIP_LAYOUT    WIREBOND       Bondfinger "Align With Wire" problem during move
1166530 ALLEGRO_EDITOR INTERACTIV    Bug: Mirror in Placement Edit resets the options tab for Edit > Move
1166819 CONCEPT_HDL CORE          Cadence DEHDL Text Size Issue
1167847 CAPTURE       PROPERTY_EDITOR  Implementation name length greater than 31 character causes capture crash
1167887 F2B          OTHER          Improve message on symbol to schematic generation
1168369 F2B          DESIGNVARI    Variant don縯 appear in increasing order while Annotate.
1168629 APD          OTHER          Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD
1168678 ALLEGRO_EDITOR NC             Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.
1168798 ALLEGRO_EDITOR INTERACTIV    Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk
1168830 ALLEGRO_EDITOR DRC_CONSTR    missing DRC-marker for package to package check
1168864 ALLEGRO_EDITOR CREATE_SYM    Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty
1169213 PSPICE       SIMULATOR       Parametric sweep is giving incorrect reuslts
1169436 FSP          FPGA_SUPPORT    Add support for Cyclone V CSX and CST parts
1170108 ALLEGRO_EDITOR INTERACTIV    Enhancement to preserve Rat T location for Topology assigned schedule
1170313 SIP_LAYOUT    LOGIC          scm adding additional pin names and unassigned property to codesign die chips file
1171136 CONCEPT_HDL CORE          Page Number should also be displayed in Import Design Window.
1171747 ALLEGRO_EDITOR PLACEMENT       Allegro crashes when doing a gate swap between components
1172183 ALLEGRO_EDITOR INTERACTIV    Alignment modules fails on equal spacing
1173183 ALLEGRO_EDITOR DRC_CONSTR    Undesired Same net DRC for overlapping Pin and Via
1174067 ALLEGRO_EDITOR DRC_CONSTR    Soldermask to shape drc does not show if the layer is a PLANE.
1174338 ALLEGRO_EDITOR PLACEMENT       preview has rotated pads
1175307 CONSTRAINT_MGR ANALYSIS       CMGR fails to report RPD DRC for accuracy 4 - mm
1175537 ALLEGRO_EDITOR REPORTS       net loop report crashes Allegro. Design specific
1176126 ALLEGRO_EDITOR INTERFACES    3D viewer doesnot change models units dynamically
1176281 CONCEPT_HDL CORE          Option to Auto-hide excluded modules
1176413 ALLEGRO_EDITOR MANUFACT       Q - testprep parameter settings is not retained, what could be the cause..
1176791 ALLEGRO_EDITOR GRAPHICS       Spurious odd lines are shown in shapes and text that are not part of the design with opengl
1178052 ALLEGRO_EDITOR SHAPE          SIP crashes during shape degassing.
1178158 ALLEGRO_EDITOR INTERFACES    Export step file creates step file of same height
1178201 ALLEGRO_EDITOR GRAPHICS       Large oval pads rendered as oblong hexagons in the 3D viewer
1178671 ALLEGRO_EDITOR GRAPHICS       3D Viewer in package symbol editor not displaying correct place bound shapes.
1178725 ALLEGRO_EDITOR OTHER          With fillets present, rat lines do not point to the closest endpoint.
1178972 CONSTRAINT_MGR ANALYSIS       The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.
1179093 ALLEGRO_EDITOR SHAPE          Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas.
1179109 ALLEGRO_EDITOR OTHER          DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version
1179571 ALLEGRO_EDITOR ARTWORK       Artwork crash and artwork log report Aparture missing
1179636 SPECCTRA    ROUTE          Route Automatic will not start if NET_SHORT are attached to a mec-pin
1179659 SIP_LAYOUT    DIE_EDITOR    die edit on co-design die losing c4 bumps
1180306 ALLEGRO_EDITOR ARTWORK       When trying to create Artwork the tool crashes with no error messages just a little X box
1180573 ALLEGRO_EDITOR ARTWORK       If one layer has warning, all artwork films are "created with warning".
1180960 SIP_LAYOUT    PLACEMENT       swap function is not swapping logical paths in sip layout!
1182534 ALLEGRO_EDITOR SKILL          axlLayerPrioritySet() not working with v166 s013 and up
1182560 ALLEGRO_EDITOR PLOTTING       Creating plot 2nd time casues Allegro to crash
1182616 ALLEGRO_EDITOR PLACEMENT       Application crashes when attempting to place a high pin count BGA
1183752 CONCEPT_HDL CORE          Unable to modify location properties within a read-only hierarchical block
1183774 SIP_LAYOUT    DIE_EDITOR    Die Refresh hangs
1184178 CONCEPT_HDL CONSTRAINT_MGR Ecset xnet members lost from electrical class when restore from definition of  subblocks
1184787 ALLEGRO_EDITOR EDIT_ETCH       Allegro SPB166 s 015 crashes during normal add connect function.

DATE: 08-22-2013 HOTFIX VERSION: 015
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1156102 PCB_LIBRARIAN  CORE          PDV severe performance degradation on Linux platform makes PDV counter productive after some time
1165756 CONCEPT_HDL CORE          DE HDL 16.6 adding ASCII character to properties
1169896 ADW          LRM             Library Revision Manager makes updates but the interface never returns to the user
1170635 SIP_LAYOUT    WIZARDS       BGA PIN NAME doesn't sync with PIN Number
1171061 ALLEGRO_EDITOR PLACEMENT       Place Replicate Apply cannot place module
1171415 CONCEPT_HDL CORE          Mismatch in the interface ports in design bw_hybrid for block a38410_scsp
1171598 APD          WIREBOND       Cannot load xml over 65 profiles defined in file.
1171713 ADW          LRM             Blank lines appear in the LRM - RM-Clicking causes LRM to crash
1172576 SIP_LAYOUT    IMPORT_DATA    AIF import fails with Error: symbol is missing refdes
1172938 ALLEGRO_EDITOR PLOTTING       Export IPF probrem
1173190 ALLEGRO_EDITOR ARTWORK       Not able to Add/ Replace film_setup.txt file in Artwork control file.
1173750 ALLEGRO_EDITOR REPORTS       SIP tool crash when clicking report "Net Loop Report"
1175582 ALLEGRO_EDITOR SKILL          axlDBCreateFilmRec error undifined function

DATE: 08-9-2013 HOTFIX VERSION: 014
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1155569 APD          MODULES       P1_U1 and P1_U3 Die pins are missing after Place Module.
1158528 CONCEPT_HDL OTHER          Dual Monitor issue: Retain Hard Packaging option is missing and attribute test distorted
1160968 ALLEGRO_EDITOR SKILL          Text Subclass change difference in Edit > Change and axlChangeLayer Skill command
1161986 SIG_INTEGRITY  SIMULATION    Flatline waveform seen when via model is set to detailed closed form or analytical solution
1162323 SIP_LAYOUT    DIE_EDITOR    Die Editor is incorrectly leaving an unassigned function pin in the die during refresh from die abstract
1162752 ALLEGRO_EDITOR SKILL          axlDBChangeText doesnt recognize ?layer as a valid argument as documented
1165002 GRE          CORE          GRE Crashes during Plan Spatial giving "Memory Allocation Failure" Error.
1165469 CONCEPT_HDL CORE          Import Design loses design library name
1165708 ALLEGRO_EDITOR TESTPREP       Test point router failing when attempting to insert new TP via's
1165801 CONCEPT_HDL PDF             Pin texts of spun symbol overlap in publish PDF.
1166020 SIP_LAYOUT    WIREBOND       Bondpads created with shapes do not follow the orthogonal pattern when adding wirebonds.
1166371 ALLEGRO_EDITOR DATABASE       File locked for writing in 16.5 cannot be unlocked in 16.6
1166482 ALLEGRO_EDITOR INTERFACES    Step orientation for y-rotated component is not exported correctly.
1167519 ALLEGRO_EDITOR DATABASE       Uprev dbdoctor does not log warnings about renaming properties.
1167588 SIP_LAYOUT    DIE_ABSTRACT_IF  do not create a new pad stack for each I/O pad
1168496 ALLEGRO_EDITOR SCHEM_FTB       Export Physical Crashes when netreving the board
1169510 SIP_LAYOUT    WIZARDS       Netlist in Wizard is crashing with this text file where the Net Name for one of the assignments is blank, meaning dummy
1169593 CONCEPT_HDL PDF             Published PDF file's hyperlinks do not work fine when user click 1D10 or 2A10.
1169984 F2B          PACKAGERXL    Error Mapping cset when packaging but not in CM Audit
1171008 SIP_LAYOUT    OTHER          SiP Layout - Beta feature Void Adjacent Layer Shapes - changes or modifies "priority" of other/all shapes
1171411 ALLEGRO_EDITOR OTHER          Enh - Break in Step 3D view in latest hotfix v16.6s013

DATE: 07-26-2013 HOTFIX VERSION: 013
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
111368  CAPTURE       CORRUPT_DESIGN Capture - will not produce allegro netlist with 10.0
134439  PD-COMPILE    USERDATA       caCell terminals should be top-level terminals
186074  CIS          EXPLORER       refresh symbols from lib requires you to close CIS
583221  CAPTURE       SCHEMATIC_EDITOR Option to have the Schematic Page Name as a Property in the Titleblock
591140  CONCEPT_HDL OTHER          Scale overall output size in PublishPDF from command line
801901  CONCEPT_HDL CORE          Concept Menus use the same key "R" for the Wire and RF-PCB menus
813614  APD          DRC_CONSTRAINTS  With Fillets present the "cline to shape" spacing is wrong.
881796  ALLEGRO_EDITOR GRAPHICS       Enhancement request for Panning with Middle Mouse Button
887191  CONCEPT_HDL CORE          Cannot add/edit the locked property
911292  CONCEPT_HDL CORE          Property command on editing symbol attaches property to ORIGIN immediately
987766  APD          SHAPE          Void all command gets result as no voids being generated on specific env.
1001395 SIP_LAYOUT    ASSY_RULE_CHECK  Shape Minimum void check reports lots of DRCs which are not necessary to check out.
1030696 ALLEGRO_EDITOR INTERACTIV    Enh - Allow another behavior of PAN movement using middle mouse in Allegro
1043856 ADW          TDA             Diff between TDO and DE-HDL Hierarchy Viewer is confusing to the user
1046440 ADW          PCBCACHE       ADW: ImportSheet is not caching libraries under flatlib/model_sym when the source design is not an ADW project
1077552 F2B          PACKAGERXL    Diff Pairs get removed when packing with backannotation turned on
1079538 F2B          PACKAGERXL    Ability to block all 縮ingle noded nets� to the board while packaging.
1086362 ALLEGRO_EDITOR SHAPE          Enhancement request to autovoid a via if shape cannot cover the center of the via.
1087958 PSPICE       MODELEDITOR    Is there any limitation for pin name definition?
1087967 CIS          UPDATE_PART_STAT Update part status window shows incorrect differences
1090693 ADW          LRM             LRM auto_load_instances does not gray out Load instances Button
1097246 CONCEPT_HDL CORE          ConceptHDL - assign hotkeys to alpha-numerical keys
1099773 CONCEPT_HDL CORE          DE HDL goes into recursive loop if a custom text locked at site level is deleted from Tools > Option
1100945 SCM          SCHGEN          SCM generated DE-HDL has $PN placement issue
1100951 PSPICE       SIMULATOR       Increasing the resolution of fourier transform results in out file
1103117 RF_PCB       FE_IFF_IMPORT Enh- Allow the Allegro_Discrete_Library_to_ADS_Library_Translator to output in its original unit
1105473 PSPICE       PROBE          Getting error messages while running bias point analysis.
1106116 FLOWS       PROJMGR       view_pcb setting change was cleared by switching Flows in projmgr.
1106298 ALLEGRO_EDITOR INTERACTIV    Copy Shape uses last menu pick location as origin and not the Symbol Origin as specified in Options.
1106626 CONCEPT_HDL CORE          Concept HDL crashes when saving pages
1107086 ALLEGRO_EDITOR INTERACTIV    manual void with arc's goes in wrong direction during arc creation
1107172 CONCEPT_HDL OTHER          Project Manager Packager does not report errors on missing symbol
1108193 CONCEPT_HDL CORE          Using the left/right keys do not move the cursor within the text you're editing
1108603 PCB_LIBRARIAN  VERIFICATION    PDV Tools Verification > View Verification (CheckPlus) leaves <project>.cpm_tmp.cpm
1109024 CIS          OTHER          orcad performance issue from Asus.
1109109 CAPTURE       NETLIST_ALLEGRO  B1: Netlist missing pins when Pack_short property pins connected
1109466 ALLEGRO_EDITOR ARTWORK       Artwork create some strange gerber lines for fillet.
1109647 SIP_LAYOUT    DEGASSING       Shape degassing command enhancement - control over what layers are counted in even/odd layer sets.
1109926 CONCEPT_HDL CORE          viewing a design disables console window
1110194 SIP_LAYOUT    WIREBOND       If OpenGL settings for display of dynamic net names is enabled, should be visible while push/shove wirebonds.
1112357 SIP_LAYOUT    WIREBOND       wirebond command crashes the application
1112395 CONCEPT_HDL CORE          縗BASE\G� for global signal is not obeyed after upreving the design to 1650.
1112658 CAPTURE       PROPERTY_EDITOR  Changing Part 縂raphic� value from property Editor Changes Occ refdes values to instance
1112662 CAPTURE       PROJECT_MANAGER  Capture crashes after moving the library file and then doing Edit> Cut
1113177 PCB_LIBRARIAN  CORE          Pin Shapes are not getting imported properly
1113380 ALLEGRO_EDITOR INTERACTIV    Change layer to - option for package type .dra is not available in 16.6 release
1113656 SIP_LAYOUT    WIREBOND       Enable Change characteristic to work without unfixing its Tack point.
1113838 SIP_LAYOUT    DIE_ABSTRACT_IF  probe pins defined in XDA die abstract file are added with wrong location
1113991 CAPTURE       GENERAL       Save Project As is not working if destination is a linux machine
1114073 APD          DRC_CONSTRAINTS  Shape voiding differently if there are Fillets present in the design.
1114241 CAPTURE       SCHEMATIC_EDITOR Port not retaining assigned color, when moved on the schematic
1114442 PSPICE       PROBE          Getting Internal error - Overflow Convert with marching waveform on
1114630 CONCEPT_HDL ARCHIVER       Archcore fails because the project directory on Linux has a space in the name
1114689 CONCEPT_HDL CORE          Unknown project directive : text_editor
1114928 F2B          PACKAGERXL    縀rror (SPCODD - 5) while Export Physical even after change pin from A<0> to A
1116886 CONCEPT_HDL CORE          Crefer hyperlinks do not work fine when user use double digits partitions for page Border.
1118088 ALLEGRO_EDITOR EDIT_ETCH       Should Plan accurate and Optimize be removed in 16.6?
1118734 APD          EDIT_ETCH       Multiline routing with Clines on Null Net cannot route in downward direction
1118756 ALLEGRO_EDITOR SHAPE          Shape clearance parameter oversize values getting applied to Keepouts
1119606 CONCEPT_HDL MARKERS       Filtering two or more words in Filter dialog box
1119707 CONCEPT_HDL CORE          Genview does not use site colors when gen sch from block symbol
1119711 F2B          DESIGNSYNC    Design Differences show Net Differences wrongly
1120659 CAPTURE       PROJECT_MANAGER  "Save project as" does not support some of Nordic characters.
1120660 CONCEPT_HDL CORE          Save hierarchy saves pages for deleted blocks.
1120817 SIP_LAYOUT    SYMB_EDIT_APPMOD Rotate Pads commands not working while in the Symbol Edit App. mode
1120985 PSPICE       MODELEDITOR    Unable to import attached IBIS model
1121171 CONCEPT_HDL CREFER          PNN and correct property values not annotated on the Cref flat schematic
1121353 ALLEGRO_EDITOR INTERACTIV    Local env setting will change after saving and reopening.
1121382 ALLEGRO_EDITOR INTERACTIV    Undo command is limited to two for this design
1121540 F2B          PACKAGERXL    pxl.chg keeps deleting and adding changes on subsequent packager runs
1121558 ALLEGRO_EDITOR MODULES       Unrouted net and unrouted connection when module is placed of completely routed board file.
1121585 ALLEGRO_EDITOR OTHER          Drill Hole to Shape Same Net Spacing with Dynamic Shapes shows wrong result.
1121651 CAPTURE       SCHEMATIC_EDITOR "PCB editor select" menu option is missing
1122136 SIP_LAYOUT    PLACEMENT       Moving a component results in the components outline going to bottom side of the design.
1122340 CAPTURE       NETLIST_ALLEGRO  Cross probe of net within a bus makes Capture to hang.
1122489 CONCEPT_HDL OTHER          Save _Hierarchy causing baseline to brd files
1122781 CONCEPT_HDL CORE          cfg_package is generated for component cell automatically
1122909 CONCEPT_HDL CORE          changing version replicates data of first TOC on 2nd one
1123150 CONCEPT_HDL CORE          property on y axis in symbol view was moved by visibility change to None.
1123176 ALLEGRO_EDITOR UI_FORMS       Negative values for pop-up location is not retained with multiple monitors (more than 2)
1123815 ALLEGRO_EDITOR GRAPHICS       Embedded netname changes to a different netname
1124369 ALLEGRO_EDITOR INTERACTIV    Sliding a shape using iy coordinate does not work indepedent of grid.
1124544 CONCEPT_HDL CORE          About Search History of find with SPB16.5
1124570 APD          IMPORT_DATA    When importing Stream adding the option to change the point
1125201 CONCEPT_HDL CORE          Connectivity edits in NEW block not saved( lost) if block is created using block add
1125314 ALLEGRO_EDITOR INTERACTIV    Enved crash during setting of library paths in user preference
1125366 CONCEPT_HDL CORE          DE-HDL craches during Import Physical if CM is open on Linux
1125628 CONCEPT_HDL CORE          Crash on doing save hierarchy
1130555 APD          WIREBOND       Wirebond Import should connect to pins of the die specified on the UI.
1131030 PSPICE       ENVIRONMENT    Unregistered icon of Simulation setting in taskbar
1131083 ALLEGRO_EDITOR INTERACTIV    Bug: 16.6 crash in changing the mode in Find filter window
1131226 ALLEGRO_EDITOR PLACEMENT       When Angle is set in design parameters while placement component is rotated but outline is not.
1131567 CONCEPT_HDL OTHER          Lower case values for VHDL_MODE make genview use pin location to determen direction.
1131699 PSPICE       PROBE          Probe window crash on trying to view simulation message
1132457 CONCEPT_HDL CORE          The schematic never fully invokes and has connectivity errors.
1132575 CONCEPT_HDL CORE          2 pin_name were displayed and overlapped by spin command.
1132698 ALLEGRO_EDITOR EDIT_ETCH       Slide Via with Segment option with new Slide command
1132964 ALLEGRO_EDITOR SHAPE          Same net "B&B via to shape" errors created when adding shape
1133677 CONCEPT_HDL CORE          Cant delete nor reset LOCATION prop in context of top
1133791 CONCEPT_HDL CORE          Cant do text justification on a single selected NOTE in Windows mode.
1134761 CONCEPT_HDL CORE          Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property
1135118 ALLEGRO_EDITOR INTERACTIV    Mirror and other editing commands are missing for testpoint label text in general edit mode.
1136420 CAPTURE       GENERAL       Registration issue when CDSROOT has a space in its path
1136808 PSPICE       STABILITY       Pspice crash marker server has quite unexpectedly
1136840 CAPTURE       SCHEMATICS    Enh: Alignment of text placed on schematic page
1138586 ADW          MIGRATION       design migration does not create complete ptf file for hierarchical designs
1139376 CONCEPT_HDL CORE          setting wire color to default creates new wire with higher thickness
1140819 APD          GRAPHICS       Bbvia does not retain temp highlight color on all layers when selected.
1141300 CONCEPT_HDL CORE          DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped
1141723 ADW          PURGE          purge command crashes with an MFC application failure message
1143448 CAPTURE       GENERAL       About copy & paste to Powerpoint from CIS
1143670 SIP_LAYOUT    OTHER          Cross Probing between SiP and DEHDL not working in 16.6 release
1143902 ALLEGRO_EDITOR DATABASE       when the shape is rotated 45 degrees the void is moved.
1144990 PCB_LIBRARIAN  CORE          PDV expand & collapse vector pins resizes symbol outline to maximum height
1145112 CONCEPT_HDL CORE          Warning message: Connectivity MIGHT have changed
1145253 CONCEPT_HDL CORE          Component Browser adds properties in upper case
1146386 ALLEGRO_EDITOR INTERACTIV    Place Replicate Create add Static shape with Fillet shape
1146728 F2B          PACKAGERXL    DCF with upper and lower case values on parts causes pxl to fail
1146783 ALLEGRO_EDITOR INTERFACES    Highlighted component is missing from exported IPF file.
1147326 CONCEPT_HDL CORE          HDL crashes when trying to reimport a block
1148337 CAPTURE       ANNOTATE       Checking "refdes control" is not giving the proper annotation result
1148633 SIP_LAYOUT    INTERACTIVE    Add "%" to the optical shrink option in the co-design die and compose symbol placement forms
1149778 CAPTURE       SCHEMATICS    Rotation of pspice marker before placement is not appropriate
1149987 PCB_LIBRARIAN  PTF_EDITOR    Save As pushing the part name suffix into vendor_part_number value
1151748 ALLEGRO_EDITOR OTHER          If the pad and cline are the same width don't report a missing Dynamic  Fillet.
1152206 CONCEPT_HDL CORE          ROOM Property value changes when saving another Page
1152755 CONCEPT_HDL COPY_PROJECT    Copy project hangs if library or design name has an underscore
1152769 PSPICE       ENCRYPTION    Unable to simulate Encrypted Models in 16.6
1153308 ALLEGRO_EDITOR DRC_CONSTR    Creating Artwork Getting Warning "DRC is out of Date" even when DRC is up to date
1153893 F2B          DESIGNVARI    16.6 Variant Editor not supporting - in name
1154185 SIG_INTEGRITY  SIGNOISE       Signoise didn't do the Rise edge time adjustment.
1154860 ALLEGRO_EDITOR MANUFACT       Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
1155167 ALLEGRO_EDITOR EDIT_ETCH       Via structure placed in Create Fanout has incorrect rotation.
1155728 CONCEPT_HDL CORE          Unable to uprev packaged 16.3 design in 16.5 due to memory
1155855 SCM          SCHGEN          A newly user-defined net property is not transferred from SCM to DEHDL in Preserved Mode
1156274 ALLEGRO_EDITOR INTERFACES    Exported Step file from Allegro is wrong
1156316 CONSTRAINT_MGR OTHER          Break in functionality while creation of pin-pairs under Xnet in Constraint Manager
1156351 CONCEPT_HDL CONSTRAINT_MGR Loose members in Physical Net Class between DEHDL and Allegro
1156547 ALLEGRO_EDITOR DRC_CONSTR    Etch Turn under SMD pin rule check through pin Etch makes confused.
1156779 CONSTRAINT_MGR OTHER          Electrical Cset References in CM not working correctly
1157167 ALLEGRO_EDITOR SKILL          axlPolyFromDB with ?line2poly is broken
1158042 ALLEGRO_EDITOR DFA             DFA_DLG writes the dra file name in uppercase.
1158718 CONCEPT_HDL CHECKPLUS       Customer could not get $PN property values on logical rule of CheckPlus16.6.
1158970 ALLEGRO_EDITOR SCHEM_FTB       Changing LOCATION to $LOCATION in DEHDL does not update the .brd file
1158989 ALLEGRO_EDITOR INTERFACES    pdf_out -l creates a PDF
1159285 APD          DXF_IF          DXF_OUT fails; some figures are not exported
1159432 ALLEGRO_EDITOR SHOW_ELEM       http:// in the Show Element in 166 do not have HTML link to open the Website
1159483 PCB_LIBRARIAN  SETUP          part developer crashing with
1159516 ALLEGRO_EDITOR EDIT_ETCH       Unable to slide cline segment with new slide.
1159959 ALLEGRO_EDITOR GRAPHICS       3D viewer displays clines arcs incorrectly
1160004 SCM          UI             The RMB->Paste does not insert signal names.
1160410 ALLEGRO_EDITOR DATABASE       Lock databse with View Lock option is misleading
1160529 SCM          SCHGEN          Schematic generation stopped because the tool was unable to create an appropriate internal symbol structure
1160537 SPIF          OTHER          Cannot start PCB Router
1161363 ALLEGRO_EDITOR SYMBOL          Getting error SPMHGE-73 when trying to mirror symbol
1161781 CONSTRAINT_MGR CONCEPT_HDL    SigXp crash when selecting ECset in design
1161896 ALLEGRO_EDITOR DRAFTING       Tolerance value added for Dimensions is not working correctly (HF11-12)
1162193 SIP_LAYOUT    DIE_ABSTRACT_IF  shapes in dia file not linked to the die after edit co-design die
1162754 APD          VIA_STRUCTURE Replace Via Structure command selecting dummy nets.

DATE: 06-28-2013 HOTFIX VERSION: 012
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
914562  ALLEGRO_EDITOR GRAPHICS       3D viewer, PCB Symbol view in DRA needs to be same as in BRD
1120397 CONCEPT_HDL CREFER          CreferHDL attempts to create missing vlog004u.sir files
1136449 ALLEGRO_EDITOR GRAPHICS       about previous shape fill display
1145635 ALLEGRO_EDITOR SHAPE          Auto Voding on the same net shapes with other parameter.
1150334 ALLEGRO_EDITOR EDIT_ETCH       AiDT deletes the clines and turns it back to PLAN line
1151100 APD          VIA_STRUCTURE Net filter not working in replace via structure command.
1151126 APD          VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.
1151458 GRE          CORE          GRE crashes on Plan Spatial
1151932 F2B          PACKAGERXL    PXL error when case is wrong at differen levels in hierarchy
1152151 ALLEGRO_EDITOR INTERFACES    dxf2a gives error [SPMHGE-268]
1152475 PSPICE       SIMULATOR       RPC server unavailable error while simulating the attached design
1152737 ALLEGRO_EDITOR SKILL          dbids are removed because highlighted objects in setting the xprobe trigger
1153006 ALLEGRO_EDITOR SKILL          axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.
1153279 CONSTRAINT_MGR OTHER          Netrev changing design accuracy from 3 to 2 dec places
1153461 SIP_LAYOUT    DIE_EDITOR    Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail
1154973 APD          EDIT_ETCH       Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.
1155227 ALLEGRO_EDITOR DRC_CONSTR    via to shape check on the negative layer

DATE: 06-14-2013 HOTFIX VERSION: 011
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
982306  CONCEPT_HDL OTHER          When plotting a PDF publisher output the page coming out half inch bigger in pdf
1055338 SIP_LAYOUT    DRC_CONSTRAINTS  Soldermask to Via drcs on bondfingers
1093375 ALLEGRO_EDITOR PLACEMENT       Align Module with Zero spacing value space the modules further away the modules should be nearer
1103201 RF_PCB       FE_IFF_IMPORT Wrong permissions to map file during IFF import
1106900 CONCEPT_HDL COMP_BROWSER    Component Browser performance utility should honor CPM directives for include and exclude PPT
1110178 ALLEGRO_EDITOR EDIT_ETCH       Line Width Retention should be controlled via setting
1110323 APD          DXF_IF          DXF out is offsetting square discrete pads.
1123581 ALLEGRO_EDITOR MANUFACT       Dimension Line gets changed on board
1134083 CONCEPT_HDL OTHER          Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.
1139338 ALLEGRO_EDITOR DRC_CONSTR    The total etch length does not seem to work for Xnets after setting the variable "retain_electrical_constraints_on_nets"
1139361 ALLEGRO_EDITOR DRAFTING       Angular dimension tolerance is incorrect when plus minus tolerances are equal.
1141882 ALLEGRO_EDITOR EDIT_ETCH       Allegro Crashes during diffpair slide
1142876 ALLEGRO_EDITOR SHAPE          No DRC error when airgap between place bounds exactly zero
1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP
1145243 ALLEGRO_EDITOR NC             Duplicate drills found in the NC Drill output
1145260 SIP_LAYOUT    DIE_EDITOR    Enable "Copy" in die editor
1145284 CONCEPT_HDL CORE          Publish PDF crashes DE HDL
1145333 ALLEGRO_EDITOR SHAPE          SHAPE boundary may not cross itself. Error cannot be fixed.
1145856 ALLEGRO_EDITOR DRC_CONSTR    DRC Line to Thru Pin appear while Fillet be added
1146287 PCB_LIBRARIAN  CORE          PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps
1146865 ALLEGRO_EDITOR DATABASE       Allegro crashes when trying to place mechanical symbol
1148513 ALLEGRO_EDITOR OTHER          Importing a subdrawing file causes incorrect net name assignment.
1148734 CONCEPT_HDL OTHER          Logical Symbol Text is turned upside down after extracting PDF by  Publish PDF
1149025 ALLEGRO_EDITOR INTERFACES    IPC-2581 imports cross-hatched shapes as solid
1149948 APD          OTHER          Stream_out hangs on this design -- hang processing merge of overlapping shapes using poly_deletecolinear_only()
1150274 CONCEPT_HDL CORE          Uprev from 16.3 to 16.6 is not preserving RefDes
1151450 SIP_LAYOUT    DXF_IF          DXF export from CDNSIP missing symbols

DATE: 05-25-2013 HOTFIX VERSION: 010
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1084716 ALLEGRO_EDITOR OTHER          Getting an MPS error when updating CM from SigXplorer
1111430 FSP          CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border
1119007 CONCEPT_HDL CORE          PDF Publish of schematic creates extremely large PDF files
1121020 FSP          MODEL_EDITOR    Cut-Paste from Excel causes empty cell in Rule Editor
1124610 PSPICE       SIMULATOR       Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.6
1125330 FSP          CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border
1131775 ADW          LRM             LRM error with local libs & TDA
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
1132080 ALLEGRO_EDITOR PLOTTING       Size of the logo changes after File > Import > Logo
1134956 SPECCTRA    HIGHSPEED       Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
1135548 SIP_LAYOUT    SHAPE          This design shows two areas with shape shorting errors that should not occur
1138312 ALLEGRO_EDITOR MANUFACT       NCROUTE is not generated for filled rectangle slot ?
1139433 ALLEGRO_EDITOR GRAPHICS       embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.
1139509 CONCEPT_HDL CORE          The LRM update changes npn device to resistor
1140752 ALLEGRO_EDITOR PLACEMENT       Moving a place replicate module crashes allegro
1141314 SIP_LAYOUT    SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.
1141751 ALLEGRO_EDITOR INTERFACES    Allegro Crashes with Export IPC2581.
1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash
1142884 ALLEGRO_EDITOR OTHER          Boolean type user defined property doesn't export to the PDF
1143199 SIP_LAYOUT    DIE_EDITOR    Enable bump remastering
1143654 SIP_LAYOUT    DIE_EDITOR    Add X&Y offset when adding or moving a pin in die editor

DATE: 05-9-2013 HOTFIX VERSION: 009
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
961420  ALLEGRO_EDITOR PLACEMENT       Regardless of the aspect ratio for room of side The QuickPlace by room command could be placed comp
1079862 ALLEGRO_EDITOR SKILL          Ability to create IPC2581 layer mapping file by Allegro Skill function
1080734 CONCEPT_HDL CORE          Repainting of grid lines during pan or by moving window show as solid white lines instead of gray da
1104145 ALLEGRO_EDITOR SCHEM_FTB       User defined properties do not appear in PCB
1107547 SCM          OTHER          v15.5.1 tcl/tk code not recognised in 16.6
1110209 CONCEPT_HDL OTHER          We can move symbols and wires off grid despite the site.cpm grid lock
1117825 CONCEPT_HDL OTHER          SHOW_CONSOLE_ON_LAUNCH throws an unrecognized directive warning in the schematic editor
1118874 ALLEGRO_EDITOR INTERFACES    Oblong pad shapes are not shown with correct orientation after DXF export from Allegro
1121873 ALLEGRO_EDITOR INTERFACE_DESIGN Importing Bundles from Net Groups does not allow any further editing.
1122933 CONCEPT_HDL CORE          Newly added Toolbars are getting invisible after re-staring Concepthdl
1124587 ALLEGRO_EDITOR INTERACTIV    The Shape Expansion/Contraction command should also be available in EE mode.
1125895 SIP_LAYOUT    LEFDEF_IF       Tool crash while moving the slider in the Filter options Macro tab form of the co-design die library manager
1125962 F2B          DESIGNVARI    Custom Text in Variant Details dialog box is inconsistent
1126096 SCM          REPORTS       Two nets missing in report
1126134 SIG_INTEGRITY  GEOMETRY_EXTRACT Attempting to extract topology hangs APD
1126182 ALLEGRO_EDITOR DRC_CONSTR    Shape fillet DRC in same net thru via to thru via was removed after update DRC.
1130280 ALLEGRO_EDITOR MANUFACT       stream_out command in 16.6 seems hard coded to look for a design called stream_out.brd
1130737 F2B          PACKAGERXL    Error - pxl.exe has stopped working
1131650 ALLEGRO_EDITOR PLOTTING       PDF Publisher doesnot display few component defination properties in Property parameters
1131764 ALLEGRO_EDITOR EDIT_ETCH       Line segment will not slide using the New Slide.
1132638 ALLEGRO_EDITOR DFA             'dfa_update' crashes when running the utility on the attached foder.
1133311 ALLEGRO_EDITOR SKILL          ?origin switch is not working correctly with axlTransformObject while rotating shapes
1133893 SIP_LAYOUT    IMPORT_DATA    netlist-In Wizard crashes

DATE: 04-26-2013 HOTFIX VERSION: 008
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
876711  ALLEGRO_EDITOR GRAPHICS       Mouse wheel will only zoom out using Win7 64 bit
1080386 CONCEPT_HDL CORE          Unable to highlight netclass on every schematic page using Global Navigation
1082587 FSP          FPGA_SUPPORT    Support of Xilinx's Zync device
1105286 FSP          DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.
1105461 ALLEGRO_EDITOR DRAFTING       Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section
1105504 PCB_LIBRARIAN  CORE          PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running
1110126 ALLEGRO_EDITOR GRAPHICS       Display Hole displays strange color.
1113518 CIS          DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence
1117580 SCM          OTHER          DSMAIN-335: Dia file(s) error has occurred.
1117845 FSP          DE-HDL_SCHEMATIC Schematic Generation fails without a reason
1119864 FSP          TERMINATIONS    Auto-increment the pin number while mapping terminations.
1120250 ALLEGRO_EDITOR MANUFACT       Why is the parameter File altered?
1120414 ADW          LRM             TDO Cache design issue
1121044 SIP_LAYOUT    SKILL          axlDBAssignNet returns t even when no net name is assigned to via
1121148 ALLEGRO_EDITOR PLACEMENT       Ratsnests turns off when moving symbols with Net Groups
1122440 ALLEGRO_EDITOR DATABASE       Cannot unlock database using the password used to lock it
1122449 ALLEGRO_EDITOR DRC_CONSTR    Uncoupled length DRC for diff pair shows different actual length value between show element and CM.
1122990 ALLEGRO_EDITOR INTERACTIV    RF PCB Symbol which is part of Reuse Module cannot be replaced
1123083 ALLEGRO_EDITOR PLACEMENT       Saving after mirroring a Place replicate mdd create a .SAV board file.
1123257 SIG_INTEGRITY  SIMULATION    some of the data signals at the receiver are not simulatable
1123764 CONSTRAINT_MGR OTHER          Allegro crash while importing DCF file
1123816 CAPTURE       PART_EDITOR    Movement of pin in part editor
1124183 ALLEGRO_EDITOR EXTRACT       Output from EXTRACTA gets corrupted with refdes 50

DATE: 04-13-2013 HOTFIX VERSION: 007
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1107397 SIP_LAYOUT    PLACEMENT       Place Manual-H rotates die
1111184 ALLEGRO_EDITOR PLACEMENT       NO_SWAP_PIN property does not work in 16.6
1112295 APD          DXF_IF          Padstacks� offset Y cannot be caught by DXF.
1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components
1113317 CONCEPT_HDL SKILL          skill code to traverse design not working properly
1115491 ALLEGRO_EDITOR SKILL          telskill freezes command window
1115625 ALLEGRO_EDITOR SKILL          Design extents corrupted when axlTrigger is used.
1115708 ALLEGRO_EDITOR INTERFACES    Export DXF is outputting corrupt data on one layer.
1115850 ALLEGRO_EDITOR GRAPHICS       Text edit makes infinite cursor disappear
1116530 ALLEGRO_EDITOR MANUFACT       Import artwork show missing padstacks
1117498 ALLEGRO_EDITOR DATABASE       Why does dbstat flag LOCKED?
1118407 SIP_LAYOUT    DIE_EDITOR    net connectivity is getting lost when running die abstract refresh
1118413 SIP_LAYOUT    DIE_EDITOR    pin number is getting changed when running die abstract refresh
1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors
1118830 ALLEGRO_EDITOR SHAPE          Performance issue when moving/refreshing shapes in 16.6
1119784 ALLEGRO_EDITOR INTERACTIV    ipickx command gives drawing extent error inconsistently
1120469 SIP_LAYOUT    DIE_ABSTRACT_IF  use different padstack for different, but look-alike bumps
1120669 CONCEPT_HDL CORE          DEHDL crash on multiple replace of hier blocks
1120810 ALLEGRO_EDITOR EDIT_ETCH       Cannot slide cline segment.

DATE: 03-29-2013 HOTFIX VERSION: 006
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
625821  CONCEPT_HDL CORE          publishpdf  from command line doen not work  if temp directory does not exist.
642837  PSPICE       SIMULATOR       Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep
650578  ALLEGRO_EDITOR SHAPE          Allegro should do void only selected Shape without "Update Shape".
653835  ALLEGRO_EDITOR MANUFACT       Double character drill code overlaps with "cross" in NC drill legend
687170  SIP_LAYOUT    DRC_CONSTRAINTS  Shape to Route Keepout spacing DRC display incorrect
787041  FSP          DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics
825813  CONCEPT_HDL CORE          HDL crashes when copying a property from one H block to other
834211  ALLEGRO_EDITOR SHAPE          Constant tweaking of shape oversize values is time consuming
835944  ALLEGRO_EDITOR OTHER          Customer want to change for Jumper symbol by other Alt symbol.
868981  SCM          SETUP          SCM responds slow when trying to browse signal integrity
871899  CONCEPT_HDL CORE          'Multiple:' column of Grid window in DE-HDL option is too wide
873917  CONCEPT_HDL CORE          Markers dialog is not refreshed
887887  CONCEPT_HDL CORE          Option to find unconnected Pins/Nets with DEHDL L License
888290  APD          DIE_GENERATOR Die Generation Improvement
892857  CONCEPT_HDL CORE          packager treats R? as a unique reference designator
902908  PSPICE       SIMULATOR       Support of CSHUNT Option in Pspice
908254  ALLEGRO_EDITOR INTERACTIV    Enhancement request for DRC marker to have a link to CM
922422  CAPTURE       NETLIST_ALLEGRO  Netlist errors when using mix of convert and normal symbols
923361  ALLEGRO_EDITOR INTERACTIV    Stop writting PATH variables in env file if no modifications are done using User Preferences
935155  CAPTURE       DRC             No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC
945393  FSP          OTHER          group contigous pin support enhancement
969342  ALLEGRO_EDITOR DATABASE       Enhanced password security for Allegro database
1005078 CAPTURE       ANNOTATE       Copy paste operation does not fill the missing refdes
1005812 F2B          BOM             bomhdl fails on bigger SCM Projects
1010988 CAPTURE       OPTIONS       ENH: ADD ISO 8601 Date Time format to Capture
1011325 ALLEGRO_EDITOR PLACEMENT       Placement replication creates modules with duplicate names
1016640 ALLEGRO_EDITOR PLACEMENT       Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net
1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical
1032387 FSP          OTHER          Pointer to set Mapping file for project based library.
1032609 FSP          IMPORT_CONSTRAIN Import qsf into FSP fails with 縋LL PLL_3 does not exist in device instance�
1040678 ALLEGRO_EDITOR MANUFACT       Text spacing is inconsistant for top and bottom SM layer in xsection chart
1042025 APD          WIREBOND       Order placement of  power rings for power/ground rings generation with using Perform Auto Bonding
1045500 CONCEPT_HDL CORE          Why Search results does not display the correct Physical Pages.
1047259 CIS          EXPLORER       Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type
1047756 CAPTURE       NETLISTS       Not adding user defined properties in netlist generated by orDump.dll
1052455 RF_PCB       DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation
1054314 CONCEPT_HDL CORE          Zoom of custom text is different from other schematic objects
1061529 CONCEPT_HDL CORE          Space can be included in LOCATION value and cannot be checked by checkplus
1064035 CONCEPT_HDL COMP_BROWSER    Component Browser crashes on part number search using a library containing >23K parts
1064604 ALLEGRO_EDITOR MANUFACT       Enh - Include ability to add slot notes to designs
1065636 CONCEPT_HDL OTHER          Text not visible in published pdf
1065843 CIS          PART_MANAGER    time stamp on library from different time zones triggers part manager lib out of date warnings
1066701 ALLEGRO_EDITOR OTHER          Missing padstack warnings not in Symbol refresh log summary
1067283 SCM          PACKAGER       ALLOW_CONN_SWAP does not work for lower level schematic parts
1067400 CONCEPT_HDL CORE          ERROR(SPCOCD-171): Port exists in symbol but not in the schematic
1068878 CONCEPT_HDL CORE          Rotating symbol causes the pin name to be upside down
1069896 ALLEGRO_EDITOR EDIT_ETCH       Cline changes to arc when routing even when Line lock is set to Line 45
1070465 CONCEPT_HDL CORE          Why does ConceptHDL crash on renaming a Port Signal
1071037 PSPICE       SIMULATOR       Provide option to disable Index Files Time Stamp Check
1072311 CONCEPT_HDL OTHER          Schematics are incorrect after importing design.
1072691 CONCEPT_HDL CORE          Customer has the crash from Run Script of DE-HDL 16.51 again(#3)
1072859 SIP_LAYOUT    DIE_EDITOR    padstack selection window crash from Die Editing: Component editing of Co-Design Die
1073354 CONCEPT_HDL CORE          Bubble defined on symbol pin is not visible on the schematic
1073837 ALLEGRO_EDITOR GRAPHICS       Some objects disappear on ZoomIn ZoomOut
1074243 ALLEGRO_EDITOR GRAPHICS       Allegro WorldView window does not always refresh after dehighlight of objects
1074606 ALLEGRO_EDITOR INTERACTIV    Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format
1074794 ALLEGRO_EDITOR REPORTS       add commonly reguested via reports to Allegro and ICP reports.  Via per net, via per layer per net
1075587 CONCEPT_HDL PAGE_MGMT       Unable to insert page in schematic
1076117 PSPICE       PROBE          Copy & Paste text/label in probe window changes font size and later gets invisible
1076145 SIP_LAYOUT    DIE_ABSTRACT_IF  Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.
1076566 ALLEGRO_EDITOR EDIT_ETCH       Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.
1076604 ALLEGRO_EDITOR SHAPE          Sliding via in pad corrupts surrounding shape and generates false DRC Errors
1076820 SPECCTRA    FANOUT          Fanout fails to stack vias in bga pads.
1076868 ALLEGRO_EDITOR PARTITION       Symbols become 'read only' inside a design partition
1076879 GRE          IFP_INTERACTIVE  Plan Column should not be present in Visibility tab for Symbol Editor
1076898 CONCEPT_HDL CORE          User can not increase logic grid size value continuously using Up button on Design Entry HDL Options
1077026 CIS          LINK_DATABASE_PA fonts changes while linking db part in 16.5
1077187 ALLEGRO_EDITOR DATABASE       DBDoctor appears to fix database but nothing is listed in the log file.
1077527 CONCEPT_HDL CORE          ConceptHDL net with name U cannot be found using Global navigate
1077621 CONCEPT_HDL CORE          DEHDL crashes when saving page 3
1078270 SCM          UI             Physical net is not unique or not valid
1079616 CONSTRAINT_MGR CONCEPT_HDL    Packager error in 16.5 which is resolved when system is re-booted
1079821 CONCEPT_HDL CORE          Project Setup does not respect $TEMP variable for temp_dir and creates a  directory in project calle
1080142 CIS          CONFIGURATION peated entries in Allowed Part Ref Prefs
1080207 ALLEGRO_EDITOR INTERACTIV    Separate the 2  types of SOV violations."Segments over voids & Segments with missing plane coverage"
1080261 PSPICE       SIMULATOR       Encryption support for lines longer than 125 characters
1080336 CONCEPT_HDL CORE          Backannotation error message ehnancement
1081001 ALLEGRO_EDITOR PLACEMENT       Package boundary is not visible while manually placing a component when using OrCAD license
1081237 ALLEGRO_EDITOR PLACEMENT       Place replicate > apply does not apply component pin properties stored in .mdd
1081284 MODEL_INTEGRIT TRANSLATION    Space in the file path will create a bogus error
1081346 ALLEGRO_EDITOR INTERACTIV    With Place manual, rotation of the symbol is not updated.
1081760 FSP          CONFIG_SETTINGS  Content of 縁PGA Input/Output Onchip termination� columns resets after update csv command
1082220 FLOWS       OTHER          Error SPCOCV-353
1082492 ALLEGRO_EDITOR PLACEMENT       Place replicate create does not highlight symbols.
1082676 ALLEGRO_EDITOR EDIT_ETCH       HUD meter doesnot display while sliding / add command
1082737 CAPTURE       GENERAL       The 緼rea select� icon shows wrong icon in Capture canvas.
1082739 CAPTURE       OTHER          The product choices dialogue box shows incorrect name
1082785 CONCEPT_HDL CORE          DE HDL should clean the design with non sync properties in some automated way
1083761 CONCEPT_HDL OTHER          AGND text missing from PDF Publisher
1083964 CONCEPT_HDL OTHER          Do not display Value and other attributes on variant parts which are DNI
1084023 PSPICE       MODELEDITOR    Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file
1084178 ALLEGRO_EDITOR SHAPE          Spike create on dynamic void.
1084637 ALLEGRO_EDITOR INTERACTIV    Enhancement: Pick dialog should automatically be set to enter coordinates
1085010 CONCEPT_HDL CREFER          Crefer crashes if the property value in the dcf file has more than 255 characters
1085347 CAPTURE       SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.
1085522 ALLEGRO_EDITOR INTERACTIV    Allegro add angle to Display->Measure results
1085791 CONCEPT_HDL CORE          Publish PDF can not output Constraint Manager properties into PDF file.
1085891 ALLEGRO_EDITOR INTERACTIV    about DRC update
1085990 CAPTURE       DRC             B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO
1086514 CONCEPT_HDL COMP_BROWSER    Component Browser placement restrictions not working
1086576 CONCEPT_HDL CHECKPLUS       CheckPlus hangs when running Graphic rules.
1086671 PSPICE       SIMULATOR       SPB16.6 pspice crashes with attached design
1086749 ALLEGRO_EDITOR MENTOR          mbs2brd: DEFAULT_NET_TYPE rule is not translated
1086886 CAPTURE       PROPERTY_EDITOR  "Is No Connect" check box in property editor doesn't work for power pins
1086902 CONCEPT_HDL INFRA          Problems occurred while loading design connectivity
1086937 PSPICE       ENVIRONMENT    PSpice Color map getting doubled leading to crash after colors are modified number of times.
1087221 CONCEPT_HDL OTHER          Part manager could not update any parts.
1087223 CAPTURE       CROSSREF       Cross Probing issue when login into system with user name containing white space
1087295 SIP_LAYOUT    EXPORT_DATA    Enable "Package Overlay File for IC" for concurrent co-design dies too
1087658 CAPTURE       PRINT/PLOT/OUTPU Lower level design pages are getting print twice
1088231 F2B          PACKAGERXL    Design fails to package in 16.5
1088252 CONCEPT_HDL CORE          Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.
1088606 ALLEGRO_EDITOR INTERACTIV    Pin Number field do not support Pin Range for Symbol Editor
1088983 CONSTRAINT_MGR CONCEPT_HDL    Units resolution changed in 16.6 Constraint Manager
1089017 ALLEGRO_EDITOR SHAPE          What is the cause of the shape not filling?
1089259 SCM          IMPORTS       Cannot import block into ASA design
1089356 SIP_LAYOUT    DIE_EDITOR    Distributed co-design : launching die editor taking more than an hour to bring up edit form
1089362 PSPICE       STABILITY       Pspice crash on pspice > view simulation result on attached project
1089368 SCM          OTHER          Can't do Save - cp: cannot stat ... No such file or directory
1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.
1090068 ALLEGRO_EDITOR SHAPE          shape priority issue in SPB165
1090125 ALLEGRO_EDITOR DATABASE       Q- The rename resequence log file is not giving correct message.
1090181 GRE          CORE          AiDT fails for the nets with errors SPGRE-21 & SPGRE-22
1090930 CONSTRAINT_MGR CONCEPT_HDL    DEHDL-CM does not retain customized worksheet.
1091335 CONCEPT_HDL OTHER          Color change cannot remain in some situation.
1091347 CAPTURE       TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled
1091359 CAPTURE       GENERAL       Toolbar Customization missing description
1091662 CONCEPT_HDL CORE          Incorrect behavior with the SHOW_PNN_SIGNAME directive
1091714 CAPTURE       PART_EDITOR    More than one icons gets selected in part editor at the same time
1092411 CONSTRAINT_MGR INTERACTIV    In v16.6 CM multiple net name selection under net column is not working as in v16.5
1092426 CONCEPT_HDL CORE          Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design
1092874 CONCEPT_HDL CORE          DEHDL wire short during move not detected with check enabled
1092882 ALLEGRO_EDITOR EDIT_ETCH       AICC should be removed from orcad PCB Designers design parameters
1092918 CAPTURE       GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error
1092933 CONCEPT_HDL OTHER          PDF Publisher saves the pdf generated in the previous project folder
1093327 CONCEPT_HDL OTHER          Getting error SPCODD � 369 Unable to load physical part in variant editor
1093391 CONSTRAINT_MGR OTHER          Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.
1093886 SPECCTRA    HIGHSPEED       Pin delay does not work in PCB Router when specified in time
1094223 CAPTURE       PROPERTY_EDITOR  CTRL+S does not work in Property Editor but RMB > Save.
1094513 CONCEPT_HDL CORE          How to display $PNN for which SIG_NAME is not visible?
1094611 CAPTURE       PROPERTY_EDITOR  E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic
1094618 CONCEPT_HDL INFRA          Unable to uprev the design in 16.5
1094867 CONCEPT_HDL CORE          Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet
1095449 SIP_LAYOUT    LOGIC          Allow netlist-in wizard to work on a co-design die
1095701 CONCEPT_HDL CORE          Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block
1095705 CONCEPT_HDL CREFER          Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3
1095861 F2B          BOM             Using Upper-case Input produces incorrect BOM results
1096318 ALLEGRO_EDITOR INTERFACES    IDF import not removing MCAD tagged objects during import
1097241 CONCEPT_HDL CORE          Concepthdl - zoom in to first object in Find result automatically
1097468 ALLEGRO_EDITOR INTERACTIV    Need ability to hilight and assign color to vias
1097675 CAPTURE       ANNOTATE       Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate
1099151 SIG_INTEGRITY  SIMULATION    All Neighbor crosstalk numbers reported when there are no aggressors
1099175 CONCEPT_HDL CORE          CPM directive that enables the Command Console Window in DE-HDL
1099838 CAPTURE       TCL_INTERFACE TCL library correction utility is not working correctly.
1099903 ALLEGRO_EDITOR PLACEMENT       Mirror and rotating component places component mirror side
1099941 ALLEGRO_EDITOR PLACEMENT       Problem in rotating bottom components when using Place Manual or place manual -h command
1099998 CONCEPT_HDL CHECKPLUS       CheckPlus marker file not locating signal when signal name includes the # character.
1100018 CONCEPT_HDL COPY_PROJECT    CopyProject gives errors about locked directives
1100449 ALLEGRO_EDITOR ARTWORK       Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork
1100758 CAPTURE       LIBRARY       Import properties does not update pin numbers of multi section parts
1101009 CONCEPT_HDL CORE          Cursor stays as arrow after performing File > Save Hierarchy
1101497 ALLEGRO_EDITOR UI_FORMS       Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.
1101813 SIP_LAYOUT    DIE_ABSTRACT_IF  Support die abstract properties
1102531 ALLEGRO_EDITOR GRAPHICS       Allegro graphics distortion infinite cursor 16.6
1102623 ALLEGRO_EDITOR SHAPE          Strange void around the pad
1103246 FSP          FPGA_SUPPORT    New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3
1103631 MODEL_INTEGRIT OTHER          Model Integrity license when using orcad
1103703 F2B          DESIGNSYNC    Toolcrash with Design Differences
1103712 CONCEPT_HDL COPY_PROJECT    Copy Project crashes on customer design attempting to update symbol view
1104068 CAPTURE       DRC             "Check single node connection" DRC gets reset in 16.6
1104121 PSPICE       AA_OPT          縋arameter Selection� window not showing all the components : on WinXP
1104575 CONCEPT_HDL CORE          Allign does not allign offgrid symbols correctly
1104727 CONSTRAINT_MGR SCM             Net Group created in sip does not transfer to SCM
1105128 CONSTRAINT_MGR DATABASE       Import dcf does not clear out user defined schedule.
1105195 SIP_LAYOUT    WIREBOND       Request that Tack points default to a "fixed" position after Generate Bond Wires.
1105249 ALLEGRO_EDITOR OTHER          PDF out--- component user defined prop doesn't list the prop selection form
1105443 PSPICE       AA_OPT          Parameter selection window in optimizer  does not list param part
1105818 ALLEGRO_EDITOR INTERACTIV    Menu-items seperators are clickable and menu goes away when clicked
1105822 ALLEGRO_EDITOR SCHEM_FTB       Netrev failing with compact pin syntax
1105993 SIP_LAYOUT    LOGIC          Import netlist no longer works with co-design die in SiP 16.6
1106332 SIP_LAYOUT    OTHER          sprintf for axlSpreadsheetDefineCell writes characters in upper case only
1106786 CAPTURE       SCHEMATICS    Bug: Pointer snap to grid
1107132 FSP          OTHER          Altera ArriaV (5AGXMA5GF31C4) support.
1107151 ALLEGRO_EDITOR ARTWORK       Shape filling removed when changing artwork format to RS274X in Global Dynamic Param
1107237 SIP_LAYOUT    WIZARDS       Updating a Die using the Die Text In Wizard will error out and not finish
1107371 ADW          COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).
1107599 CAPTURE       STABILITY       Capture 16.6 crash when trying to invoke
1108118 ALLEGRO_EDITOR OTHER          PDF Publisher pad rotation messed up with flashed pad.
1108574 ADW          COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode
1109095 SIP_LAYOUT    WIREBOND       Bondfinger move in hug mode create drcs
1109113 ALLEGRO_EDITOR DATABASE       Allegro Netrev crash with SPB 16.6
1109622 SIP_LAYOUT    DATABASE       In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.
1110077 ALLEGRO_EDITOR DRC_CONSTR    Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
1110256 ALLEGRO_EDITOR SHAPE          Auto void on dynamic shape is not correct in 16.6
1110264 RF_PCB       FE_IFF_IMPORT IFF Import in DEHDL has component offset
1111226 ALLEGRO_EDITOR DATABASE       Name too long error with Uprev command when output file name exceeds 31 characters
1111234 ALLEGRO_EDITOR MANUFACT       Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
1112431 SIP_LAYOUT    COLOR          Frequent crash while working with latest version of CDNSIP
1112493 ALLEGRO_EDITOR DATABASE       Customer does not like 16.6 Ratsnest points Closest Endpoint
1112774 GRE          CORE          Allegro GRE not able to commit plan after topological plan
1113908 ALLEGRO_EDITOR COLOR          Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.
1114815 ALLEGRO_EDITOR OTHER          Q1: Switchversion error when reading -fa file
1114994 ALLEGRO_EDITOR DATABASE       Getting an error after upreving components to 16.6

DATE: 03-7-2013 HOTFIX VERSION: 005
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1067770 IXCOM-COMPILE  COVERAGE       Assertion failed: file ../covToggleCoverageXform.cpp, line 1102
1100442 ALLEGRO_EDITOR PLACEMENT       Placement queue shows components whichs are already placed
1101555 ALLEGRO_EDITOR DATABASE       Allegro Crash frequently
1104011 ALLEGRO_EDITOR DATABASE       Place replicate move group of a modules leaves traces behind
1104065 SCM          NETLISTER       SCM 16.6 has problem generating Verilog with existing sym_1 view
1104605 F2B          PACKAGERXL    Pins of function swapped part in block not displayed
1104790 SCM          IMPORTS       Corrupt data once SiP file is imported into SCM
1105066 APD          IMPORT_DATA    Import NA2 worked in 16.5 "035" but fails in 037 and 16.6
1106323 ALLEGRO_EDITOR PLACEMENT       Unable to locate specific placed symbol on this board as it becomes invisible after placement.
1108032 CONCEPT_HDL CORE          'Find' option does not list all Components in the Design
1109080 ALLEGRO_EDITOR OTHER          Window DRC is not working in OrCAD PCB Editor Professional

DATE: 02-22-2013 HOTFIX VERSION: 004
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1081026 ALLEGRO_EDITOR GRAPHICS       3D Viewer do not show the height for the embedded component correctly
1095225 ALLEGRO_EDITOR EDIT_ETCH       The Constraint option does not work from right mouse click>Options>Line Width > constraint during interactive routing
1096356 ALLEGRO_EDITOR DATABASE       Cannot Analyze a Matched Group in CM
1097481 ALLEGRO_EDITOR INTERACTIV    Allow replace padstack command in design partition
1098252 ALLEGRO_EDITOR MANUFACT       Double digit drill character overlaps with figure "circle" in NC drill legend
1099958 ALLEGRO_EDITOR PAD_EDITOR    Library Drill Report producing an empty report
1100401 ALLEGRO_EDITOR OTHER          Invalid switch message for "m" for a2dxf command
1101026 ALLEGRO_EDITOR OTHER          utl_perftune hanging in fpoly_RemoveVerySmallSegments(), causing shape degassing never to exit.
1101064 SIP_LAYOUT    SHAPE          'Shape force update creates a rat
1102798 SIP_LAYOUT    OTHER          Stream out puts offset pad in wrong position if pad is mirrored but not rotated.

DATE: 02-8-2013 HOTFIX VERSION: 003
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
1077728 APD          EXTRACT       Extracta.exe generate the incorrect result
1084711 APD          DXF_IF          Padstacks with offsets cause violations in Export > DXF
1090369 SIG_INTEGRITY  LICENSING       Impedance value not updating in OrCAD PCB Designer
1093050 ALLEGRO_EDITOR DRC_CONSTR    Taper trace on diff pairs not checking to min line spacing.
1093563 SPECCTRA    ROUTE          PCB Router crashes with reduce_padstack set to on
1093717 APD          DATABASE       Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent
1094788 SIP_LAYOUT    WIREBOND       Wirebond edit move command
1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor
1096234 ALLEGRO_EDITOR DFA             Via pad connected to shape didn縯 show up after 縎uppress unconnected pads� option.
1096313 RF_PCB       LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff
1096613 ALLEGRO_EDITOR INTERACTIV    Enh-While moving parts silk ref des should remain visible
1096676 CONCEPT_HDL CORE          SPB 16.5 HF36 breaks designs that workded fine in HF35
1096913 APD          IMPORT_DATA    Import > NA2 fails to bring in the Y1 component.
1097751 ALLEGRO_EDITOR DATABASE       Import CIS netlist crashes.
1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.

DATE: 1-25-2013 HOTFIX VERSION: 002
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
491042  CONCEPT_HDL SECTION       Prevent PackagerXL from changing visibility on SEC attribute
863928  ALLEGRO_EDITOR INTERACTIV    Segment over void higlights false "nets with arc"
1067272 PCB_LIBRARIAN  CORE          Unable to retain the symbol outline changes
1074820 ALLEGRO_EDITOR GRAPHICS       losing infinite cursor tracking after selecting the add text command with opengl enable
1075622 CONCEPT_HDL CORE          PDV Edit Symbol in DE-HDL all editing functions disabled since Hotfix 33
1076986 APD          WIREBOND       Wirebond Adjust Min DRC does not maintain the finger position in the same sequence
1078031 SIG_INTEGRITY  REPORTS       Requesting improvement to progress indicator for report generator
1080213 SIP_LAYOUT    WIREBOND       Wrong behavior of Redistribute Fingers Command
1080667 ALLEGRO_EDITOR GRAPHICS       Allegro lines with fonts not displayed correctly in 16.6
1080982 CONCEPT_HDL CORE          Crash of Allegro Design Entry during a copy of a note.
1081200 CONSTRAINT_MGR OTHER          In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete.
1081553 CONCEPT_HDL OTHER          Model Assignment can not translate M (Milli-ohm) property value of DE HDL.
1081696 ALLEGRO_EDITOR INTERACTIV    Compose shape not working when radius is set to 1.0
1082595 ALLEGRO_EDITOR COLOR          Infinite cursor remains white even we change background to white
1082704 ALLEGRO_EDITOR GRAPHICS       infinite cursor disappears when using Display>Measure
1082715 SIG_EXPLORER INTERACTIV    Single line impedance for BOTTOM Layer is not calculated in cross section upon changing the thickness of dielectic layer
1082774 ALLEGRO_EDITOR TECHFILE       Import techfile command terminates abnormally when importing a generic techfile.
1082820 CONSTRAINT_MGR UI_FORMS       The configure generic cross-section pull downs do not work.
1083133 SIP_LAYOUT    INTERACTIVE    SiP will crash when using the beta Pad Rename command to change a BGA pads name.
1083158 ALLEGRO_EDITOR GRAPHICS       The cursor chage to Arrow head for Shape Select is more sensitive to location in SPB 16.6
1083533 CONCEPT_HDL CONSTRAINT_MGR Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout
1083637 PCB_LIBRARIAN  CORE          Save As is not renaming the NAME in the symbol.css file
1083934 ALLEGRO_EDITOR PAD_EDITOR    Error(SPMHUT-41): File selected is not of type Drawing.
1084148 CONCEPT_HDL CHECKPLUS       The CheckPlus hasProperty predicate fails in the Physical environment.
1084166 SIP_LAYOUT    DIE_ABSTRACT_IF  Updating sip layout with new die abstract doesn't properly update IC_DESIGN_CELL* properties
1084285 CONCEPT_HDL INFRA          Corrupted dcf was never fixed and caused PXL error
1084441 CONCEPT_HDL CORE          Assigned net property value changes to numeric
1084542 ALLEGRO_EDITOR DRAFTING       Dimensions associated with frect doesn't rotate with the symbol.
1084736 APD          IMPORT_DATA    Import SPD2 file from UPD-L shape Pad and text issue
1085008 ALLEGRO_EDITOR INTERACTIV    Relative (from last pick) option in the Pick dialog not working for pick command
1085139 ALLEGRO_EDITOR GRAPHICS       Infinite Cursor disappear during Add Connect if Infinite_cursor_bug_nt is enabled
1085187 SIP_LAYOUT    INTERFACE_PLANNE netrev with overwrite constraints fatal error
1086402 ALLEGRO_EDITOR GRAPHICS       Infinite cursor dissapear when using command like add connect or Place manually with opengl enabled.
1086905 PSPICE       SIMULATOR       PSpice crash while simulating circuit file with BREAK function
1087770 ALLEGRO_EDITOR EDIT_ETCH       Allegro crashes on a pick with the slide command.
1088412 SCM          CONCEPT_IMPORT why reimport block adds _1 to the netnames?
1088958 CONSTRAINT_MGR INTERACTIV    annot create Differential Pairs out of nets that belongs to a Net Group
1089336 ALLEGRO_EDITOR GRAPHICS       infinite cursor and pcb_cursor_angle
1090689 ADW          LRM             LRM: Unable to select any Row regardless of Status
1090955 ALLEGRO_EDITOR OTHER          Cancel command crashes PCB Editor when add rectangle
1091047 ALLEGRO_EDITOR REPORTS       The "Dangling Lines Via and Antenna� report seems to be missing vias that are antennas.
1091218 ADW          LRM             LRM is not worked for the block design of included project
1091443 ALLEGRO_EDITOR OTHER          Crash when toggling suppress pads
1091706 ALLEGRO_EDITOR EDIT_ETCH       Allegro crash while routing after setting variable acon_no_impedance_width
1092916 CAPTURE       OTHER          Capture crash
1093573 ALLEGRO_EDITOR DATABASE       team design opening workflow manager crashes allegro.  possibly corrupt database

DATE: 12-18-2012 HOTFIX VERSION: 001
===================================================================================================================================
CCRID PRODUCT       PRODUCTLEVEL2 TITLE
===================================================================================================================================
501079  ALLEGRO_EDITOR MODULES       Enhancement for Module swap function similar to component swap
745682  CONCEPT_HDL CORE          Attributes window requires resizing each time DEHDL is launched
825846  CONCEPT_HDL CORE          The module_order.dat file gets corrupted
871886  CONCEPT_HDL CORE          Browse button in Signal Integrity window of DE-HDL option causes program crash
891439  ALLEGRO_EDITOR INTERACTIV    moving cline segments
898029  CAPTURE       PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore
923210  CONCEPT_HDL CORE          Search with multiple properties does not show all properties
938977  CONCEPT_HDL CORE          Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
947451  ALLEGRO_EDITOR INTERACTIV    Allow the tool to select multiple shapes when assigning a net to more than one shape.
968646  ALLEGRO_EDITOR EDIT_ETCH       The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
976723  ADW          MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor
981767  SCM          UI             Add series termination in ASA will crash if both output and input pins are selected.
982273  SCM          OTHER          Package radio button is grayed out
988438  CONCEPT_HDL CORE          Visible constraint disrupts MOVE command
989471  ALLEGRO_EDITOR INTERACTIV    Functionality to zoom to the selected object in Pre Select Mode
993562  CONCEPT_HDL INFRA          After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).
996577  SPECCTRA    ROUTE          Specctra not routing NET_SHORT connections
997992  CONCEPT_HDL CORE          Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
1001300 PSPICE       MODELEDITOR    BUG: Simserver crash with encryptedm model
1010124 PSPICE       SIMULATOR       Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs
1013656 SCM          OTHER          create diff-pair should honour diff-pair setup or ask user for positive negative leg
1013721 ALLEGRO_EDITOR EDIT_ETCH       Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
1016859 SCM          REPORTS       dsreportgen exits with %errorlevel%
1018506 ALLEGRO_EDITOR INTERACTIV    Edit copy with retain net of via will assign net to pin
1020746 CONCEPT_HDL OTHER          PDF Publisher tool behavior inconsistent between OSs
1020798 SIP_LAYOUT    SHAPE          Shape not voiding on layer 2 causing shorts
1023051 SCM          UI             Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
1023774 APD          WIREBOND       After "xml wire profile data" is imported it isn't reflected to actual wire.
1023807 SPECCTRA    GUI             Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button
1024239 ALLEGRO_EDITOR INTERFACES    DXF pin location is moved when I execute DXF out
1028237 CONCEPT_HDL HDLDIRECT       Error binding design when generating simulation netlist
1030591 CAPTURE       LIBRARY       Library Correction utiltiy locks the library and deosn't frees it even after being closed
1035624 CONCEPT_HDL CORE          Options pre-selected when launching base product
1035896 SIP_LAYOUT    ASSY_RULE_CHECK  Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly
1036580 ALLEGRO_EDITOR MODULES       Module created from completely routed board file has lot of missing connections in it.
1037345 ALLEGRO_EDITOR INTERACTIV    Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)
1038180 ALLEGRO_EDITOR DRC_CONSTR    BGA escapes not being calculated in phase tol
1038285 SCM          UI             Restore the option to launch DE-HDL after schgen.
1038371 ALLEGRO_EDITOR INTERFACES    Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."
1038577 ALLEGRO_EDITOR DATABASE       Modifying Void crashes Allegro
1039112 ALLEGRO_EDITOR ARTWORK       Antietch and Boundary layers deleted when Match Display selected
1039147 ALLEGRO_EDITOR COLOR          Need an option to change color of Text marker and Text select in Display listing
1040653 ALLEGRO_EDITOR DATABASE       Cannot update netlist data,  ERROR(SPMHDB-121): Attribute definition not found.
1041368 APD          DEGASSING       The Degas_No_Void properties assigned to Cline does not work.
1041864 ALLEGRO_EDITOR MANUFACT       Allegro crashes when opening the Backdrill setup menu
1042199 SIG_INTEGRITY  SIMULATION    Waveform list was not refreshed by switching tab.
1042348 SIP_LAYOUT    STREAM_IF       GDSII export includes the full refernce path, breaks CATS flow
1043861 SIG_INTEGRITY  REPORTS       Derating values are NA in bus simulation report when derating table is not in working directory
1043903 GRE          GLOBAL          This design crashes during planning phases in GRE.
1044029 PSPICE       ENCRYPTION    Encrypted lib not working for attached
1044222 ALLEGRO_EDITOR INTERACTIV    Capture Canvas Image changes working directory
1044264 PSPICE       SIMULATOR       Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.
1044577 GRE          CORE          Plan > Topological either crashes or hangs GRE
1044687 TDA          CORE          tda does not get launched if java is not installed
1044754 SIG_INTEGRITY  SIMULATION    Incorrect waveforms when simulating with stacked die
1045607 ALLEGRO_EDITOR OTHER          Component get placed even after Cancel IDF in form.
1045694 CONCEPT_HDL INFRA          Why to package the design twice to pass the net_short property to the board?
1045863 CONCEPT_HDL INFRA          Customer had the crash several times when they run script with SPB16.51.
1046929 CONSTRAINT_MGR OTHER          Unable to create physical of spacing cset after rename the default cset in design entry.
1047590 ALLEGRO_EDITOR SCHEM_FTB       Buses created in Allegro-CM are deleted by netrev in traditional flow
1047823 CONSTRAINT_MGR OTHER          acPutValue predicate text not being displayed at bottom of Constraint Manager window.
1048403 ALLEGRO_EDITOR SKILL          Allegro crashes opening more than 16 files with skill
1049262 ALLEGRO_EDITOR OTHER          APD and extracta crash owing to Wirebond.
1049303 CONCEPT_HDL CORE          Block rename deletes schematic data immediately in 16.5
1049317 CONCEPT_HDL OTHER          bomhdl with scm mode not working on RHEL in 16.5
1049399 SIG_INTEGRITY  OTHER          Toggling z-axis delay in CM shows the same value
1049956 ALLEGRO_EDITOR DATABASE       BUG:dbdoctor deletes fillets as design is migrated from old version
1050408 APD          DXF_IF          Symbol has 45 degrees rotation  in mcm but DXF doesn縯.
1050483 ALLEGRO_EDITOR DRC_CONSTR    DRC has been waived but after updated DRC system generated a new DRC.
1050918 ALLEGRO_EDITOR MANUFACT       Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.
1051588 ALLEGRO_EDITOR PAD_EDITOR    Pad_Designer library drill report omits some drill holes
1052005 SIG_INTEGRITY  OTHER          Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
1052045 ALLEGRO_EDITOR OTHER          Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3
1052449 CONCEPT_HDL COPY_PROJECT    Copy Project does not update all relative paths in the cpm file
1052600 ALLEGRO_EDITOR SHAPE          Adding a specific cline causing shape errors
1052753 ALLEGRO_EDITOR DRC_CONSTR    Allegro showing soldermask drc only when the symbol is rotated.
1054235 ALLEGRO_EDITOR PLACEMENT       Cannot place alt_symbols for mechanical parts.
1054269 ALLEGRO_EDITOR MANUFACT       Backdrill Setup and Analysis crashes on attached design
1054351 ALLEGRO_EDITOR SHAPE          Shape voiding fails for board having diffpairs with arcs
1054456 ALLEGRO_EDITOR MENTOR          mbs2lib incorrectly translates refdes label
1055273 ALLEGRO_EDITOR INTERFACES    DXF exported from Allegro has an offset in pad location for Y- direction.
1055328 CONCEPT_HDL COPY_PROJECT    Project Manager - Project Copy
1055481 APD          SHAPE          keepout does not clear shape unless it's picked up and dropped down
1055729 CIS          GEN_BOM       Standard CIS BOM per page is not working correctly with option  Process Selection
1056418 ALLEGRO_EDITOR OTHER          PDF exports the blank text markers whether or not the markers are visible.
1056579 CAPTURE       OTHER          Ability to define custom variables for titleblocks that update for specific variant views
1057003 ALLEGRO_EDITOR SHAPE          Z-copy to create RKI does not follow board outline
1057976 ALLEGRO_EDITOR DRC_CONSTR    No Same net Spacing DRC on attached design.
1058002 SIG_INTEGRITY  SIMULATION    Incorrect Xtalk sim netlist was created.
1058364 ALLEGRO_EDITOR SKILL          axlTransformObject() is moving refdes text when only symbol pin is selected for move
1058940 ALLEGRO_EDITOR INTERFACES    IDF(PTC) out command output wrong angle value
1059037 CIS          PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer
1059389 ALLEGRO_EDITOR MANUFACT       about back drill analisys report
1059901 CONCEPT_HDL CORE          Global Property Change and <<OCC_DELETED>> property value.
1060428 ADW          DESIGN_INIT    ADW Flow Manager Copy Project fails to complete
1060589 F2B          PACKAGERXL    Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
1060977 F2B          DESIGNSYNC    back annotate in 16.5 does not bring in already placed nets as global nets
1061223 CONCEPT_HDL CHECKPLUS       What determines a passthru pin?
1061424 CONCEPT_HDL CORE          Customer creates <<OCC_DELETED>> property values.
1061572 ALLEGRO_EDITOR INTERACTIV    Shortcut keys wont work after "Edit Text" command is finished.
1061659 ALLEGRO_EDITOR DATABASE       Unable to return drawing origin to 00
1062558 APD          DXF_IF          If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
1062982 ALLEGRO_EDITOR MODULES       Module containg partitions has been imported to the main design and cant be refreshed.
1063284 PCB_LIBRARIAN  OTHER          PDV Save As is broken
1063658 ALLEGRO_EDITOR SCHEM_FTB       Allegro Import Logic does not remove library defined diffpairs
1063778 CONCEPT_HDL CHECKPLUS       The hasSynonyms CheckPlus predicate is not returning true for all global signals.
1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager.
1064707 CONCEPT_HDL CHECKPLUS       Rules Checker core dumps on design
1065124 PCB_LIBRARIAN  SETUP          PTF properties cannot be deleted from the setup in PDV
1065618 CONSTRAINT_MGR ANALYSIS       DRCs on board but Constraint Manager shows the columns as green.
1065641 PCB_LIBRARIAN  CORE          PDV symbol editor is crashing when deleting a group using delete or CTRL+X
1065745 SIP_LAYOUT    DATABASE       The logic assign net command crashes the application
1065860 ALLEGRO_EDITOR REPORTS       Design crashes when running a padstack usage report
1066051 ALLEGRO_EDITOR TESTPREP       Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
1066318 CONCEPT_HDL CREFER          Issue with LOCATION visibility in flattened schematic
1067339 CONSTRAINT_MGR ANALYSIS       Relative Propagation Delay analysis in the Partition file seems very inconsitent.
1067984 SIP_LAYOUT    OTHER          layer compare batch fails with write protected file
1068425 F2B          DESIGNVARI    Out of memory message in Variant Editor while 縞hange properties� command
1068547 ALLEGRO_EDITOR EDIT_ETCH       Outward Fanout is not fanning out this 4 sided part as intended
1068966 SIP_LAYOUT    DRC_CONSTRAINTS  DRC update aborts on this design with  ERROR -3000067
1069215 CAPTURE       DATABASE       Capture Crash on usnig a TCL utltiy to correct design
1069517 SIP_LAYOUT    DIE_EDITOR    change die abstract pins tab default action from delete to modify
1069915 ALLEGRO_EDITOR EDIT_ETCH       Allegro hangs with when doing spread between voids
1070007 ALLEGRO_EDITOR PLOTTING       Export IPF omits drill figure characters for backdrill holes
1071722 SIP_RF       DIEEXPORT       Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow
1072067 APD          EXTRACT       When expoting using Extracta oblong pads with anyangle are abnormal
1072791 ALLEGRO_EDITOR DATABASE       Database check cannot fix error and keep report the same issues cause artwork cannot export.
1072806 CIS          EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6
1072843 ALLEGRO_EDITOR PLACEMENT       The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5
1072904 SIP_FLOW    SIP_LAYOUT    Probe pins not being mirrored in Die Editor correctly in Chip Down mode.
1073237 SIG_INTEGRITY  GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.
1073445 ALLEGRO_EDITOR GRAPHICS       'infinite cursor graphics fail -ghost copies as you move cursor
1073464 SCM          SCHGEN          Schgen never completes.
1073587 SIP_LAYOUT    OTHER          axlSpreadsheetSetWorksheet command clears the cells in memory
1073745 CONCEPT_HDL CORE          Import design fails
1073852 ALLEGRO_EDITOR INTERACTIV    While doing a Copy Via use the last 'Copy Origin'
1074279 ADW          DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE
1074791 CONCEPT_HDL HDLDIRECT       User gets port exists in schematic but not on symbol message even though the port does not exist
1075135 ALLEGRO_EDITOR DRAFTING       Ability to edit dimension text block in Instance Parameter
1075151 ALLEGRO_EDITOR SHAPE          Cannot change global shape parameter back to thermal width oversize after having used fixed thermal
1075256 ALLEGRO_EDITOR OTHER          Import > IPF in 16.5 is dropping data.
1075853 ALLEGRO_EDITOR REPORTS       please add "PART_NAME" at Extract UI
1075934 ALLEGRO_EDITOR DRAFTING       Able to Changing Dimension Text Block
1075955 CAPTURE       SCHEMATIC_EDITOR ZOOM in 16.6  using key "I" on keyboard in not centered on mouse pointer
1075964 ALLEGRO_EDITOR SHAPE          Shape voiding is not consistent in conjunction with odd angle and arc traces
1076086 SIP_LAYOUT    IMPORT_DATA    missing wirebond after import SPD2
1076202 ALLEGRO_EDITOR EDIT_ETCH       Allegro add connect causing crash after Hotfix
1076205 CAPTURE       PRINT/PLOT/OUTPU : Printing of User Assigned RefDes
1076536 ALLEGRO_EDITOR DRC_CONSTR    Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top
1076538 CONCEPT_HDL CORE          Property visibility changes in attribute form not updated in schematic canvas.
1076655 APD          DXF_IF          Dxf does not get offset value if die symbol padstack has offset value
1076846 ALLEGRO_EDITOR EDIT_ETCH       Grid snapping broken after slide in 16.6
1076891 ALLEGRO_EDITOR INTERACTIV    Symbol rotation not displayed correctly when defined as a funckey
1076909 ALLEGRO_EDITOR DRC_CONSTR    Allegro crashes while placing modules from database
1077084 CAPTURE       NETGROUPS       Crash on selecting bus when Enable Global ITC is unset
1077169 APD          SHAPE          Shape > Check is producing bogus results.
1077572 ALLEGRO_EDITOR DATABASE       Mechanical symbol created with 16.6 cannot be placed on board.
1077879 ALLEGRO_EDITOR SKILL          Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim
1078380 SCM          OTHER          Custom template works in Windows but not Linux
1078497 ALLEGRO_EDITOR INTERFACES    Import DXF does not seem to work correctly.
1078682 ALLEGRO_EDITOR DRC_CONSTR    Unaccetable slowness with Slide
1079082 ALLEGRO_EDITOR PLACEMENT       Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping
1079533 ALLEGRO_EDITOR PLACEMENT       Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"
1079937 CAPTURE       SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text
1082582 ALLEGRO_EDITOR GRAPHICS       Allegro hangs on a given testcase using the MMB zoom control
1082981 ALLEGRO_EDITOR SKILL          Allegro crash while change the new symbol type as mechanical.
1083230 SIP_LAYOUT    SHAPE          Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.