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更新说明：1 ~; w. r! X+ ^
DATE: 07-25-2014 HOTFIX VERSION: 032
0 u9 L+ M6 e; I: u# W===================================================================================================================================( D' K# V% N" X6 N+ t+ x/ t4 S
CCRID PRODUCT PRODUCTLEVEL2 TITLE
- U$ f) D/ k; n- h" c! O }===================================================================================================================================
$ ^( f0 G' R* @; Q/ R- t381127 SPECCTRA CROSSTALK Specctra xtalk reports aren't correct
: n4 D4 D7 J2 j1 X/ ~) F616770 allegro_EDITOR COLOR Remove the APPLY button in the Color Dialog window.: q1 e/ |0 d* M6 b7 s
982944 ALLEGRO_EDITOR COLOR seperate the Etch to the Shape and the the Cline in the visibility window
8 M. l6 ]; l& Q: j7 X( Q$ R982995 ALLEGRO_EDITOR INTERACTIV Shown infomation for the selected physical symbols) h* d b6 t2 j% {$ W
1024832 Pspice PROBE Shows wrong data & header when exporting trace to .txt
/ c. E2 R7 J" x/ c( n& a1063258 PSPICE AA_OPT curve fit fails with error same data works in 16.5 Simulation error: out of range of data
6 X, Z4 A" [" Q7 x1112360 PSPICE AA_OPT Advacne analysis gives runtime error while using Optimizer in attached design
4 s* s( ?+ P7 Z1154323 PCB_LIBRARIAN VERIFICATION Con2con is choosing incorrect Primitive from Chips file and failing FTB Checks
! G- |! P9 p s+ ?- |1184690 concept_HDL CORE Weird behavior of genview for split hierarchical blocks
1 ]1 |0 |: W1 |3 P, S, N1212577 PSPICE MODELEDITOR IBIS translation fails without any information in log file
( L7 \8 r6 Y/ d# Y. W5 x* p1213204 ALLEGRO_EDITOR PLACEMENT Place Manually with existing fixed net behaving incorrectly% d; u0 v, x' K4 \# Z0 K% `
1213837 ALLEGRO_EDITOR INTERACTIV When copying a stacked via the temp highlight does not display on the last layer of the stack.
6 Q. P* J: c* S- _- @4 @1216519 SPECCTRA ROUTE Autorouter will not add BB via between uvia within the BGA area! L2 D2 T# ~! i& ` r
1220655 PSPICE DEHDL_NETLISTER Support for automatic addition for Power source and Ground Node for Globals in DEHDL PSpice netlisting
( w: R2 B9 \# y c. q) _1223018 CAPTURE OTHER Diff pair Auto Setup not working for the buses.
8 T3 ^; W7 ]3 Z/ x2 y1225689 PSPICE AA_SMOKE Smoke analysis crashes with attached testcase
3 O7 q$ C+ P, W5 q) t+ D1232124 CONCEPT_HDL COMP_BROWSER unable to generate ppt_options.dat file in first go1 I3 Y4 S6 p: w6 \6 d+ j2 X
1235059 PCB_LIBRARIAN IMPORT_CSV pin_delays not being imported into PDV
V4 l: Z+ u2 d! I. `3 `1238815 CAPTURE OTHER Capture doesn?t retain more than 191 library in add part/capture.ini under part selector configured libraries, ?/ d6 p- @% y3 [' v, {
1239241 ALLEGRO_EDITOR INTERACTIV Via replacement doesn't replace with correct via but right padstack name.3 B! Q5 F0 @) K1 ?4 g
1240201 ALLEGRO_EDITOR EDIT_ETCH RPD DRC unresolved evenif HUD turns Green
' M( w* g# E2 b6 t$ p: a1240314 PSPICE SIMULATOR Getting internal error,oveRFlow for the second run
. \" c- P. l$ Z; c$ |/ O+ a1242805 ALLEGRO_EDITOR DRC_CONSTR no_drc_progress_meter variable hangs allegro after running update drc
( J+ w3 j0 k; `& |+ d1243267 ADW TDA URL to TDO-SharePoint should be defined in CPM File
# K) Z: H. Z& {3 `! u; ~' D1244857 ADW TDA Policy File Variables not working correctly in policy file
) S, E5 H8 t5 g7 W1 U: D1245779 CONCEPT_HDL CONSTRAINT_MGR Obsolete objects in DEHDL CM3 n9 a9 S; n. F8 L4 n+ L, j6 d
1246811 CIS EXPLORER Option to keep the part type tree in CIS explorer expanded on every invoke1 b6 |6 a# ~9 x$ m
1246964 PSPICE PROBE Simulation Crashes in 16.6 but running successfully in 16.5) K2 @9 t, o" L, t7 e# n
1248782 CONCEPT_HDL CORE Display winning physical bus names (occurrence mode) in the the lower block of an Hierarchical design
1 F2 G, P* X0 o% P9 d. a7 m1 n1249238 CONCEPT_HDL CORE Uprev from 16.3 splatters text around sch page+ p/ k; h# o& @
1249692 ALLEGRO_EDITOR GRAPHICS 3D Viewer is wrong when resizing its window.
( L! L" C0 m7 ~% w9 o* f1249850 ALLEGRO_EDITOR SHAPE With shape_rki_autoclip Route Keepin to Shape DRC is created
. {8 v8 l# e; |# a3 p2 y. U% {1250683 ALLEGRO_EDITOR INTERACTIV devpath corrupts if edited from user preferences.
' b) {: \/ b' d; |1252059 ALLEGRO_EDITOR INTERACTIV Preference Editor is unable to delete a previous path entry for library paths
' W5 D) e% u& O+ j: Y% D) E1253563 SIP_LAYOUT DEGASSING Not getting degassing voids when close to shape in center of design7 h W9 c. h$ K% _% ^
1254319 ALLEGRO_EDITOR GRAPHICS ENH: Functionality to change the 3D Model color for more realistic view: A1 q5 h% n" b' R$ h
1254562 ALLEGRO_EDITOR DATABASE Unable to delete a subclass that exist only on classes Package Keepout, Package Keepin and Route Keepin.
+ a: Q Y: D& c. Z1255169 CONCEPT_HDL OTHER ADW (BPc) Packager should report the specific corrupt directive in the .cpm file
) A) ?: O7 o! G2 \( {1255573 ALLEGRO_EDITOR DRC_CONSTR Need soldermask DRC checks when same net via and smd pad overlaps
3 E2 U" c! p9 A* f; L* B* x) ^, o1257950 CONSTRAINT_MGR SCHEM_FTB Changing xnet name on Allegro CM.
N9 a" Y. P) x1258165 F2B DESIGNVARI changing visibility of Probe_number in variant schematic changes it to $Porbe_number* ^( m1 k( n8 V5 k
1258274 PCB_LIBRARIAN VERIFICATION con2con crash with no notification or error message
! S( v5 B2 k) |0 m7 @# I6 i( }* {; B1258860 CAPTURE PROJECT_MANAGER Bug: Text Editor (File> New> VHDL File) filters characters from Text. n W9 W* y" t5 f: g9 o
1258872 CONCEPT_HDL CORE Objects are copied (instead of moved) when moved from sheet to sheet* o2 O9 @0 V+ N1 h
1259284 CONCEPT_HDL PDF HDL_POWER ( global) net does not get transferred to the published pdf/ x5 O+ E( c( F/ Y% Y
1259375 CONCEPT_HDL CORE Help link to cdnUsers.org needs to be changed
3 v3 ]% @" t2 @& z/ b1259860 ALLEGRO_EDITOR INTERACTIV Edit > Mirror does not display asymmetrical pad correctly when the footprint is attached to cursor. [3 @8 K! x7 r2 e8 q" O; \7 g3 O4 o
1260002 ALLEGRO_EDITOR INTERACTIV Alt sym hard is not obeyed when using Edit > Move > Mirror
5 F- I5 q* S; v# s" w1260006 ALLEGRO_EDITOR PLACEMENT funckey r iange 90 rotation issue
4 B/ Y+ `; ?6 ~# T( H W; B1260667 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes when running AICC command on few Diff Pair traces.( l/ Z: c8 T" E4 O
1260763 CONCEPT_HDL CORE Export Physical fails with $TEMP entry in Setup-Tools
" f; N( l+ J* C+ {1260847 SIP_LAYOUT SYMB_EDIT_APPMOD Border texts seen as triangles.' U7 A% f. [3 k0 N( Q; W
1260948 ALLEGRO_EDITOR SHAPE Dynamic ground shape is shorting to via of a different net at layer 4 & 5 in this design* o$ v! x7 F Q2 C2 K9 s8 l
1262011 ALLEGRO_EDITOR PLACEMENT Key Properties on Component Instance/ Definition on available to use with Quickplace by Property* J4 V3 Q9 q; _: s- [, `. e
1262322 ALLEGRO_EDITOR PADS_IN Pads_in can not translate route keepout which specified for the all layers.
. X. L- C0 H3 F& L1262626 CONCEPT_HDL CORE PROBE NUMBER attributes lost from the nets after upreving the design
5 i1 t& g: c4 G- b. ?1 i! n" {1263592 PCB_LIBRARIAN VERIFICATION Unable to check in Schematic Model due to pc.db file/ I) a' @! ?" q# E1 l* e
1263685 ALLEGRO_EDITOR INTERACTIV Editing Photo Width value from non zero to zero allegro gives warning- Value must be greater or greater to zero
6 @+ y% e! r7 b5 S9 T/ k! h1263704 ALLEGRO_EDITOR EDIT_ETCH Bug - AiTR wrongly deletes blind vias and do reroutes.
: @0 g& s$ l1 C3 U# ^1265120 ALLEGRO_EDITOR SHAPE Require voids in dynamic shapes to use pad value
) k& z5 A/ \: n6 `) L1265275 ALLEGRO_EDITOR DRC_TIMING_CHK When XNETS are dissolved by removing the Models all Physical and Spacing NetClass associations are lost1 @$ N( [. W# e
1265633 PSPICE SIMULATOR Bias point result is different in consecutive simulation run of the attached project
% f4 b/ i6 d# W& S1266349 ALLEGRO_EDITOR PLACEMENT Rotating symbol while placement show wrong angle of rotation than the placed angle when Angle is set in Design Parameter
. j) r) @* d9 j7 U1267541 PSPICE PROBE pspice.exe does not exit when run from command line- U$ l2 b+ u& F& {3 I& V
1267707 ALLEGRO_EDITOR PLACEMENT Mirror Command - preselect/postselect bug with general edit mode
" _8 f' {: _* d% j3 H0 \1268299 PSPICE STABILITY Pspice crash on attached design
' [# T2 R* \# H. F1270879 ALLEGRO_EDITOR COLOR Color view save creates .color file using older extension
% _- C& \0 P5 B+ R1271295 SIP_LAYOUT DIE_STACK_EDITOR Die stack editor support needed for large variant combination designs.
: s- T" l( z @ U" N. _1271385 CONCEPT_HDL CORE Locked property can still be added
1 L9 {9 ~9 R4 _, }: E1271853 APD OTHER When using the beta "shape to cline" command, add improved messages and partial completion of individual segs in error.
* C/ T# V' A3 H: t4 x6 t1272197 CONCEPT_HDL CORE concepthdl_menu.txt contains invalid Variants menu
* M/ N8 \0 f4 b' a7 W$ Q2 Y1272318 CAPTURE GEN_BOM BOM_IGNORE not working for Capture BOM on hierarchical designs.7 c5 [, ~# g0 ^) I& ?( x8 X
1272743 ALLEGRO_EDITOR PADS_IN PADS Library Translator does not open the Options dialog window.4 [) |. T; h# ]; E' |* w2 j
1273517 F2B PACKAGERXL Netrev error - ERROR(40) Object not found in database
4 F, q+ c+ W5 ? E1274000 ALLEGRO_EDITOR DATABASE PCB layer can't be removed
' {! I) d: A5 N2 T, Z7 x1274530 ALLEGRO_EDITOR INTERACTIV Add Circle radius value changes next time using this command0 _8 T7 V9 P9 K- ^' f9 z& P ]
1274697 PSPICE AA_MC pspiceaa crashes when running Advanced analysis monte carlo for the attached design
+ [# A; ?; T* {6 m. M! |1275154 CONCEPT_HDL CORE Hierarchical Blocks lose ref designators when moved to another page
# U& u0 K/ _+ M# b' w) u Y5 ]# D0 i1275724 GRE CORE AiDT delete another clines. I, S! c5 z6 t5 y" a# e o( I
1275831 ALLEGRO_EDITOR DRC_CONSTR Waived DRCs return when using multi-thread DRC check' W+ Y8 F% ]3 W$ O2 H' w
1275834 CONCEPT_HDL CORE ERROR (SPCOCD-569) on global bus
! c0 T) u. R8 T* l, D8 Q1276334 ALLEGRO_EDITOR PADS_IN PADS Library Import problem with outlines
) s$ b$ t, c2 a( o1277062 ALLEGRO_EDITOR PLACEMENT Swapping parts from top to bottom Orientation changes
4 A* o4 W1 t9 P( Q" Q' i1278746 ALLEGRO_EDITOR DRC_CONSTR Package to package DRC allows place_bound_top in 0 spacing has drc in 16.6 version.
, f" m/ ^3 j7 t1278804 CONCEPT_HDL COPY_PROJECT Copy project crashes
6 V5 f! U( P- M1 C' {4 k4 w1279362 ALLEGRO_EDITOR INTERACTIV User skill file makes Allegro Icons gone away
1 ^( T# O0 O& u- O8 A/ p1 F1279619 ALLEGRO_EDITOR DRC_CONSTR Netgroup in a Netclass doesn't inherit Spacing Cset
6 v3 J0 ]$ s, x2 V1279815 CONCEPT_HDL CORE Text > Change and RMB Editor does not allow multiple text edits
% X2 z4 r/ o1 r8 U( X( V) j7 C1279876 ALLEGRO_EDITOR DATABASE Using the Curved option in Fillets results in a pad to shape DRC
) @. O3 @: I1 H0 W% q% Q& ]# F, L' `1280435 F2B BOM BOMHDL with variant repeats the PART_NUMBER value7 ]; U: P6 z& R) M; P
1281669 CONCEPT_HDL COMP_BROWSER Match Any radio button in Component Browser didn't work.
3 v) }/ k2 i1 X8 j3 l1282001 ALLEGRO_EDITOR DRC_CONSTR Updating the DRCs on this design cause the DRC count to change on every update
$ [: f' k7 W. o4 c- c5 n1282480 SIP_LAYOUT WIREBOND Info on the Wire Count property needs to be updated indicating that it is a User Defined Property1 G; s# |3 y7 g8 J3 j
1283952 ALLEGRO_EDITOR PLOTTING Published pdf does not show dotted or phantom lines2 U8 y2 R% C' c5 z; `+ {; D
1283957 ALLEGRO_EDITOR INTERACTIV Replace padstack in "Single Via Replace Mode" is changing netname of the vias with the latest hotfix of Allegro 16.6
& J* R# b6 X" V6 l* m1285588 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase control has wrong analysis result when add rectangle test bead in Clines.
+ o4 [/ }4 j( Z+ l1286743 ALLEGRO_EDITOR SHAPE Getting copper islands in the design after running the Delete Plating Bar command; M' b( I% E9 R: K( l
1287215 ALLEGRO_VIEWER OTHER Allegro viewer plus does not support constraint regions
8 D! b- w2 `. y7 p8 l* w1288808 APD LOGIC Derive Assignment stalls out or won?t finish and appears to run out of database room.
0 N; r& p2 r o1289251 ALLEGRO_EDITOR SCHEM_FTB Pin escapes (clines and vias) not inheriting new net name from a pin with a new net name.- m& y) d$ d9 F* Q W
1289293 F2B DESIGNVARI Warning 04: Cannot merge the variant properties on variant instance C119 component with same canonical path not present$ i4 G- h7 g- B% g
1289809 SCM VERILOG_IMPORT User not able to import a verilog netlist into SCM9 x5 r& e. I0 Z V* @
1290696 CONCEPT_HDL CORE Copying a net name repeatedly causes it to go off grid7 q D# Z7 C$ D
1291162 CONCEPT_HDL CREFER crefer crashes when selecting generate cross refernece for all nets selected( t5 z# d8 r) c7 }# {: M
1291285 SIP_LAYOUT IMPORT_DATA Replacing a Die with the Die Text in Wizard causes some Clines to Shift, creating new DRCs.
- n$ J; u) d' u3 L! d1291658 ALLEGRO_EDITOR INTERACTIV Cannot add Frectangle to Group
. _) u5 H0 w0 x* p1292180 ALLEGRO_EDITOR SKILL Allegro Crash while performing query contents of "Maximum_Cavity_Size" with the skill command 'axlDBGetPropDictEntry'
: Y2 @1 G) U& w" K, I7 N1292210 CONCEPT_HDL CORE DEHDL crash if design was opened with -nonetlistuprev option.
/ F# i9 R- z- r. u" p1292278 SIP_LAYOUT WIREBOND When creating Wirebonds by Importing a Wirebond File, (wbt) the wirebonds are not on the correct Die layer7 v: K% g* z. t" \; ^9 @
1292282 SIP_LAYOUT INTERACTIVE Getting Multiple GUIs when the Wirebond Import is open and we select outside the command GUI.
+ ^' s3 M" ]+ ^3 N4 j$ \; _ e) {1293381 SIP_LAYOUT IMPORT_DATA Import SPD2 error* O, T& [! q$ o
1293889 CONCEPT_HDL PAGE_MGMT page name regression result deleted by netassembler
* ]2 P& \" _3 P3 d" [: E7 {9 {$ X- |1 K! H1294124 ALLEGRO_EDITOR INTERACTIV Samsung Mobile division wants to disappear the grids in the display window when zoom-out function executes in the allegr$ i, a; `9 b( ~
1294749 ALLEGRO_EDITOR ARTWORK Null pad is flagged as an error that break Thales automatic tape out
! y5 V9 b7 ~ f! S; _4 s1294777 ALLEGRO_EDITOR SYMBOL Mechanical symbols missed on STEP result
! U2 \: S+ D0 \6 M. w
4 ]( N3 [4 \% @7 {2 gDATE: 06-20-2014 HOTFIX VERSION: 0315 `6 ^5 G9 L( o9 L% Y3 t" \. q. Z
===================================================================================================================================( g& v, k" e& r; G' E1 j ~2 |9 _
CCRID PRODUCT PRODUCTLEVEL2 TITLE
7 Z- g/ M+ o# [" y! n/ c6 Q===================================================================================================================================
) ]2 a4 q5 D% H2 J0 |( \/ y726553 FSP CAPTURE_SCHEMATI Method to select bus bit?s order while generating Capture design from FSP.
2 O! f0 D, ~7 y- Z& i8 o1257631 FSP DE-HDL_SCHEMATIC Schematic Generation selects incorrect symbol version- i3 g9 h( A! j
1273456 ALLEGRO_EDITOR PLACEMENT Place module instance causes Allegro to crash
( B' I: ?6 m5 m& }9 Z3 f1277099 ALLEGRO_EDITOR INTERACTIV Clines and pins are disconnected even though they are at the same x, y coordinate.0 x6 R6 Q% G* W! I2 r9 s) q
1280913 ALLEGRO_EDITOR EDIT_ETCH Add Connect should be able to be made by go straight even though the cursor is not exist on straight line5 R' ]% t5 q6 y/ H0 Y
1282491 ADW PURGE ADW PURGE is removing Page Name data in DEHDL
; W6 Q8 e* Y% q- b& z. c1283045 ALLEGRO_EDITOR DATABASE Ecset not getting downreved.2 B" o0 @8 ~4 Z/ s: L3 D
1283138 SIP_LAYOUT IC_IO_EDITING symed app mode chooses wrong text block sizes for I/O driver inst names+ ]! w/ [8 e; R! q' o
1283227 PDN_ANALYSIS PCB_STATICIRDROP Enhancement request to add 32 bit files for IRdrop
; z8 z! k0 N1 F6 B Y5 G1284656 CONCEPT_HDL CREFER Crefer fails on large design
6 H9 ~( C# M7 ?+ Y$ _" g1285814 CONCEPT_HDL CORE DEHDL crash on opening the Design
9 P7 D2 N" \: s; C1285967 ALLEGRO_EDITOR EDIT_ETCH Slide via in circle pad1 v; `* s8 ]5 ]3 z7 P6 a" q! X4 G
* h* i1 n7 \+ a; i! PDATE: 06-12-2014 HOTFIX VERSION: 0306 D/ y6 ^- S/ w; U+ Y
===================================================================================================================================( {2 e' z, N5 r0 l: m: ^8 w6 M9 E
CCRID PRODUCT PRODUCTLEVEL2 TITLE$ H0 K4 Z/ f- y w F; W7 {
===================================================================================================================================
- C+ Z- L8 H- C% A6 y/ r982961 ALLEGRO_EDITOR PLACEMENT Show the Rats when one selects physical symbols to place them
+ d! O9 @ B5 U1138680 FSP POWER_MAPPING Ability to assign decoupling capacitors in spreadsheet like application
1 F; m# ?# `1 X1243410 SIG_EXPLORER EXTRACTTOP Circuit topology extract failed in case of CLASS" ?3 V; I8 |! ?* r; G) J
1262977 ALLEGRO_EDITOR TECHFILE When importing a certain tech file into an empty .brd Allegro crashes.4 p8 x- V5 K, I) R% `& a
1267558 ALLEGRO_EDITOR INTERFACES Arc part of symbol pin missing in 3D view of step model
% ^9 Q+ F5 S- ]% Q( r8 e1268252 ALLEGRO_EDITOR GRAPHICS step place bound issue(3D View)% W! X- y! q( O \0 A
1270450 ALLEGRO_EDITOR INTERACTIV footprint add line on line crash- s: w% Q6 s: Q3 ~9 _
1270962 CONCEPT_HDL PDF PDF Publisher command line does not print pdf file if double back slash is present
- @4 E3 n7 t$ P; \1270964 ALLEGRO_EDITOR mentor Mentor translation crashes with no errors in log file" {3 p2 Y/ _2 ~ u/ d3 h# e. J8 ~
1270999 MODEL_INTEGRIT TRANSLATION ibis2signoise Issue
* w. q$ s* c7 ~1271543 ALLEGRO_EDITOR PAD_EDITOR Library import reporting missing padstacks1 z1 c7 Z6 W. V( V' G
1272099 ALLEGRO_EDITOR GRAPHICS Plotting does not fill shapes1 S/ B7 ?# o, Q9 Z, C3 n
1272406 ALLEGRO_EDITOR DRC_TIMING_CHK SKILL command 'axlDBTextBlockFindName' returns 1 when nil is expected
9 q+ V) c0 N9 }0 F/ d; a$ e1272748 ALLEGRO_EDITOR GRAPHICS 3D viewer crashes on this specific testcase
# K' l& @* b! N0 {1272793 ALLEGRO_EDITOR GRAPHICS 3D view doesnot displays hole with offset correctly
# l. U$ ^2 t2 e7 ]# E# i0 Y$ I1272863 ALLEGRO_EDITOR INTERFACES Ability to find the origin of STEP File in order to place it exactly where it needs to be on footprint during mapping./ [1 V: p& ^- }" k" F2 _2 h
1273264 ADW COMPONENT_BROWSE hyperlinks not recognized in the component browser
1 Z( T* `/ C9 Z2 l1273304 CONCEPT_HDL PDF Publish PDF from commandline does not work if there are spaces in the Path1 X' H% i( i" r. P
1274661 CONCEPT_HDL CORE I can't copy a property from one component to another
) A0 J1 M9 W# l/ `$ F2 ~2 X1275237 ALLEGRO_EDITOR DATABASE Allegro Crash on running DBDOCTOR for a board
) g/ t- H6 U" i' G/ {% S. z1275345 CONCEPT_HDL CREFER The Xref information page number values are incorrect$ j- [3 ~$ e% [1 ^8 `
1275748 APD IMPORT_DATA WireBond starts away from the Die Pin after importing Die using Die Text In Wizard8 m4 k/ V' i; R) M- G
1276270 CONCEPT_HDL CORE DEHDL crash by Zoom In > Ctrl+A > Move( l% S' S/ l( N4 j0 G1 |4 D
1277735 SIP_LAYOUT IMPORT_DATA sip layout spd2 translator issues with offset die and mirroring5 R; M# X" a3 \
1279258 CONSTRAINT_MGR OTHER Import logic stops with error
5 h' G: j. K$ Z& {9 H+ R9 Y& ]1279694 ALLEGRO_EDITOR SKILL axlCNSSpacingMin('via nil) crashes Allegro PCB Editor
7 v) N8 h% Y* F6 a$ p J
: o* b7 E; }1 u9 FDATE: 05-23-2014 HOTFIX VERSION: 029
; {6 U( ~1 A5 |# }4 B6 x5 e===================================================================================================================================
8 w' i( N) l- sCCRID PRODUCT PRODUCTLEVEL2 TITLE/ J4 r( E) U. a& g! v
===================================================================================================================================8 i$ `; i1 v$ L3 J [* m) c
1209461 FSP DE-HDL_SCHEMATIC Hierarchical Block Size not automatically adjusting to text needs
: e! [( Z& h2 B1217832 SIG_EXPLORER SIMULATION S-param generated by SigXP doesn't match with HSPICE/ADS.
' I) w* ?* Q0 V1263575 CONCEPT_HDL CORE Copy-Pate makes Components Off-Grid
6 S" z: P* n& `; {# p! e& K3 T) c1267602 SPIF OTHER Route Automatic hangs- k3 C4 e `% e& Y7 p
1268022 FSP PROCESS FSP is not respecting the use banks for attached design.
6 }7 R/ e% J6 m0 f, ]1268587 ALLEGRO_EDITOR INTERFACES Enh. Preserve relation between hole and padstack in IPC-2581$ D$ d& y4 a# D8 Y
1268918 SIP_LAYOUT DIE_ABSTRACT_IF SiP - DIE export from co-design object to XDA results in missing data& S4 n+ e3 J8 q" x( q% c% H
1269232 CONCEPT_HDL INFRA While pspice uprev the design crashes
) N" ~4 u" q$ j- K: m1 {+ _ w& ^1269825 SIG_INTEGRITY SIGNOISE PCB SI hangs when running crosstalk simulations7 o5 k+ t- V* z5 \' A$ X
1270963 ALLEGRO_EDITOR GRAPHICS Add Circle lint font hidden/Phantom has resolution problem
$ Y+ ]( ], N' J' s; H7 E1270990 ALLEGRO_EDITOR GRAPHICS Allegro response is slow when added circle8 w% i: a1 j, w) H
1271655 ALLEGRO_EDITOR MANUFACT Dimension option causes a generic crash, reproducible in any design
$ S! P! |" c' S1272495 ALLEGRO_EDITOR MANUFACT Filtered Part numbers in IPC-2581 still pass actual part number for references onutide of BOMItem
8 ?4 }1 y3 F2 Q8 z0 m3 ?) f& x0 f1272839 ALLEGRO_EDITOR MANUFACT Kindly explain the drill legend behavior when padstack rotation is 45 degrees and mirrored ?- j8 ~; c- x1 [* P, h' e& D) Y4 d
1274518 ALLEGRO_EDITOR ARTWORK Artwork does not create void correctly.
8 S4 H( I5 M0 m, S2 C# Y$ |2 ?$ v: M- a: A( M) H2 l
DATE: 05-10-2014 HOTFIX VERSION: 0286 M+ q8 d: b4 u4 a: n/ e
===================================================================================================================================* @) W) I% I- l8 g! d. k
CCRID PRODUCT PRODUCTLEVEL2 TITLE
+ f$ m) W: m9 A; [! R9 g( ~* y=================================================================================================================================== x$ P; L) G" E( _
1199256 ALLEGRO_EDITOR INTERACTIV DFA bubble does not appear when moving a symbol to within another symbols dfa bounds on specific symbols7 }* ], E4 R' z/ o. `' ^2 H9 b9 k* ?
1220196 ALLEGRO_EDITOR OTHER create xsection chart results in ERROR(SPMHA1-73): Text line is outside of the extents.# D' U) l" Q/ V) p
1259520 ALLEGRO_EDITOR EDIT_ETCH Allegro will crash when adding connections to a differential pair. I, v. N* m7 q7 h0 i+ h
1260446 ALLEGRO_EDITOR VALOR Creating odb output the xhatch shapes where arcs are will become inverted. Difference in the geoms.out extraction?8 G1 I+ z& i0 ]; N
1261313 ALLEGRO_EDITOR INTERFACES Step mapping does not show all Available Packages$ \/ a4 i# G: V1 M6 X
1261356 CONCEPT_HDL CREFER crefer is crashing with generate for all nets option
, C7 H2 ]6 X7 c4 A* I g1261514 ALLEGRO_EDITOR ARTWORK Exporting raster artwork with overlaping voids fails.* @2 \( `4 ]" r( `; Y
1261735 ALLEGRO_EDITOR ARTWORK Presence of Smaller shapes inside bigger shapes is crashing artwork generation.* @) L8 j4 V3 e2 Y q9 h
1262019 ALLEGRO_EDITOR INTERFACES Artwork control form hangs if we close PDF publisher gui% h. Q" ^, A6 U4 S
1262246 CONSTRAINT_MGR ANALYSIS Constraint manager shows ALL PASS when Adding members to a NetClass and adding parallelism rule1 w' r! E+ G1 ?# l/ v6 c4 Y" w" W
1262560 APD WIREBOND bondwire can't connect to GND ring directly4 Z6 `6 _" t% z8 r5 P" O- V6 G! X4 g
1263275 CONSTRAINT_MGR OTHER Import of constraint file hangs in this design
4 I1 G C& n4 }7 H3 }. j1263358 SIP_LAYOUT OTHER SiP Layout - Void adjacent Layer enhancement to merge voiding for PADS without changing shape params; @- | t5 o% f. E
1264109 ADW LRM LRM error - WARNING(SPDWREV-7): Unable to read the design
y7 m8 F7 s! ~) L# {* d1265580 APD MANUFACTURING Icp_soldermask_allow_pins cannot create correct solder mask when the pin rotate.3 _. j, g( d( K( E5 z
1266391 APD LOGIC SPB16.6 Derive assignment : want to select 1 DRC marker only.4 n+ x/ w. k! a' p( R, ^0 W" x
1266687 ALLEGRO_EDITOR SKILL The SKILL p- Y! s5 g7 D. t3 P+ e
1267267 SIP_LAYOUT WIZARDS Attempting to create a die using the die text in wizard but the tool is not creating the correct die outline
$ X: f5 w/ L% W+ h1 h$ a4 ~7 ]1267308 SIP_LAYOUT OTHER When updating a BGA with the Symbol Spreadsheet tool it will start, update a few pins then stop.
) r" F3 f% x# ^( v: @0 `1 J1267639 ALLEGRO_EDITOR PARTITION Allegro crashes when partition is created and opened from a location that contains "!" in its path.
$ S3 `. f& L0 A$ O8 O9 j* }7 k- q7 O1267704 SIP_LAYOUT STREAM_IF Cannot import stream file, the tool starts scanning the file and never stops.
p/ j2 k: z% ^1 y) r# M1267907 CONCEPT_HDL CORE Ctrl+RMB Context Menu Option doesn't work.8 O e1 @4 _' e( c5 b
: `3 G3 X! F$ e/ M) {
DATE: 04-25-2014 HOTFIX VERSION: 027; M' {3 r) m; i4 G
===================================================================================================================================
' ]' x5 ~2 e( k3 J1 W9 y5 r/ P. mCCRID PRODUCT PRODUCTLEVEL2 TITLE9 o% a8 m+ `, E- E" m
===================================================================================================================================
. g2 W* y! h6 [- M! j. q; a l308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM
4 e! x& i2 _+ G. M+ r& m481674 ALLEGRO_EDITOR PADS_IN No board file saved from PADS_in
. E1 G9 e& T8 B% x# [- B982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.
# V! p) H( g; E1012783 FSP OTHER Need Undo Command in FSP
$ z: _/ [1 {; n% ? Y2 F" q/ v1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.
1 {0 r0 V; w/ b& G1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
( x( S0 g& x0 ?/ g4 e) H/ P8 E1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode." p' H# l, k9 B4 Z9 v
1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups# @. s$ o* d% U i
1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash
/ L2 E. `" b! d! R' v( a- }1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command
. _0 \3 {* `0 g/ T3 [$ s, j. e: B1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode9 q9 f; v$ Q! `4 J. U, V
1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
5 a6 [& f0 @% f1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
# Q9 t) H7 t- G1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings
8 p6 e( t* A) [4 d1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
5 x+ w$ o) V/ w2 V: h' c1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV$ }; y1 E+ ^/ }+ D
1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.: q( _8 L" J7 {; E+ ]: ]
1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates" R$ M0 o. A$ Q* h9 H
1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime ]8 D( Y, A9 T- T' ]- Q
1208478 PSPICE PROBE Attached project gives overflow error with marching ON.! S5 F" x1 r+ `1 y( T0 \
1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol0 Z! P+ @* E' Z! t" Y/ i$ D1 v
1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed
" X# }. ?7 b4 m# `. L. Q7 a- l1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape" x" A3 @' h1 W6 Z& r; H
1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers
7 y2 ~! q. n; _6 R; K) G! W1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?
% I6 p8 f/ |0 N+ C1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.
6 {$ f) h- |0 t$ I* g6 l1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values
1 [6 g! X6 ?" r* h+ @7 c1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging# D! h& i; f: ]3 P
1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information8 T7 M5 E/ T% |- q
1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added" v. Q9 y' F2 M3 ]
1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
& n8 J! u) Y# H$ ^5 z9 f! A5 c, Z1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes
* A" h( C w2 B, `% T- c) z) n1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux
1 u) G Y7 x0 m+ t1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
- l& i/ X+ {9 T+ K: L7 L# L1221182 ADW TDA Team Design with SAMBA
. q, z, E' \9 C1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair1 p) d# @' ` H
1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened
; P1 N8 c# l6 m: w5 {1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
: {% z8 @1 W; u- y1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
; K g% D; [9 c, b1 ]1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms3 X; F- l0 R! N* ?, h' P- M
1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.$ |1 H$ W2 Y- h; h9 y+ A' {
1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor8 o# f+ Y% f, H0 c& M0 @
1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.; S2 _+ a. G8 L" q, A; p& j- y% Q
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path7 h: ?# Z) i$ ~
1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin
2 X8 K0 h, t/ d# O1225494 CAPTURE DRC Different DRC results for Entire design and selection0 }0 U/ r, y9 a' p" ?
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property `' |& r5 P# T2 F5 Y
1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet
+ w- U4 Y3 r8 { | ]1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet
1 W R5 z7 f0 w: L% S1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts� function is inconvenient for Global Signal
X- m$ |3 |. ~6 P! B1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
2 ?( [. ~! @- X% C+ x, H& |6 S2 s6 p1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
5 h5 n& v% c7 O" O+ Y$ Z1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
/ |$ H0 y8 V5 Z% r U1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration
" I0 S# k0 M3 e* @* `0 N. q1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part$ J# o+ c r2 \ _( a
1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case
8 y4 T4 R) i# K6 `: B4 Q" ?+ |5 ?+ t' a/ q1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins
1 i/ v9 H- H" k Z1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
0 \6 }+ }- u d6 P8 r7 q6 B1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.) N0 ]2 m: o& a6 r7 d
1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
% W( I7 W( n0 w' A7 m: a1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).5 m% o4 U7 g8 c- E: X
1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM
w0 @9 O z' } k4 ^7 E1 d1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
7 O# C* z( `$ O( e& A) E W, D# [1230432 CONCEPT_HDL CORE No Description information in BOM: W& Z6 I _6 M
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes% r( O9 _4 e6 q6 @
1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files) k; O& J6 t1 \0 F% s
1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands1 v" I( a( `5 s1 j) z
1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets4 Z% e4 B3 C; M1 y- P- C. @5 r
1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
5 ~, Q. K& ?; |" U1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode- Y5 r9 q, V* F, u( \9 A
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical# t# b7 B i2 l$ l
1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode' O7 t3 u1 t$ k% g, x) q
1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files
; z9 I7 S8 E+ z1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy) O9 N7 l+ Z7 U D" R
1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved* m5 E; f; b5 f* V: r7 t, S
1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect) E1 c/ p' w8 u+ @+ [% A% [
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set% N6 r6 {% H9 }+ R; J
1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
) e9 v7 ~. H. L8 \. ^% j7 g1236161 CONCEPT_HDL CORE Import Design shows the current project pages
2 v/ r& ]9 }" \1 W+ }1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.
1 r6 c; ~/ {, ^# w0 S" V1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion
3 T) l3 B: K& w8 f ?3 ~1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file
! h* U% p/ U& a6 \2 @1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape* |, D- u; U0 u4 q7 Z! r; H& P6 j
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming
6 f" E$ e' M# I+ Y1236781 F2B PACKAGERXL Export Physical produces empty files. G! S% y* K, T* Y3 e) }
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run
& `' F! u, D+ n1 u- ]6 B1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib� command
7 v1 v) x5 D( S [3 p, K9 H1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
6 x8 Z1 Q( V {. i1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
9 H. n$ f- K. ?9 r& d: H5 h% @' I. H0 v1238852 CAPTURE GENERAL signal list not updated for buses+ o7 x" p. U$ e( k3 ?
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes
0 g$ y9 e" B; m! y2 `1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.9 y; L# K& C3 }7 ?8 x
1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE
& p& j/ b" ~3 N0 Z# I0 y+ A1239763 PSPICE PROBE Cannot modify text label if right y axis is active6 M# o: s# F+ ?7 y6 J% ~9 L: s
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images# p3 o6 ?' {/ `4 q
1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture., v0 {1 @$ P; L, I. d
1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing
- k0 O( X Y- R% _+ k1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file' i# P8 N8 v4 N/ m- \
1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable2 f# [! T3 c; n, G( j6 \; e' r
1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy
3 G- V0 Y8 u% I2 i. L' C1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms+ {" H9 \, V- i" G4 V" k8 N
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working7 {" |" W) H+ m% ^. |: Z* g- P9 ?
1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.
( \# Y4 _# G. U# @; }5 x7 ^1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard: m* |; g( H+ S8 P g$ W
1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning% O% X; O2 x1 ^
1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side
6 S, S5 k0 c7 Z1 B1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer/ y8 g0 d& E; v9 O. m) N4 F
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results$ ?6 V* W2 ]1 R
1243609 CONCEPT_HDL CORE autoprop for occurrence properties5 b/ e6 N& l3 ]* L1 U0 r
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI
7 ~# Z4 s+ x7 b. K1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
9 }, ] j: Y* o0 q) T8 A% x/ I1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring
$ J% i% B4 ^ |) i1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder
% Q# `" y5 r- y! L4 C1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is; Y9 @* u: I* e& z
1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design
. \' ~" [) ?. w0 V& |1 J1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?; v% u! Y. m* O" d- z5 F) A
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character
. O( }3 X5 X' k" j& F$ r1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters
?1 u6 l! v" Y. t. S9 j1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown
( @8 K' M: U- B, u! C4 ^9 b1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number+ x# _- q( @$ t; Z
1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL
4 J$ M5 T4 e! p# r/ J' q% j/ p1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained
7 x1 a- _/ x& b: ^4 d; @1247462 CONCEPT_HDL CORE Text issue while moving with bounding box9 {; D3 E z% X K6 S2 A/ d" h* G
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered, G( {/ W9 c$ W$ q
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components5 s; K8 D$ K9 K# f$ ?8 ]8 a4 q
1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts# k# `" L( c9 |. O+ [* g/ V- I
1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.
/ n. d0 G: ^: }# W$ Z1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
! w& O1 P8 E! l: m& v" K9 T1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly! _4 |9 I/ s- i; l {' S `
1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.
& b2 E( N5 m- _# j! \$ Q- f1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies0 a% v5 i) x) {$ y
1253424 SCM SCHGEN Export Schematics Crashes System Architect
2 o' ]- g% N E0 m n( l1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled7 K0 ]6 B5 k) J' N0 s
1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing- d7 s' l9 E$ t! L7 L( s4 q; Z! m
1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router+ b: z N' r8 U! W3 ~
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error
# n2 k, C! v( E1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.
. h0 M2 x. }/ l( d( p2 x1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation
; Y% ^' ^) @6 b8 w9 }2 X `0 z1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects
( i, P+ f* D' S% w: S1 g1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode
* f Z) N. s! a% D1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
; {1 ~5 ]* f2 U |4 H$ T1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
6 E8 e0 O# U) {6 s1 t0 ]1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool6 `4 Q: U3 w) S$ }" P
1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design
8 N8 R! R* A4 k7 }/ ?. ~1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library
( Z7 G& U: N5 `6 p" ?* `* [1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long: q9 v: B5 T: l. i
1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash$ [4 J' \3 T, R1 C% ?
1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time
: T; M( @2 t9 N4 {* ]1258029 APD WIREBOND The bondwire lost after import the wire information
, {* B, n# @8 X, T6 N/ P1258979 APD NC NC Drill: There is difference of number of drills.
6 v6 E+ S- x( W* C/ o1 l/ Z( ~1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement) u7 {# | U, e& F$ h# u
1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change. \+ a2 E* J" `+ w T9 `) Y
1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"
Z! g+ @6 g$ |% p( W1 ]1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines6 u c& j/ q2 l7 ]# s6 [
1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void% v$ V% @# C2 q4 [3 m% n5 U/ v$ n
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
& E- e8 [3 P' b6 R
: ^+ ^5 o9 _ \) v ]1 iDATE: 03-28-2014 HOTFIX VERSION: 026
, Z ^- z( V- o& T' S2 V===================================================================================================================================/ J0 N) I2 v6 L, i! U7 T2 n
CCRID PRODUCT PRODUCTLEVEL2 TITLE: e" \, v! }- N6 D* u" l
===================================================================================================================================
& b1 T% S7 X5 E5 L( |$ l1190942 CONCEPT_HDL CORE Cannot copy locked .xcon files0 J/ w5 y$ A+ l& w( k/ V
1226085 F2B PACKAGERXL Winning net NC shorted with loosing net due to PACK_SHORT
+ T6 s% Q$ z" |' @1244894 SCM SYSTEM_OBJECT Get packaging error when adding a pullup/pulldown resistor
( S# r4 Q; }5 w2 O1247432 CONSTRAINT_MGR OTHER PCB Editor crash
0 t/ J2 \# M$ r4 M, ^1248560 F2B DESIGNVARI Variant Editor > Help about for S024 says unreleased ?" [, R- g# X) b% B0 n: ]. [
1248712 SIP_LAYOUT WIREBOND Changing the charecteristics of a Bond Finger causes it to shift position
" L. Z' E6 D7 ?- }& X1248839 ALLEGRO_EDITOR OTHER 16.6 S023/024 crashes on Logic Change Parts command.3 N' `* N+ c+ G# D1 k; L
1249000 SIP_LAYOUT DIE_EDITOR unexpected shift of instances/pins by co-design die editor
. U6 M5 V; z8 H- n3 y: @1249186 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 ignores property UNUSED_PADS_IGNORE9 g& {2 {9 \" H3 k/ P
1249272 SIP_LAYOUT IMPORT_DATA film resistor pins/pads are created on the wrong layer. Always synthesized on top cond layer regardless of config file0 W$ v# @3 _) T# e5 n
1249792 ALLEGRO_EDITOR INTERACTIV Cannot place rectangular shape as per included width and height.' I+ e& }) ? U; M
1249801 ALLEGRO_EDITOR INTERFACES Bug - Arcs in IPC2581 export are corrupted5 y1 i- O1 w3 c5 i7 C/ V
1251006 ALLEGRO_EDITOR INTERFACES IDX does not recognize PKG_PIN_ONE property7 y5 c, g( Z: \
1252142 ALLEGRO_EDITOR INTERFACES Remove inappropriate Conductivity specs from the dielectric layers from the IPC-2581 output
: q: D! E% M4 e( \: V1 t% Q) N1253047 ALLEGRO_EDITOR SCRIPTS Bug: SAV file when creating symbol
E) I# q8 z# N8 x
* U& Y, t: {' k3 b& BDATE: 03-13-2014 HOTFIX VERSION: 025. `7 d8 W8 A0 b4 l* w
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1194646 CONCEPT_HDL GLOBALCHANGE Global Update > Global Component Change does not work
7 i3 [9 w1 \6 P; }9 b* x1227843 SIG_EXPLORER EXTRACTTOP Cannot extract the topology correctly.
7 ~. w D) h4 [* M( a$ C% [ n1231510 ALLEGRO_EDITOR INTERFACES IDX exchanges with CREO 5.0 issues
" N3 z& Y" l& o2 R* Y6 n- F k/ m1233030 SIG_INTEGRITY GEOMETRY_EXTRACT Net Parasitic of ground Connection
{6 h8 T) P) _# X1236961 SIP_LAYOUT OTHER Moving component using Place Manual -H causes mirror_geometry.; K5 Z8 `9 v* L6 A' \+ F8 i( ~
1241456 ALLEGRO_EDITOR EDIT_ETCH When creating Die pins or changing their attributes an oval is placed on the pin
. Q' t: x4 @: u& H/ R1242461 SIP_LAYOUT OTHER SiP Layout - DIE is being mirrored when placing, g$ E0 B! n9 m. p3 U
1242682 CONCEPT_HDL PDF PDF Pubisher crash DEHDL on design$ O2 C9 P, A* z7 c
1242685 SIG_INTEGRITY SIGNOISE Incorrect net name was displayed/output if the net include consecutive underscore.
; T7 {2 y& o& U3 N+ H5 [1243357 ALLEGRO_EDITOR INTERFACES Ability to add any new name9 ]2 w% {6 {2 {7 ^
1243758 ADW COMPONENT_BROWSE I don't see an option to switch between database and cache mode
# C" J+ u* K) f% \ Q& ]1244325 ALLEGRO_EDITOR INTERFACES Merge all the BOMItems with same part number into one single entry in IPC2581B.9 X* o: O. c6 Z; R
1245363 CONCEPT_HDL CORE Design Entry HDL program crashes upon save9 h# A+ {" I: S, \9 Y& ?
1245790 ALLEGRO_EDITOR PADS_IN Bug: PADS Translation with 16.6s023 gives parse error, @- n3 L9 W c" j( V
1246343 ALLEGRO_EDITOR SKILL axlAirGap command is broken in s022
5 c- m& a( E+ u8 O. o1246419 CONSTRAINT_MGR OTHER Netrev fails with SPMHGE-268 on existing design( i" q# m5 s' u k& O$ g, n! c
1246878 CONCEPT_HDL CORE Changing Symbol in Variant Editor makes schematic page crash
( k& K2 R4 ^( K" r/ r0 h/ M) U& a p1246884 ALLEGRO_EDITOR GRAPHICS Infinite cursor disappears from the canvas after step package mapping GUI is closed.1 m" K" k$ u K
1247016 ALLEGRO_EDITOR INTERFACES STEP Model of connector cannot be zoomed sufficiently after mapping it to symbol dra file.2 z6 m; ]- s5 M! Y/ ]
1247107 ALLEGRO_EDITOR INTERFACES Incorrect Spelling in IPC-2581 EntryFillDesc field. M, X& S7 P; V
1247177 SIP_LAYOUT WIREBOND Bondfingers not aligning to wire when tack point on the other wire end is moved from center
& T* Z7 S/ I) A i! K4 K( u1247400 ALLEGRO_EDITOR INTERFACES option to Export optimized PDF in color
: G. Q* ~- Q9 z0 S1 r y
1 X" R4 C; ~. H/ L: O7 C% wDATE: 02-28-2014 HOTFIX VERSION: 024
$ l" d6 k4 n( g7 R+ g# `===================================================================================================================================4 M) Q6 H1 \5 C" `' r2 {8 m Z
CCRID PRODUCT PRODUCTLEVEL2 TITLE9 _; A( q& z H9 }3 o
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1207753 CONCEPT_HDL OTHER The Variant Name with a dash is represented by #2d
2 c) F! c2 O' C' |& w1234991 ADW TDA Team Design does not remove deleted page files from zip files
* m" X# j/ V* ] ?3 Z1235919 CONCEPT_HDL PDF DNI crosses are not printed on the correct components: S+ [5 @0 \4 m5 F
1238007 ALLEGRO_EDITOR PARTITION Import partition removes properties from RKO that were on the exported partition& h( U7 r" I8 i; ]+ z: ~
1238140 CONCEPT_HDL CORE Design Entry HDL Crashing
6 T7 _5 K$ q1 u5 I0 d0 b) f1238195 ALLEGRO_EDITOR DATABASE Via's losing net idenity after being mofifed or replaced.; C8 m4 G' H \/ _9 Q- l; y1 y
1238478 ALLEGRO_EDITOR ARTWORK IPC-2581 negative artwork layers does not recognize shape bounding box value. D, d; p/ r7 ~- y# W5 @7 {
1238483 ALLEGRO_EDITOR ARTWORK IPC-2581 not drawing negative artwork correctly with traces in voids.
3 F' o2 M: F2 E: K! e) r1239070 SIP_LAYOUT WIREBOND When importing wirebond data onto a Die rotated 90 degrees the WB data is placed in the wrong locations
, V9 q2 k5 ?. L8 Y1 d9 ]1239433 SIP_LAYOUT WIREBOND Need the Wirebonds to lock to the die aftter importing wirebond data
u! G$ M Z& y, Y& c+ q" I+ b' H1239952 ALLEGRO_EDITOR SYMBOL Allegro crashes with a component rotation of 45 or 135., I* s) \4 v5 N( T ]0 U
1240205 SIP_LAYOUT DIE_EDITOR Crash occurs when trying to "oops" for a moved driver in co-design die editor in SiP
( M; Z/ a' ~1 m" ?5 l1240288 ALLEGRO_EDITOR INTERFACES Why are some of the mechanical holes not showing up in Step output of thi design, while others are ?
. ]0 l+ |. E% ]: m7 U1240305 ALLEGRO_EDITOR INTERFACES STEP Export gives some errors which are not documented/ Y# r) s4 [! K! g! A% P* d& K
1240425 ALLEGRO_EDITOR DATABASE Export ODB is not working on 16.6 HF 22
; S, m. ^ K. }4 Y; S* G* g1240879 ALLEGRO_EDITOR NC NC ROUTE file is not correct using hot fix 22 of v166
$ m5 z. ^, g+ p! T/ c- H3 ~1241904 ALLEGRO_EDITOR INTERFACES IDX baseline import displays false DRC with Package_height Offset until DRC update is run.& ], N- }4 h7 S e. g
1242266 ALLEGRO_EDITOR INTERFACES IPC2581 crash on HF22 and HF23
/ s5 B3 x: z y4 ?: M3 y0 d/ O1242433 ALLEGRO_EDITOR INTERFACES ipc-2581B incorrect LayerRef values in BOTTOM side RefDes elements
- A9 Y1 }% a6 d, a7 L n1242988 ALLEGRO_EDITOR SKILL Allegro crashes on skill command axlDesignFlip
! a( |" O# Z9 m5 ~- n/ V% [' l4 ?1243845 FSP FPGA_SUPPORT FSP design created in 16.6 s018 will not open in 16.6 s021
0 `' ^2 u% E! W5 R, T) b. j
" P+ T. c' F, W! X7 K' M5 yDATE: 02-14-2014 HOTFIX VERSION: 023
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.6 D ]) Y7 h: R4 H0 H. o. Z4 G. H
1202715 SPIF OTHER Objects loose module group attribute after Specctra. v1 J# g. @4 N4 ^
1203443 ADW LRM LRM takes a long time to launch for the first time* W/ q' k& Z" @6 B
1207204 CONCEPT_HDL CORE schematic tool crashed during save all3 E! _# I& [7 ]" q' \' `
1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter
1 T7 n; L: s1 Q8 Q1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA
& Q8 n8 C1 J! k( t# B1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side
* G! ^& Y. u6 F) w) c# i& c1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr
: v/ i5 \7 o( {# j, w- ~1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.
9 ]. ~' S0 s x3 X4 K5 w1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
, m) f3 `: Z0 |7 x6 K5 j4 `6 T: ^' T1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.) G! s& e- g: H) g" y
1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7
6 c) c' k$ h% F9 i1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's; o9 O3 O$ c5 A8 ~" `
1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.) s+ D( Q1 u( H' l5 u9 i
1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes! d/ H$ ?2 Q0 }7 Z+ g; k6 q R! b
1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form |8 ^7 q- k3 L5 u
1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
4 t8 W4 L, u- g$ U/ [1 I1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX% n8 g8 q. L8 s7 @5 _
1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.8 ]* }3 B5 ^# Z
1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.% U# }8 |, A0 T: U. N7 w
1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
]4 S" v- Z0 ~% v5 N2 h+ S4 D1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues
7 C, F: q4 Z6 v' M( [0 X e1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File
- [" c6 v8 |: S6 Y$ k1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat
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0 h z+ X; {# M0 C) B TDATE: 02-7-2014 HOTFIX VERSION: 022
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===================================================================================================================================
8 f# P% o& m$ ]1 R192358 ALLEGRO_EDITOR PADS_IN Pad_in does not translate some copper shapes3 [! ]$ J) @9 _! z
222141 ALLEGRO_EDITOR PADS_IN PADS_IN: Extra shapes are created when importing PADS design
3 Q z9 x$ t6 o274314 ALLEGRO_EDITOR PADS_IN PAD_in boundary defined for flooded area be translated DYN
+ x! k: P B' J) Z( a3 P413919 ALLEGRO_EDITOR PADS_IN pads_in cannot import width of refdes.) p! `2 X7 p( Y. T' c! b
609053 ALLEGRO_EDITOR PADS_IN "Mils to oversize" of "pads in" did not work correctly for MM data.
y& D% s4 Q( N+ c9 L* E8 b666214 CONCEPT_HDL OTHER Option to increase Line thickness in publishpdf utility- q/ d1 q! X1 \: y4 m2 `: f
738482 ALLEGRO_EDITOR GRAPHICS Export image creates black image with Nvidia GeForce 8400M GS Graphics card6 k G' n0 X" F7 I- \( u( E
982950 CONCEPT_HDL OTHER change the mouse button for the stroke to have same function with in pcb editor
: b( t% ~3 x5 F" d. ]4 b1020886 SIP_LAYOUT LEFDEF_IF a quicker way to promote die pins (by importing macro_pin list), z5 S: X( J( w( K8 G+ A! h
1032678 CIS VIEW_DATABASE_PA View Database Part gives incorrect result in complex design with variants.
1 D; A$ B _+ _/ C* `1033864 ALLEGRO_EDITOR PADS_IN pads_in doesnot translates teardrops present in design% X4 k: ~" h' `6 Y. Q$ l
1054862 CONCEPT_HDL OTHER Option to increase Line thickness in publishpdf utility, ?$ S& W* z! N" ~7 \8 [6 t5 a
1055252 FSP PROCESS Add a synthesis option to target a group to contiguous or consecutive banks! Y! Q' T9 u* R
1100772 CONSTRAINT_MGR OTHER In Constraint Manager > DRC > Spacing the Show Element DRC totals are wrong.
- S# Q% ?) y2 {$ n$ `1135020 CIS DESIGN_VARIANT Variant list is showing wrong results for hierarchical designs
. X n3 h! W9 c9 _1138951 SIP_LAYOUT DIE_ABSTRACT_IF Fix die abstract r/w to properly support pinnumbers on ports! o; u% K7 H) a. g
1140042 CONSTRAINT_MGR OTHER Diff_Pair lengths and analysis are lost after closing and opening Constraint Manager.
0 V' |- B: n- _* {1143662 ALLEGRO_EDITOR INTERACTIV Enhancement Request for RMB - Snap Pick to options increased to include Pin edge
. ^' n% i1 e5 l5 F+ ]1147961 PSPICE SIMULATOR Simulation produces no output data
+ c/ I& `" S" p1 K1150874 ALLEGRO_EDITOR PADS_IN Dimensions in PADS are not translated correctly during pads_in translation
8 U& a/ _* g0 |9 T1154184 CONSTRAINT_MGR CONCEPT_HDL Difference in the way topology is extracted in 16.3 versus 16.6: v" D, q8 C4 j; q$ @: y
1154770 CAPTURE PROPERTY_EDITOR Variant Name property doesn't show value in Variant View mode8 ^3 z7 x/ ]( [! i, Q
1158350 CONCEPT_HDL CORE Need a warning Message while importing a 16.3 sub-design in a 16.6 Design3 y! D4 s# \% d5 _8 O$ J
1162347 ALLEGRO_EDITOR EDIT_ETCH Enh- Allow new option in Move command such that it allows stretching etch using only 45/90 degree segments directly
6 |+ y4 s% K. z3 @+ @2 x' y! P1165553 ALLEGRO_EDITOR INTERACTIV Subclass list invoked from the status window does not represent correct colors.) ?8 q) P) Y* c- V! K, D
1168079 FSP MODEL_EDITOR Clicking OK or Save As in rules editor allows user to overwrite the master with no warning2 `4 l6 Y6 V0 G" w& W
1172043 SCM OTHER : in pin name causes SCM to crash- b p& l+ W: x" s6 l4 x7 r& O
1172207 CAPTURE STABILITY Capture crash while adding new part from Spreadsheet5 d8 D: L" `1 s5 X S+ n6 l
1172743 ADW TDA Allowed character set for the check-in comments is too limited9 X" C+ U r- z: J; _
1174099 SIP_LAYOUT WIREBOND Option to reconnect wire based on 縫in name� in the Wire Bond Replace
' @$ m( Y- i8 G5 U, ?2 X1177672 APD IMPORT_DATA Netlist-in wizard didn縯 provide detail information about what columns have been ignored by import process
1 |& _: n( _4 h' b1 c& ?& b4 m1177714 CONCEPT_HDL RF_LAYOUT_DRIVEN RF component's LOCATION property can not be set to invisible
: V* P7 h5 f1 t4 }( I- O* B3 D1177820 CONSTRAINT_MGR INTERACTIV Done the Allegro command when attempting to launch CM; Q5 Q: r0 a: j8 [/ E
1178586 ALLEGRO_EDITOR EDIT_SHAPE Number of digits displayed after the decimal point of Shape Creation function does not match the Accuracy of BRD A1 o6 t$ P- o& x9 s
1179688 PSPICE STABILITY pspice crash for particular HOME variable vlaue
, a- ^- M2 t! Z" k" Q" V& q9 U1179827 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to Symbol export - enable field to add Keywords for data fields to excell cells& W1 U& a' a+ E- `
1179879 SIP_LAYOUT STREAM_IF Data file corrupt when exporting Stream data from SiP database.2 C% l1 k8 U: Y" o
1180164 F2B BOM BOM csv data format converts to excel formats, |- v& S0 T: }3 C2 d
1180477 ALLEGRO_EDITOR INTERFACES IPC-356 output is listing a duplicate location in the comment section
# i$ q0 G K# O. _1180932 SIP_LAYOUT OTHER SiP Layout - Symbol to Spreadsheet add option for writing to existing spreadsheet
+ {. J0 k8 b. U- S8 k1181377 ALLEGRO_EDITOR INTERACTIV Pick Releative does not work correctly with RMB-Move Vertex2 N3 } D- z% _- B0 C/ ]
1181516 ALLEGRO_EDITOR DRC_CONSTR Getting a "Thru Pin to Route Keepout Spacing" when there should not be one.
# U8 R3 W0 [+ ?0 i+ b1181739 GRE CORE Running Plan > Spatial crashes GRE
; N- L; n0 Q+ ]9 {! ?1181935 ALLEGRO_EDITOR DATABASE Enh. Property that allows internal C-C DRC errors8 U( j; p n5 T' J* ~' T3 P
1182185 SIP_LAYOUT OTHER SiP Layout - Import symbol spreadsheet - suppress Family for the font in the XML spreadsheet( e. B* ]2 P5 x m+ t* D
1182566 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to symbol - Enhance ability of spreadsheet exchange to allow for a portion of a full pin map
. T8 m: g5 w* c' D1182599 CONSTRAINT_MGR DATABASE CM Prop Delay Actuals do not update after Z Axis option is turned ON or OFF and Analyze is run.
" S) h# }' Y9 j% p1182892 CAPTURE SCHEMATIC_EDITOR Pspice marker rotation before placement y, q, X1 z; {
1183682 ALLEGRO_EDITOR DRC_CONSTR Implement Nodrc_Sym_Pin_Soldermask & Nodrc_Sym_Pin_Pastemask to symbol level
1 q; s/ f7 O: y% j1185445 SIP_LAYOUT DIE_ABSTRACT_IF Die abstract export needs to be able to select xda file type when browsing
2 X3 R8 {: _& r1 n! O1185932 ALLEGRO_EDITOR SHAPE Soldermask in solder mask void DRC
0 ^/ k6 l% v: A! X6 G5 R! T, b/ U& r1185946 CONCEPT_HDL CORE Ericsson perfomance testing report 5 sept 20135 s' A9 |8 H5 c8 a ^: S0 B1 P
1187213 FLOWS PROJMGR Unable to lock the directive: backannotate_forward3 X! J8 {* D) g' Y
1187444 ALLEGRO_EDITOR DRC_CONSTR With this design Database check prompts error "SPMHGE-47: Error in call to batch DRC"1 V/ u$ g% U, M+ f% V
1187597 ALLEGRO_EDITOR DRC_CONSTR No Package to Package Spacing DRC error, when symbol overlap sideways at 45 degree.9 C; r D" A. z) @# j. H% J5 t
1187723 FSP PROCESS Synthesis can fail depending on component placement8 S" F. F6 [( @# H, v
1188164 SIP_LAYOUT OTHER SiP Layout - Spreadsheet interfaces Import Export and Add Component - include Keyword for NET_GROUP
0 j0 }7 E' A2 b. x+ H/ h$ c1188245 CONCEPT_HDL CORE INFO(SPCOCN-2055): You cannot run the CHANGE command in a read only schematic* H. k. N' z \ I+ l4 I4 V
1190927 CONCEPT_HDL CORE Check sheet does not report shorted signal/power nets if power symbol is connected to a pin
; K' O* J# q* J: N9 C; o; \% e1191497 ALLEGRO_EDITOR INTERACTIV ENH: Adding names to the text block parameters numbers
; N4 f) o) y1 a4 ^1192005 SIP_LAYOUT IMPORT_DATA Import SPD2 is missing 1 smart metal shape from file
* N+ W5 k2 _4 {1192204 ALLEGRO_EDITOR EXTRACT Need ability to extract vias that are labeled as microvia
1 B# J2 i5 U+ T7 p: Y5 V9 @$ M0 f1193063 ALLEGRO_EDITOR MANUFACT TestPrep log displays "Pin is not accessible from bottom". The component is through hole.
" }; X( _3 \* D) t! B6 f) R; A1193418 ALLEGRO_EDITOR GRAPHICS 3D Viewer can`t export image in both SPB166S015 and SPB165S047
" D& l3 k% N5 \* k1 Q' D& v1194305 SIP_LAYOUT EXPORT_DATA export package overlay creates file with no package info
& P. B& ^/ }$ A* U; J) E1194418 APD IMPORT_DATA issue when do File->import->netlist-in wizard1 s+ P7 h% [' `
1195279 F2B PACKAGERXL Ptf files are not being read when packaging with Cache' B3 E# d4 [, X4 v- ^" v& i/ d
1195374 ALLEGRO_EDITOR INTERACTIV Modules are not showing up in Tools > Module reports
* D( ?# M6 S# U; `) @' {! v1196603 SIP_LAYOUT EXPORT_DATA Change form for "Write Package Overlay..." to better support longer lists of routing layers
/ z, ^; H" L+ ?* F$ `( c" M* v# y1197302 CONSTRAINT_MGR UI_FORMS Inconsistancy in selection of object for Spacing Constraint Worksheet* p/ `% |' j" B* l1 n# w
1197399 CAPTURE OTHER Draw toolbar disappears when using Print Preview( u2 u5 |! N) \$ W& I
1197543 ADW TDA TDO does not correctly show deleted pages
/ y9 i% y, B1 @% |6 _7 X1198033 CONCEPT_HDL CORE Signals do not get highlighted when Show Physical Net Name is option enabled
3 h5 z: K' Z2 S7 ~1198468 ALLEGRO_EDITOR GRAPHICS 3D_step model does not show the correct view in 3D_Viewer when symbols have multiple place_bounds.
4 w D6 X& F0 H0 q. j1198617 CIS GEN_BOM Mech parts are showing with Part reference in CIS BOM
( n; Z- \7 K$ h' |* V- x1199764 ALLEGRO_EDITOR SHAPE Allegro crashes when trying to delete small island on POWER layer.$ V# h9 y( `' a1 J
1200232 ALLEGRO_EDITOR INTERACTIV Moving all items including board outline which is made of lines does not move the board outline in General Edit Mode.
5 ?: ]; G8 [- N; z/ A3 T1200748 ALLEGRO_EDITOR INTERACTIV Additional pin edge vertex object to snap pick
0 {1 T# ^5 B: a! E8 C1201056 ALLEGRO_EDITOR DATABASE Unsupported functionality strip design creates a .SAV file
) Y j" N- U( A1 n/ m7 v1201638 CIS PART_MANAGER Part retains previous linking inside the subgroup
" |" U5 j$ V6 m/ m1201834 ALLEGRO_EDITOR PLOTTING Bug: Import Logo command changes resulting imported object: H" F0 T! }$ ^
1202406 SIP_LAYOUT OTHER enable the dynamic display of component pin names for co-design dies in Sip Layout
7 [* _- l: A; C ~; V+ L1202431 CONCEPT_HDL PDF The publishpdf -variant option should have a "no graphics" option: j% L, ~ ?: L+ b$ O, x
1202717 ALLEGRO_EDITOR DATABASE About Warning(SPMHA1-108):Illegal line segment ... end points.1 I( ?; _, w( w7 B& R4 e4 ]* b6 {
1203459 CONSTRAINT_MGR INTERACTIV Object Report has no mechanism to output information for a specific design.
8 X, M ~$ j$ L6 [( e! C9 F+ [1204544 F2B DESIGNVARI Variant Editor does not warn on save if no write permissions are on the file7 Z; a7 L0 v( I5 ^7 b$ e7 `* X
1205500 FSP CONSTRAINTS MAPP FSP FPGA port mapping VHDL syntax
6 n O. _" S3 ?8 F* h3 Z7 N1205952 ALLEGRO_EDITOR GRAPHICS Step Model for Mechanical Part is visible in 3D viewer only when Etch Top Subclass is enabled% ^& w0 X5 H3 P1 [- ?
1206103 SIP_LAYOUT IC_IO_EDITING add port name property to pins, and add Skill access I/O driver cell data
$ w" C4 Q/ ~8 G9 r1206546 CAPTURE ANNOTATE User assigned refdes are resetting when 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom�- G3 u4 d( s4 y/ m; N
1206561 ALLEGRO_EDITOR GRAPHICS Not all mechanical symbols made with Step files are displayed in the 3D View2 S& B4 S7 G/ u, X- i2 `
1207125 SIG_INTEGRITY ASSIGN_TOPOLOGY ECSet mapping wrong for 2 bit in a 4bit bus* R; A$ A3 W6 P& N) a4 L% W$ g
1207386 CAPTURE GENERATE_PART Altera pin file not generating the part properly m; o; r7 F, D% ~# A
1207629 CAPTURE TCL_INTERFACE Bug: GetMACAddresses tcl command not working1 |8 U# h; z8 R& n
1207994 CAPTURE TCL_INTERFACE TCL pdf export in 16.6 fills DOT type pins with black color
' p- j, w0 R& p; u7 U- e1208017 F2B DESIGNVARI sch name is not same when updating Schematic View while backannotating Variant; X. g8 n& x3 O% H
1209363 ALLEGRO_EDITOR INTERFACES When placing pins using the polar command the tool returns 4500.00 for 45 degrees.9 L' Q% t$ f7 w/ X
1209769 CONCEPT_HDL CORE Top DCF gate information missing" \; n* N3 \% S8 F3 ~
1210194 CONCEPT_HDL CONSTRAINT_MGR HDL crashes with Edit Via List dialog box
; m& ?0 u4 L! k# D9 j- T+ Z- u' ~1210442 CONCEPT_HDL INFRA Save design gives ERROR(SPCOCN-1995): Non synchronized constraint property found in schematic page
6 J- j5 V: ^. O a; N, A1210685 ASI_PI GUI User can't edit padstack in PowerDC-lite
; l) G6 `3 g( @5 K x! }6 _) C1210744 SIG_INTEGRITY SIGWAVE SigWave: FFT Mode Display unit seems not to be correct
9 z2 D3 F( K1 q1210829 CAPTURE NETLIST_VERILOG Shorted port is missing from verilog file/ M2 E- V0 ^; Z" U; n Q
1210850 CONCEPT_HDL CORE DE-HDL backannotation crashing after instantiating specific cell from Ericsson BPc Library
$ @8 C/ E! r9 \( n% |0 L1211620 ADW COMPONENT_BROWSE Component Browser Performance
6 L7 e6 E5 u" `1 }7 U9 q8 w1212102 ALLEGRO_EDITOR INTERACTIV Shape edit boundary adds arc mirrored to the highlighted preview." d: q0 E Z" a; a6 G
1213294 CONCEPT_HDL SECTION DE-HDL windows mode multiple section fails to section first contactor pin from column of individual pins
6 `6 C% \* ^2 I3 |% Z1213402 APD DATABASE The old "ix 0 0" fix is now causing the features to lose nets entirely.8 A" d$ y7 Z! L5 r
1213694 ALLEGRO_EDITOR PARTITION Via connected to Dummy Net pin in Partition gets connected to shape on the board after importing partition/ D* \# N U3 G. V; x: `
1214247 CONSTRAINT_MGR UI_FORMS Selecting the "All" folder in Spacing Constraints in CM does not automatically select the first column for editing* x! R a$ p; u9 k& R5 s; Z
1214320 SIG_INTEGRITY SIGNOISE signoise command with -L and -k option
/ i/ c8 q7 r/ x# L8 y V7 ]0 H1214433 CONCEPT_HDL CORE Genview does not update sym_1 with ports added to the schematic
* @' q" ^) g* A2 ]$ P: w# I2 z9 g1214909 ALLEGRO_EDITOR NC NC Drill Legend show extra rows for drills. B+ I( P1 N. i# G5 ^
1214916 SIP_LAYOUT OTHER package design integrity check for via-pin alignment with fix enabled hangs
) q8 e6 w, b' a* H- e& l& O" E6 m6 F1215954 SIG_INTEGRITY SIMULATION Cycle.msm does not exist error when simulating extracted net
A' ^* k- @$ Z0 y1216328 CAPTURE STABILITY Capture crash6 O# c, Y$ e1 \" |
1216993 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crash on SPB16.50.049: F9 l$ J S8 I+ E( t
1217450 F2B BOM ERROR 233: Output file path does not exist
6 k1 x% b1 q9 \' ^1217612 ALLEGRO_EDITOR INTERACTIV Replace padstack will not replace padstacks that have multiple alphabetic characters in the pin name - AB21-AB373 ? z$ [$ |' L
1217823 ALLEGRO_EDITOR INTERACTIV Compose shape fails with SPMHIS-473
7 X" S% |; }9 P4 Y, \% J" o2 ]6 H1217887 ALLEGRO_EDITOR INTERFACES An undo option to be made available in the STEP Package Mapping window
2 @5 G$ f4 Y1 K# v2 y1218665 ALLEGRO_EDITOR INTERFACES In step viewer, the bottom side parts are placed above the pcb board surface8 k8 c/ N& I& b) {* e2 e, s
1219053 PSPICE PROBE PSpice crash with the attached Design. U$ g7 _+ X* d0 T! ?
1219067 ALLEGRO_EDITOR EDIT_ETCH dynamic fillets behavior is unstable5 G9 A! m9 ~' ^: V3 R! X
1219095 ALLEGRO_EDITOR MANUFACT Design Cross section chart is tapered for two layer board' l" Q7 U* O8 v! }3 x+ |& g
1219126 ALLEGRO_EDITOR SKILL Skill issue with axlRefreshSymbol()
% _: f; m6 B9 V- C% ]# n) j: q1220701 ALLEGRO_EDITOR INTERACTIV View > Windows > Worldview (showhide view command) fails with command not found4 g& f4 z' ?, Z& H3 Q' _- M& R+ }
1221057 ALLEGRO_EDITOR REPORTS Units in Cross section report for spacing is not synced with the design
& V( r9 F7 _7 ?* {& d# W# M1221139 ALLEGRO_EDITOR EDIT_ETCH Delay tune is not tuning differential pair
+ \ `7 K8 \+ ^' Q1221157 SIP_LAYOUT IMPORT_DATA import spd2/na2 file is not importing data correctly into sip
( p7 K6 g" C+ N- ~1221163 SIG_INTEGRITY GEOMETRY_EXTRACT Simulation aborts with severe convergence issue when coupled vias is enabled.
) g# k& L5 I2 w/ X1221416 ALLEGRO_EDITOR DATABASE strip design for function type
6 O+ G1 w: p4 B1 Y N. Y; E1221931 ALLEGRO_EDITOR DATABASE Fatal software error when embedding component
+ V- i' a' m2 Z4 i* p+ d$ P1222105 CONCEPT_HDL CORE Moving Pins around the edge of a Block causes the text of the pin to change its text size.
$ T/ M4 ^; O2 ?7 T: v1222124 APD DATABASE Same Net DRC's exhibiting inconsistent behavior.5 ^3 B7 z: M* X. D+ c" k
1222272 SIG_EXPLORER EXTRACTTOP Cannot extract net or open SigXplorer after selecting a netgroup
+ E) o8 ?/ Y! q* d/ W8 \! l! Z e1222329 ALLEGRO_EDITOR SHAPE STEP-Model Symbol which has place bound bottom is on Top( z% |- @5 X7 Z" h
1223183 SIP_LAYOUT BGA_GENERATOR Getting an incorrect error message when using the BGA generator with a long BGA name.! a0 R, B# M. y! }( q3 m3 h9 S
1223662 ALLEGRO_EDITOR REFRESH Allegro crashes when trying to refresh symbol
# s$ M' ]; ?/ ?$ e" h4 n- g1223932 CONCEPT_HDL CORE DEHDL block desend does not find 1st page if its not page1/ X& t8 h Y. N) U
1223940 CONSTRAINT_MGR UI_FORMS Unable to change CLOCK name in Setup/Hold Worksheet under Timing in CM.
9 c5 K* g. T% M* c1224127 SIG_INTEGRITY IRDROP Is the old static IRDrop in 16.6 officially supported?
, A2 L ]* @: m1225492 PCB_LIBRARIAN CORE PDV expand vector pins resizes symbol outline to maximum height again
0 o' q! P7 |# u$ \0 G& X1225546 CONSTRAINT_MGR ECS_APPLY nets where the referenced ECS maps correctly in constraints manager for front end but not in back end
: F" m+ `9 j! ~, x+ L1226405 ALLEGRO_EDITOR INTERFACES File > Export > IDF ask for filter config file eventhough it is created in same session and stored in parent folder
& l2 t( B0 I5 f! w1226448 PDN_ANALYSIS PCB_STATICIRDROP License failure about PDN Analysis with XL and GXL% i7 o: A! x* m) O& D
1228721 SIP_LAYOUT OTHER File Export Netlist Spreadsheet enhance sort to be a natural method per Jedec according to customer
. z% g8 m: E, R, w/ x% x U7 V3 U0 b4 f- ^. H+ M; `5 O
DATE: 12-20-2013 HOTFIX VERSION: 021; y0 `4 B7 f" Z/ [
===================================================================================================================================
+ b0 p' @4 O# d/ KCCRID PRODUCT PRODUCTLEVEL2 TITLE
3 M) G6 l" E2 y F===================================================================================================================================
. Z$ `6 V. t4 _# b1214932 ALLEGRO_EDITOR OTHER Allegro will crash when performing show dimension on linear dimensions., A. X' A$ K' Q' d" M
1215045 ALLEGRO_EDITOR SKILL Successive file open / ipc calls crashes Allegro 16.6' g/ Y3 S& @+ c- p* V9 \
1215115 ALLEGRO_EDITOR NC drawing name doesn't display in the ncdrill.log file* Y/ L( C* {4 r6 ^( Z& F1 T
1216028 SIP_LAYOUT PLACEMENT Design will not update embedded component symbols.
- l9 y2 K7 E1 T0 C- {9 R5 {: S6 q7 \1218451 ALLEGRO_EDITOR DRC_CONSTR Route Keepout to Pin DRC created even after adding Void in RKO shape
5 i* R- b6 y0 j7 n! u1218636 ALLEGRO_EDITOR SCHEM_FTB netin process will rotate embedded symbols( d, O5 r7 w& p4 h5 [# {5 e
1218706 CONSTRAINT_MGR CONCEPT_HDL NCC associations get deleted from FE CM
" N) D/ w% f9 F" v$ ]3 |9 U8 ?, o5 S2 B @
DATE: 12-4-2013 HOTFIX VERSION: 020# A6 ~0 ~: I; u9 I! m4 \
===================================================================================================================================
2 C* @" {% w, o$ [' b k5 e/ MCCRID PRODUCT PRODUCTLEVEL2 TITLE2 a0 P, y$ P( e+ I2 L0 ]- G& `
=================================================================================================================================== p5 z; A6 Q! M7 c! I1 i
1116426 F2B PACKAGERXL Packaging in 16.6 increased by 3 folds compared to 16.3; ^; c9 H0 j- @( f8 f
1190095 CONCEPT_HDL CORE In Windows mode select the part and click on version placed selected version +1." n8 \8 s4 _5 D( F; i
1199410 CONSTRAINT_MGR CONCEPT_HDL Constraint Differences Report window hangs in 16.6-s016
" p# l, u: h! r- J$ E A1 b1199425 CONSTRAINT_MGR CONCEPT_HDL Import Physical fails (the cmfeeback.exe has stopped working) in 16.6-s016' q0 I. z/ ]. s; M6 ?
1199700 PSPICE NETLISTER Netlist fails on addition of netgroup
O- w1 c, k |8 S9 A" `$ H1200936 CONCEPT_HDL PDF publishpdf fails if UNC paths are provided from the command line
6 ?5 v2 |# ^- g, J: m1202391 CONSTRAINT_MGR OTHER Getting 'An Invalid argument was encountered' when generating Net Class-Class report in CM
7 i& ?1 u6 C. S% D$ w9 p! o: @1202587 CONCEPT_HDL CREFER Crefer schematic reports cannot be deleted on Linux.! Q. r/ v; } D* x5 q2 c% M
1203143 GRE CORE GRE crashes on running Plan > Spatial7 i6 ^. ]7 v% e/ Z) X
1206019 ALLEGRO_EDITOR INTERACTIV Allegro needs to be restrated to read steppath with 16.6 S017& `5 \4 K' P4 y7 a4 f" a6 ]
1207050 ALLEGRO_EDITOR INTERACTIV Refresh Padstack fails on Warning2 I0 u2 n _- A
1207178 CONCEPT_HDL CORE Aqua color on wire does not matches icon color
2 Q3 y- K! a2 k) V- @1208152 F2B DESIGNASSC ERROR: Dictionary File: cmdict.l could not be found
5 m n r; K* k* q* I: F9 W q1208276 APD STREAM_IF Stream in fails to import what Allegro exported& m1 q+ q y( E& H3 ]
1208345 ALLEGRO_EDITOR SKILL Why axlChangeLayer not working for shapes on this attached skill file?* ~" r' p- `3 Z
1208351 ALLEGRO_EDITOR SKILL axlFilmCreate do not define the IPC2581 domain correctly.8 t, r, l+ }: x D. H; ~9 s
1208467 PCB_LIBRARIAN VERIFICATION con2con mangles cell data after checking cell having syntax errors on part_table
$ J% P. _! V7 o' p E1208579 SIG_INTEGRITY GEOMETRY_EXTRACT Incorrect traces are extracted when void area is less than anl_min_void_area setting
5 C* V$ C& L! ]- O1209347 ALLEGRO_EDITOR PARTITION Import partition that has diametral dimensions will crash Allegro
0 R: G k& |6 C Q; r# m1209897 ALLEGRO_EDITOR PADS_IN Pads_in will not translate design.
* U7 }) d7 W) U1209902 PCB_LIBRARIAN CORE PDV crashes reading part6 x6 [) X0 C- G3 v
1210183 PSPICE SIMULATOR SimSrvr crash with ORPROBE-3211 RPC Server unavailable Message# w5 F6 m: \. \6 W( H
1210408 ALLEGRO_EDITOR EDIT_ETCH AiBT hangs when doing interactive breakout on bundles using latest hotfix.. n7 B- E' E+ @6 c/ ]# ^& R0 V0 C
1210443 ALLEGRO_EDITOR INTERFACES Allegro Design Publisher does not create fully searchable PDF for some of the text that are present or certain layers
# S( e9 c& l$ f- [2 W9 H8 E1 g1210876 CONCEPT_HDL ARCHIVER Archiver wrongfully deletes directories.3 ?8 Y1 d. g! P
1211839 CONSTRAINT_MGR DATABASE Topology can't be extracted correctly.. q4 S/ r1 H5 ~5 }" w- ^4 Z
1212709 ALLEGRO_EDITOR DATABASE No connect can`t be detected in SPB165S048
4 z) @: W' Y9 h: Y6 S& |5 X$ Z0 F) Y1213752 CONSTRAINT_MGR OTHER "Show Constraint Difference Report" option at File > Import > Logic does not retain the last setting
: K# `5 |4 B9 {& z
& G" m: f0 @8 p: uDATE: 11-15-2013 HOTFIX VERSION: 0197 N5 \4 j( ]" x+ u, |) R4 k& g* u
===================================================================================================================================; x J, }( _/ N+ P
CCRID PRODUCT PRODUCTLEVEL2 TITLE1 n5 O3 N! t- L. H# P. l
===================================================================================================================================4 Z4 y( s, i, c' E$ A% Q
1176155 CONCEPT_HDL CORE Graphics remnants with 16.6 QIR 3
8 m3 W& o& U2 Y# K1178272 CONCEPT_HDL OTHER Verilog netlist does not include split blocks correctly( k7 m) F. g+ E) B: h
1190782 FSP FPGA_SUPPORT Support for Altera > 5SGXEA9N2F45 device.& a% X& ~# [/ L/ m- ^4 K$ L
1194140 ADW LRM SYNC_PROPERTIES is not resolving issues a based sync_properties settings+ @6 @/ ^. I5 j6 f8 b1 k
1195744 APD EDIT_ETCH Diff_Pair routing fails on certain Uvias in the pair.: o( R0 m9 {0 y, Q1 W* N3 A
1196704 ALLEGRO_EDITOR INTERFACES ENH: During ipc2581 export checkboxes corresponding to 縈iscellaneous Image Layers� should automatically get selected
/ g7 B% {' X B6 L4 J2 j( |- t/ k1198340 ALLEGRO_EDITOR OTHER Multiple -product option on the Allegro command line does not access the second -product; y( d: |* u) i6 M
1198596 ALLEGRO_EDITOR INTERFACES When copper thickness is increased for the outer layers, step Viewer does not show correct component position.+ l$ s M# }. Y" _5 O
1199673 PCB_LIBRARIAN OTHER Component Browser fails to load footrpints if they are set with UNC path
* l Y$ l8 e/ Y# C1199889 ALLEGRO_EDITOR DATABASE Allegro crashing with latest hotfix.
* Q9 y# k- u5 i9 l$ ?$ p1200303 ALLEGRO_EDITOR GRAPHICS 3D Viewer does not update after changing STEP model mapping# D9 E" c" Z% m: a+ \3 O& @
1200449 ALLEGRO_EDITOR REPORTS Allegro crashes when generating Net Loop Report.5 `* r5 C) r2 B1 v/ ]
1200915 ALLEGRO_EDITOR DATABASE Reducing accuracy of this specific design crashes Allegro
3 ^# y% |: h6 S1 X1201011 ADW COMPONENT_BROWSE Component Browser crashes in DB mode" C3 s( I9 s9 `7 B0 H
1201376 ALLEGRO_EDITOR INTERFACES Allegro hangs when trying to map a specific STEP model to a package drawing.
) X- s/ ^, I( ^# o/ e/ O, g7 z+ V1201897 SIP_LAYOUT IMPORT_DATA BGA Pin Colors not matching the Colors defined in the Symbol Spreadsheet after updating.
$ I! {2 H; p" B' N* C6 |1202709 ALLEGRO_EDITOR INTERFACES STEP File generated from Allegro is not overwritten when the variable "set ads_textrevs. m% n' x e5 Q" o9 e# \
1202820 ALLEGRO_EDITOR INTERFACES Different xml generation for same step model on S106 and S017
# ]/ V3 o3 z, U; x1 _6 ?1202842 ALLEGRO_EDITOR INTERFACES Step model invisible for one pin dra in allegro 16.6 symbol editor, T3 q8 i6 o* h" o4 |6 V6 e- n
1202983 ALLEGRO_EDITOR SHAPE Shape voiding creates DRC with Route Keepout
) O$ H4 \- |- |1203125 ALLEGRO_EDITOR OTHER Exporting STEP file with External copper enabled does not show all copper when viewed with Solid Edge or Inventor
9 r* _4 ?3 I8 h6 I- a- v+ m0 m7 R, \2 `1203236 ALLEGRO_EDITOR INTERFACES IPC2581 output with crosshatched shape is not correct
, j) {, a+ Z: y/ A" t1203995 CONCEPT_HDL CHECKPLUS CheckPlus rule, local_signal_no_offpage_body, getting an incorrect failure.- P; p. \3 f9 |& |- A0 \
1204629 ALLEGRO_EDITOR SKILL axlUIDataBrowse crashes the editor or returns error
I. M2 W6 G0 k n* T5 ?1204640 SIP_LAYOUT DIE_EDITOR Concurrent co-design update fails
, w4 {5 S5 T6 G4 ]' J+ S% _1204881 SIP_LAYOUT BGA_GENERATOR Pin numbers are messed up after deleting a pin at a staggered bga
. K9 T7 Z0 n" Y4 @- Z! U1204885 CONCEPT_HDL CONSTRAINT_MGR Cant assign discrete models after the wrong model was removed.: `2 N) X( p+ [
1205374 ALLEGRO_EDITOR OTHER pdf out command creates incorrect drill Symbol Characters placement in pdf file when setting film mirrored.. `6 k8 ^2 e0 j; q# E& w9 U
1205729 SIP_LAYOUT DIE_EDITOR update of codesign db fails on exit from die editor5 j8 `. t4 ]! \; v) H/ o: A
1205801 ALLEGRO_EDITOR OTHER Tool crash when do export IPF.
8 ]/ U4 R V( f" D ]" K- V1205881 CONSTRAINT_MGR OTHER In CMGR , Objects > Create crashes Allegro
' H8 S4 y+ c; C# y& h/ r2 [& O' a5 ]5 N8 v: ?/ Z0 s
DATE: 10-25-2013 HOTFIX VERSION: 018
0 R/ T# O8 I% k& W& R===================================================================================================================================% K. A# W3 x0 a. @0 ?+ _: f, j
CCRID PRODUCT PRODUCTLEVEL2 TITLE
3 u2 N1 p* ]* ^" ?. f7 p& d4 f' T===================================================================================================================================+ t! `7 a6 F6 T/ T d
1118303 CONCEPT_HDL CONSTRAINT_MGR can not prdefine default units in HDL
( u% m- ~6 N q2 L1174901 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl: m D# s) s0 J" M
1176990 CONCEPT_HDL OTHER DEHDL BOM tool doesn縯 see similar names.* N6 [9 V' v6 V+ _% @/ }: q
1179665 GRE CORE Plan Topological Crashes after around 8 hours of routing.. I3 m. h6 M2 c8 p: A
1188193 CONCEPT_HDL CHECKPLUS CheckPlus not recognizing PIN as a base object.9 V1 F3 Y# F% y) E- P
1189100 SCM OTHER Replace part in SCM using ADW as library fails
Q1 w7 t2 V6 x( z. v. ~1189507 SCM SCHGEN ERROR(SPCOCN-2009): Package error after second schgen run with Preserve mode.
0 a* G- C; g9 ?- ~# n' f1192391 CONSTRAINT_MGR CONCEPT_HDL Restore from definition deletes local objects in other blocks
$ e7 i1 W# }' J1194597 FSP OTHER Pin definition problem
8 e. s- e# }# T! Z# y8 a1195202 SIP_LAYOUT LEFDEF_IF Cannot add .lef files in IC Library Manager. Getting warning message WARNING(SPMHLD-52)
$ h. }: ~: m. x( ~9 a, _1195309 GRE CORE GRE crashing during Plan Spatial.
' n7 E3 r" A& ~# T3 i; A1197262 ALLEGRO_EDITOR MANUFACT Angular Dimension created in symbol is placed w.r.t. board origin and angle is blank
8 _& t+ r. X2 C! x" ^# u! S1198521 CONCEPT_HDL OTHER cadence DEHDL issue - Note for Hotfix_SPB16.60.016_wint_1of1
) |. w ^: N/ w" [& O& y1199219 ALLEGRO_EDITOR INTERFACES Question on STEP Model export which uses PLACE_BOUND layer for any symbols that do not have STEP model mapped
8 \: S, `! d/ ]& f1199235 ALLEGRO_EDITOR SCHEM_FTB capture's behavior is redundant while creating pcb editor netlist4 g5 h9 l# V1 B! ~, @
1199323 GRE IFP_INTERACTIVE Crash when importing logic
9 M- ?, X" r; z; U! m1199368 SIP_LAYOUT DIE_EDITOR Refresh of die abstract in die editor with this design takes over two hours0 ~' r8 G7 `# ]' x; e8 T
1199760 ALLEGRO_EDITOR DATABASE Allegr won't display Soldermask Top layer
7 r) U# X7 N# X: ]& R1 O- L- |% {
1 ?1 P/ j1 u1 W: L( k! v7 pDATE: 10-10-2013 HOTFIX VERSION: 017
+ p: K; K2 @6 H. {) K. X0 B===================================================================================================================================# b7 f2 s( G# [# `. V; @, G7 z* o
CCRID PRODUCT PRODUCTLEVEL2 TITLE
) m4 s# n- B3 E" ^$ Y z: ~===================================================================================================================================6 u _3 @8 f+ N" F" l
735992 ADW LIB_FLOW Create Test Schematic does not use the correct package type
_ w. H: b# i: K. A: b1121403 FSP PROCESS "Assign to Pin" not getting obeyed by Synthesis.0 b4 Z: d8 \: O9 }
1141844 RF_PCB DISCRETE_LIBX_2A ADS Lib Translation Pin Soldermask/Pastemask missing
4 L g# U7 a* @6 w2 y, w, O( O1169269 ALLEGRO_EDITOR DRAFTING Dimension placed on package symbol moves to different place when it is placed on brd file.7 ]) l3 y+ x; c. j+ a1 ~8 m
1170488 ALLEGRO_EDITOR MANUFACT Dimension text(on .psm) move to different position, when it is placed on .brd.4 M- F' q# Y8 U4 \$ P/ K
1173345 CIS CRYSTAL_REPORTS Crystal Report - Display Parameter dialog for export option
9 S/ K3 a. d3 R! z& c3 }" x8 b1181759 SCM LVS SCM Crash when doing update all that executing import physical command.- q1 o- v a3 ?) a9 \" J, I
1182499 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks (all pins and via) drill.5 O: F1 Z2 Z4 A s+ a+ E6 [
1184682 CONCEPT_HDL CONSTRAINT_MGR Net Constraint not transferring to layout from schematic) m. c, `# G, Q& Q- `7 e6 a8 h$ U
1185524 F2B PACKAGERXL Enhancement User would like notification of pack_short in pxl.log7 q$ B0 y/ N9 S2 X: v% g
1185902 ALLEGRO_EDITOR SHAPE Update shapes dont clear some diffpairs in HF15+ e* l9 z1 \/ C* T. M# m
1186152 ADW LRM Part Status for Deleted Part in LRM is distinguished with other part status
: J" E' p( p- b) O1186387 ALLEGRO_EDITOR OTHER DXF cannot catch offset value in s047 hotfix.! B& b; M# h, r' B w
1186805 ALLEGRO_EDITOR OTHER Exported STEP file missing multiple components placed on board3 \5 T4 J1 U/ T' n0 x
1186818 ALLEGRO_EDITOR COLOR Custom color not retained during dehilight
& ]1 Y. q) o% J; P1187196 CONCEPT_HDL CORE TOC not populating (page 1)9 @1 E& O9 y5 R: E# s+ e/ R! C
1187667 F2B PACKAGERXL Existing hard LOCATION property in drawing was left unchanged+ [& G( Q) z! {! W% S P" ^9 @
1188264 ALLEGRO_EDITOR MODULES Some fillets not regenerated in module created from a board file.
R- o8 X; B4 k, u5 U/ I1190144 ALLEGRO_EDITOR OTHER Fillet shape is not genrated around cline/ m) k, t' H- H
1190210 F2B BOM The bomhdl.exe fails - MFC Application has Stopped Working# t t, P& z9 V1 ]8 e
1190618 ALLEGRO_EDITOR GRAPHICS Enhancement for Visible grid
( \5 P, p0 c9 y4 G( w1 g5 g1190813 ALLEGRO_EDITOR INTERFACES 3rd party netlist file in TEL format fails syntax check but imports successfully" f9 U/ o! _3 a, V; t, T* Y6 x0 g
1190895 ALLEGRO_EDITOR EDIT_ETCH Route delay meter displays violation when sliding diff pair
9 F; R/ k Q0 g, @7 u& `! l1190908 F2B OTHER DE-HDL aborts if dummy net is being cross-probed from PCB Editor: T7 P. D4 s9 y8 c8 `5 m
1190990 CONCEPT_HDL CORE Mismatch in .csa and .csb files1 g* q3 U4 O. S0 V: T
1191008 CONCEPT_HDL CORE Remove Binary File feature doesn't work: d5 [ p8 V" s! [9 M3 @# r
1191514 SCM PACKAGER Packaging error PKG-100( X7 n9 u: T: D3 ]% u7 k
1191517 ALLEGRO_EDITOR DRAFTING Metric +tolerance when using dual dimensions is not displayed correctly) |0 o8 @$ J" T, p$ X8 i
1192561 ALLEGRO_EDITOR GRAPHICS Padstack with offset is not showing correctly in the 3D Viewer.
% X1 X& q J8 U& C# M ]1192916 ALLEGRO_EDITOR EDIT_ETCH Wrong static phase values are shown in the dynamic timing meter for certain Diff pairs compared to CM.
3 m$ U/ S- y7 ~* y1194197 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks.
( M6 e6 B$ Y! b! E) ~; T1194239 PSPICE DEHDL Associate Model does not launch from DE-HDL
7 d# J( T" z* R' s3 F3 g) u1194736 PSPICE SIMULATOR Design causes RPC failure when run consectively* \2 [+ h* s7 B5 ~) L0 J- }, @
1195139 ALLEGRO_EDITOR PLACEMENT Components disappears from board file once they moved% b d- V' V( ?$ l; _* `* b, B
8 T) ^' d7 i) i/ q. {( s* u
DATE: 09-27-2013 HOTFIX VERSION: 016
0 i; U! \) w7 d: p% H===================================================================================================================================, m3 j% y3 T6 m' _# o4 {) e( d: B
CCRID PRODUCT PRODUCTLEVEL2 TITLE& g0 K* D( z4 M s
===================================================================================================================================
0 n, ^3 ^' {8 N1 x; O548538 CAPTURE NETLIST_ALLEGRO Enhancement:Include mechanical parts in Allegro netlist& C$ e* `0 Q0 L# I( m
1076579 CAPTURE GENERAL Display value only if value exists$ a2 t3 f& G6 L, h; h9 h% G
1083904 FSP GUI Need Filter in Change FPGA dialog to select desire FPGA from the long list.4 Y1 z/ s5 l, V/ n
1089313 ALLEGRO_EDITOR INTERFACES Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility
3 D% P8 q7 y: G, E) w' a" n, M5 O1095728 ALLEGRO_EDITOR EDIT_ETCH Slide to grab adjacent elements when extend selection is enabled
# V; h- f( K- B2 R$ C+ g1102698 SIG_INTEGRITY ASSIGN_TOPOLOGY ECset will map on single ended nets but fails when the two nets are define as a diff pair.
; V) X Y: w9 A% o% K1104071 SIG_INTEGRITY REPORTS Shape Parasitic value changes for bottom shape for changes in top shape' K$ L% w8 W% ^8 x
1117731 FSP POWER_MAPPING Ability to sort in Power Regulator forms
. Z5 y5 X) T1 d! T8 w2 C+ p1121539 FSP CONFIG_SETTINGS Cannot configure special FPGA pins (temperature diodes)
, ?9 F- o! ]% {' t2 O1122721 FSP MODEL_EDITOR Partial copy-paste overwrites the complete cell in XML Editor. K* ]0 J7 H- S* ]+ g) M! B" p
1123238 FSP TERMINATIONS Report functionality for terminations defined in the complete design.
9 F0 d' N* q) {3 D8 O7 ]7 l% h( g1123364 FSP GUI Clicking on column header should sort the column.
% o$ O; o; L/ r" ?/ L* r1123403 FSP EXTERNAL_PORTS Improper checkbox selection for 緿o Not Connect� or 縀xternal Port� column! C/ J8 V6 a* I( w: Z3 A4 s
1125611 CONCEPT_HDL OTHER display unconnected pin in schematic pdf.8 C! `: e$ ]7 y( S {
1129871 ALLEGRO_EDITOR INTERACTIV Wire Profile Editor can't read mcmmat.dat in working directory.
' m/ [! D2 {4 J% l6 }" R1133688 ALLEGRO_EDITOR GRAPHICS Enhancement request to enable 3D Viewer to show STEP model from .dra file.
" m& Z5 G! c- u6 R: h$ p1141747 ALLEGRO_EDITOR GRAPHICS 3D view dooesnot displays height if step_unsupported_prototype variable set9 L+ n9 E+ a. F4 \
1142215 SIG_INTEGRITY SIMULATION PULSE_PARAM set on DiffPair wasn't used for designlink simulation.
' F* w' \* c r5 {4 K L" U# u1142798 ALLEGRO_EDITOR INTERFACES Step file output is incorrect in step viewer when composed of arcs and line.+ ?4 t8 Q; K3 _
1142894 FSP GUI Ability to RMB on a header and select `Hide Column�/ l6 I- E1 L2 [ ]& y$ t
1142940 FSP EXTERNAL_PORTS Issue with checking/unchecking "Do not connect" and "External port" cells
9 F% ?/ r: I7 f* a! F% O2 W1142949 CONCEPT_HDL SKILL Usage of "Preferences > License Settings� in FSP# r7 t) o' _% B1 @. h+ o* X! O% u
1143091 SIP_LAYOUT SYMB_EDIT_APPMOD symed: When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract
+ P- V8 y! A& K: w1144371 CONCEPT_HDL COMP_BROWSER Component Browser search results are inaccurate
! Y+ H) ?% y3 M1145033 ALLEGRO_EDITOR PLACEMENT When aligning components with options in Placement mode displays no busy indicator0 {4 N B! B1 {9 E0 K- m: h
1145286 CONCEPT_HDL CORE Directive required for switching off the console$ d$ o. }7 l) g7 V- Q# {; x- ]# V: \
1145800 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl./ X' {7 X+ a) k& n. ?
1147899 ALLEGRO_EDITOR SHAPE Autovoid two overlapping shapes that share the same net# n% ~$ k/ _. u2 S- R+ t
1149996 ALLEGRO_EDITOR EDIT_ETCH Routing does not follow the ratsnest 'pin to pin'.
2 o1 G" l( ^' m0 d5 ^% |1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.
( M E1 Q( b: s5 q1 }$ l% f% J1152577 ALLEGRO_EDITOR DATABASE slide removes cline seg2 U5 J' @( r' ^* o. Z* |2 ^- U
1152751 CONCEPT_HDL CORE Option to double-click and copy the Netname
3 ^& J& z7 [* e1 n) x k9 {1153220 ALLEGRO_EDITOR INTERFACES ENH: option to supress header/footer during PDF Export
# E$ D( y$ p x5 G, s, r, i- n0 J1153625 ALLEGRO_EDITOR INTERFACES If Symbol has place bound bottom, the step model shows incorrect placement.6 O' w w% H0 N
1153813 CONCEPT_HDL CORE Spaces should not be allowed in the signal name entry form3 S2 ] a: G$ c4 w
1153857 CONCEPT_HDL CORE Changing different power symbol should maintain the schematic level properties.7 R3 f6 Y3 R T+ T% j
1155161 CONCEPT_HDL CORE Add Signal name: Suggestion box overlaps with the typed signal name that is typed
3 _5 d/ Y1 K) W, x1155922 CONCEPT_HDL OTHER How can I use the batch mode for PDF Publisher and print a variant overlay?6 W* Y$ }( S6 U1 x0 j
1156858 ALLEGRO_EDITOR PADS_IN PADS Translator: Missing drill on square PTH padstack
7 g' Y2 _2 A6 }1 z2 R, Q: Y1157362 APD 3D_VIEWER Need a way to color multiple nets in 3D viewer from APD/SiP.
4 r( s' M) |, A4 H! S% O1158130 CONSTRAINT_MGR ANALYSIS Constraint Manager do not display the Cumulative Result in Reflection Simulation- K8 q9 r: v3 g2 o v0 Z
1158210 ALLEGRO_EDITOR SHAPE SIP Layout happens crash while users move the shape with route keep-out+ N3 d Z* I G' U2 G1 e
1158452 SIG_INTEGRITY GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle
& e. k6 O1 e2 N" x# P* {1158827 ALLEGRO_EDITOR EDIT_ETCH Slide a via in pad automatically add cline back to via to pin.
/ \. r7 y- Z! [1158871 PCB_LIBRARIAN IMPORT_CSV PIN TEXT is not automatically added when importing the .csv file8 c) b4 L9 E( N; J( o8 N
1159738 ALLEGRO_EDITOR INTERACTIV Selecting the Cancel button in the Text Edit command does not cancel the text.7 M7 s" M2 [! \8 z) `, b' `* s
1159878 SIG_EXPLORER OTHER Ecset mapping dont follow topology template
N* ]3 Q& \4 E5 e' X; a( l: c3 L4 X1159971 ALLEGRO_EDITOR MANUFACT Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file0 O: u" c& |# `! A B
1160017 SIP_LAYOUT DIE_ABSTRACT_IF Add text to clarify shrink operation6 }& Y0 { T+ O% L2 u
1160507 APD EDIT_ETCH Script not playing back what was recorded when sliding lines
) I9 g! j; A) A3 n1161261 ADW TDO-SHAREPOINT Schema for TDO-SP fails on Japanese OS8 {& k: w" x" e" C9 W0 F
1161538 CONCEPT_HDL CORE Espice model value edited in DE HDL & then netlisting done, but it doesnt changes the earlier assigned model in Allegro2 p K9 ]$ E. v
1161636 ALLEGRO_EDITOR DRAFTING need new function for PDFout : hatching shape5 ^4 m2 u/ \1 @1 {
1161777 ALLEGRO_EDITOR OTHER default line width for PDF output
* G, n5 m" g Y" U' X7 Y1162383 CONCEPT_HDL CHECKPLUS Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.9 J' K! X8 d! F8 s9 ?. w
1162562 CAPTURE STABILITY Capture crash on second attempt of pspice netlist creation in 16.6
" X% K4 f6 u9 N+ B$ W1162629 FSP PROCESS "Load Process Option" under Run does not work properly
# ^! n# q. t3 `/ Y1162686 CONCEPT_HDL CORE Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE
' K; o! j, E2 U4 P V$ s; Q1163149 ALLEGRO_EDITOR DATABASE Autosilk creates Illegal arc to corrupt database( ?. `- d2 O7 B8 c4 b
1163439 ALLEGRO_EDITOR COLOR Duplicate Views Listed in Visibility Tab.+ R+ g: _8 u$ I3 W+ ^! L
1163521 CONCEPT_HDL COMP_BROWSER System Architect crahes on replace0 z; V1 u! b3 |" y* x% V H
1163709 CONCEPT_HDL CONSTRAINT_MGR Loosing Diffpairs when reimport block or restore from definitioin8 d' f6 f C7 d6 q% \. n
1163902 APD EXPORT_DATA Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?
7 T, B9 Z& ^) N4 n7 A- j1164337 CONCEPT_HDL CORE Cannot delete attribute filter value in PDF > General > Attribute Filter list6 n b! z, K+ W: _" m1 h0 ^
1164365 ALLEGRO_EDITOR INTERACTIV Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol& N+ B* X i/ }9 i3 \: }7 d' s
1164769 APD VIA_STRUCTURE The replace via structure command does not accept a single canvas pick.
/ X, k9 s) ~( X/ n( P1165026 ASI_SI GUI EMS3D exist in Via Model Setup of SI base.3 h a- T! k7 {
1165561 CAPTURE DRC File > Check and Save clears waived DRCs
! [5 A8 @! f) J$ A: z& J1 L! k1165631 CAPTURE STABILITY Capture crash in the hierarchy tab of Project Manager window/ ]: N* I# y; H1 T! I x
1165836 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)! T* ?1 a- y4 M: ?3 T9 X$ s
1165911 FSP PROCESS Editing group name in protocol causes incorrect Process option checked
- h( Y- A& v7 I. U5 |1166026 ALLEGRO_EDITOR DATABASE Running DB Doctor removes net name from vias6 s% A/ n9 _* f+ k. c0 J
1166034 SIP_LAYOUT OTHER SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle
8 {2 f$ ~; X) I1166074 GRE CORE GRE crashes during planning phases$ D: ]% f9 _5 k( P: T' R
1166319 ALLEGRO_EDITOR PLACEMENT Swap not succeed
3 T$ ` Y5 Z5 O& c+ G9 @! `7 c: W: Q1166484 SIP_LAYOUT WIREBOND Bondfinger "Align With Wire" problem during move0 z* Z. t8 B3 ]0 ^7 h/ I. [9 z
1166530 ALLEGRO_EDITOR INTERACTIV Bug: Mirror in Placement Edit resets the options tab for Edit > Move7 U0 V( D* u% F9 T; G- [
1166819 CONCEPT_HDL CORE Cadence DEHDL Text Size Issue8 l, p, q1 y4 C" U' J: q/ f$ t3 J
1167847 CAPTURE PROPERTY_EDITOR Implementation name length greater than 31 character causes capture crash3 c% b! @) Q8 F# M3 T% g- ]9 D
1167887 F2B OTHER Improve message on symbol to schematic generation& |4 I4 j, [# U. m6 Y! G
1168369 F2B DESIGNVARI Variant don縯 appear in increasing order while Annotate.
+ r% Y3 t! z3 B1168629 APD OTHER Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD; p8 \0 g ^2 p8 |6 X7 W: z: b% P
1168678 ALLEGRO_EDITOR NC Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.
8 {4 ?7 v. ?! j# S% Y1168798 ALLEGRO_EDITOR INTERACTIV Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk. H+ B5 }" |' `" ~
1168830 ALLEGRO_EDITOR DRC_CONSTR missing DRC-marker for package to package check! a0 K6 y1 `/ i7 U' z
1168864 ALLEGRO_EDITOR CREATE_SYM Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty1 G& M8 Q3 s" R. S V* z+ z4 B
1169213 PSPICE SIMULATOR Parametric sweep is giving incorrect reuslts
) B7 M# H& ]1 j* u- F% T: k* ^1169436 FSP FPGA_SUPPORT Add support for Cyclone V CSX and CST parts1 n5 o/ k4 R$ w, X9 [3 J
1170108 ALLEGRO_EDITOR INTERACTIV Enhancement to preserve Rat T location for Topology assigned schedule2 P" F& ~ Z ]4 R" x* D
1170313 SIP_LAYOUT LOGIC scm adding additional pin names and unassigned property to codesign die chips file
2 ^, @4 n) A% X! I! |; ?9 l9 O* ]& h1171136 CONCEPT_HDL CORE Page Number should also be displayed in Import Design Window., d% L8 w7 u& X
1171747 ALLEGRO_EDITOR PLACEMENT Allegro crashes when doing a gate swap between components0 D1 `( f2 m# Z- T0 d, m" P+ k
1172183 ALLEGRO_EDITOR INTERACTIV Alignment modules fails on equal spacing
( ~" I+ b+ Z& \# C9 Y- }+ Y1173183 ALLEGRO_EDITOR DRC_CONSTR Undesired Same net DRC for overlapping Pin and Via3 j% b- T; ^3 M9 R0 V) j
1174067 ALLEGRO_EDITOR DRC_CONSTR Soldermask to shape drc does not show if the layer is a PLANE.( S. L. l) J3 Q% S d+ y$ \
1174338 ALLEGRO_EDITOR PLACEMENT preview has rotated pads
9 I/ e* g |" h6 D+ o1175307 CONSTRAINT_MGR ANALYSIS CMGR fails to report RPD DRC for accuracy 4 - mm
+ l* ~- r3 X6 G! M& ?; ~1175537 ALLEGRO_EDITOR REPORTS net loop report crashes Allegro. Design specific
* T; P+ k7 W8 [* F% V1 _1176126 ALLEGRO_EDITOR INTERFACES 3D viewer doesnot change models units dynamically
% T+ K, @" n0 F* i% o1176281 CONCEPT_HDL CORE Option to Auto-hide excluded modules5 g3 K/ x8 v* q
1176413 ALLEGRO_EDITOR MANUFACT Q - testprep parameter settings is not retained, what could be the cause..
7 {" w' _3 S, ^, C1176791 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl
& _1 x/ O5 D" {4 p: ~1 e1178052 ALLEGRO_EDITOR SHAPE SIP crashes during shape degassing.
* W0 r, G2 v! A0 [1178158 ALLEGRO_EDITOR INTERFACES Export step file creates step file of same height% r( G* u( @7 q/ _ N4 W
1178201 ALLEGRO_EDITOR GRAPHICS Large oval pads rendered as oblong hexagons in the 3D viewer3 U, b/ o K8 c: D' N1 Q$ N& w
1178671 ALLEGRO_EDITOR GRAPHICS 3D Viewer in package symbol editor not displaying correct place bound shapes.
* [) E" Z' K. s& j1178725 ALLEGRO_EDITOR OTHER With fillets present, rat lines do not point to the closest endpoint.# U9 ^+ @3 W1 J3 V+ U
1178972 CONSTRAINT_MGR ANALYSIS The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.
% ~7 F. f2 Z: K; F8 J0 a i1179093 ALLEGRO_EDITOR SHAPE Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas.
, E" n' e: H' \1 M1179109 ALLEGRO_EDITOR OTHER DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version
. F. d3 y3 C& T, l, e+ v1179571 ALLEGRO_EDITOR ARTWORK Artwork crash and artwork log report Aparture missing3 H" _* V- Z# L6 j" D# ~
1179636 SPECCTRA ROUTE Route Automatic will not start if NET_SHORT are attached to a mec-pin
# ~+ G% |& b1 a/ T1179659 SIP_LAYOUT DIE_EDITOR die edit on co-design die losing c4 bumps
3 ?- Y7 K) i' L$ t- }1180306 ALLEGRO_EDITOR ARTWORK When trying to create Artwork the tool crashes with no error messages just a little X box
T- x+ v! x" D, A' W1180573 ALLEGRO_EDITOR ARTWORK If one layer has warning, all artwork films are "created with warning".
( _) q* Y }$ L3 q; L2 [5 n/ ^1180960 SIP_LAYOUT PLACEMENT swap function is not swapping logical paths in sip layout!7 H5 Q. Y* P7 a7 `9 Q
1182534 ALLEGRO_EDITOR SKILL axlLayerPrioritySet() not working with v166 s013 and up4 c. F' Q" k( W. W$ B( J
1182560 ALLEGRO_EDITOR PLOTTING Creating plot 2nd time casues Allegro to crash
+ g# y5 e& `2 ]# C1182616 ALLEGRO_EDITOR PLACEMENT Application crashes when attempting to place a high pin count BGA9 {- h" ]! v' M! V- p- H' S
1183752 CONCEPT_HDL CORE Unable to modify location properties within a read-only hierarchical block
8 Z2 ]6 [3 A) j$ {: Q1183774 SIP_LAYOUT DIE_EDITOR Die Refresh hangs
# P1 y! R; y% n6 t- c( L1184178 CONCEPT_HDL CONSTRAINT_MGR Ecset xnet members lost from electrical class when restore from definition of subblocks
! g% T3 G" D4 g8 s1184787 ALLEGRO_EDITOR EDIT_ETCH Allegro SPB166 s 015 crashes during normal add connect function.
1 `; s3 D- F/ D& x- e: L- u9 |. E$ s( e1 q3 ]( V* k9 [, P
DATE: 08-22-2013 HOTFIX VERSION: 015. O9 R" Z3 C; x) {$ q8 Z1 V3 I
===================================================================================================================================
9 d+ {; l7 [8 m& m/ L" ?5 _! nCCRID PRODUCT PRODUCTLEVEL2 TITLE8 N9 v* K; \ _- K! U" K7 \. G- ~8 V
===================================================================================================================================, J! Z$ x* o" I- A. r2 `
1156102 PCB_LIBRARIAN CORE PDV severe performance degradation on Linux platform makes PDV counter productive after some time
5 C' X i. H" ^9 v% F1165756 CONCEPT_HDL CORE DE HDL 16.6 adding ASCII character to properties% C* w% w. y6 o( ^/ J0 g
1169896 ADW LRM Library Revision Manager makes updates but the interface never returns to the user" }* _6 O% J9 k) t( g. T, u( c
1170635 SIP_LAYOUT WIZARDS BGA PIN NAME doesn't sync with PIN Number
4 z# i- h% ]3 V6 }- r! }2 [1171061 ALLEGRO_EDITOR PLACEMENT Place Replicate Apply cannot place module
' U8 O& c7 Q6 d: \ v0 E+ c" v2 g* V1171415 CONCEPT_HDL CORE Mismatch in the interface ports in design bw_hybrid for block a38410_scsp" H$ V2 K; Y$ {- G* g0 f K
1171598 APD WIREBOND Cannot load xml over 65 profiles defined in file.# p* d% y& g( R4 ~) d- E9 o
1171713 ADW LRM Blank lines appear in the LRM - RM-Clicking causes LRM to crash( Y8 k+ A1 s4 {; J4 K3 w/ |
1172576 SIP_LAYOUT IMPORT_DATA AIF import fails with Error: symbol is missing refdes
k3 P n4 |, K1172938 ALLEGRO_EDITOR PLOTTING Export IPF probrem
! V6 B( ~, Q( _3 c. }/ n1173190 ALLEGRO_EDITOR ARTWORK Not able to Add/ Replace film_setup.txt file in Artwork control file.
# F" c/ J) ^6 b( X4 O0 b9 L1173750 ALLEGRO_EDITOR REPORTS SIP tool crash when clicking report "Net Loop Report"
. w0 b8 s$ o6 N7 t4 E# q1175582 ALLEGRO_EDITOR SKILL axlDBCreateFilmRec error undifined function1 v9 ?) f6 C, `/ Q G" u
. d0 Z& I) G7 g" H* MDATE: 08-9-2013 HOTFIX VERSION: 0144 O1 f& u3 Y5 ~& l6 K! x
===================================================================================================================================$ {: p2 L3 Z/ ~6 T2 R4 q4 c5 P$ u" b
CCRID PRODUCT PRODUCTLEVEL2 TITLE
* R6 j Z( H" c& {- t8 J4 i) {, F===================================================================================================================================
( y; N6 o6 e! c4 S- {5 P1155569 APD MODULES P1_U1 and P1_U3 Die pins are missing after Place Module.2 o: {* m- G0 \/ l0 A. ?/ I7 [, }
1158528 CONCEPT_HDL OTHER Dual Monitor issue: Retain Hard Packaging option is missing and attribute test distorted
, \# i) P* q4 B$ g4 j8 ~+ j( P# z) T C1160968 ALLEGRO_EDITOR SKILL Text Subclass change difference in Edit > Change and axlChangeLayer Skill command
/ E, G9 P* V4 n. v1161986 SIG_INTEGRITY SIMULATION Flatline waveform seen when via model is set to detailed closed form or analytical solution
. r1 K" y8 `! y2 Z0 Z0 F. S1162323 SIP_LAYOUT DIE_EDITOR Die Editor is incorrectly leaving an unassigned function pin in the die during refresh from die abstract
; e- u+ T( z" x0 x7 f5 A5 i1162752 ALLEGRO_EDITOR SKILL axlDBChangeText doesnt recognize ?layer as a valid argument as documented% o# \, ]5 ^5 w7 q/ H
1165002 GRE CORE GRE Crashes during Plan Spatial giving "Memory Allocation Failure" Error.& i* h" f! c3 V9 k" t5 X
1165469 CONCEPT_HDL CORE Import Design loses design library name
/ `6 A5 ?* L+ Q7 N) Y' H1165708 ALLEGRO_EDITOR TESTPREP Test point router failing when attempting to insert new TP via's$ e! X+ x$ X. M( u
1165801 CONCEPT_HDL PDF Pin texts of spun symbol overlap in publish PDF.
) S3 l( c: \2 Z1166020 SIP_LAYOUT WIREBOND Bondpads created with shapes do not follow the orthogonal pattern when adding wirebonds.- \! A9 B. E Z
1166371 ALLEGRO_EDITOR DATABASE File locked for writing in 16.5 cannot be unlocked in 16.6
7 a* f. A! L+ j1166482 ALLEGRO_EDITOR INTERFACES Step orientation for y-rotated component is not exported correctly.
6 I" F& [" T( j5 k" _1 k1167519 ALLEGRO_EDITOR DATABASE Uprev dbdoctor does not log warnings about renaming properties.
5 ]( y' A2 l, y, a' a) W' G1167588 SIP_LAYOUT DIE_ABSTRACT_IF do not create a new pad stack for each I/O pad% }3 `! n. _2 Q$ P
1168496 ALLEGRO_EDITOR SCHEM_FTB Export Physical Crashes when netreving the board
: H, c5 ^; b* X9 Z6 Q3 }, H1169510 SIP_LAYOUT WIZARDS Netlist in Wizard is crashing with this text file where the Net Name for one of the assignments is blank, meaning dummy
c/ s* E- N( w. M' c( p1169593 CONCEPT_HDL PDF Published PDF file's hyperlinks do not work fine when user click 1D10 or 2A10.
' A% i- b J) W; K1169984 F2B PACKAGERXL Error Mapping cset when packaging but not in CM Audit2 e& N- _4 I' |- H% o
1171008 SIP_LAYOUT OTHER SiP Layout - Beta feature Void Adjacent Layer Shapes - changes or modifies "priority" of other/all shapes
8 k, v& E( E0 [& N- d9 j. I1171411 ALLEGRO_EDITOR OTHER Enh - Break in Step 3D view in latest hotfix v16.6s013# |; Y% [+ w& J8 @ ]$ \1 M
: e8 o9 p) Y, M$ d2 _( GDATE: 07-26-2013 HOTFIX VERSION: 0137 R" s1 Q$ A* f2 Y4 y9 l
===================================================================================================================================, ~" {7 n* B! Z8 W9 \
CCRID PRODUCT PRODUCTLEVEL2 TITLE
1 K& d# A" Q6 q. \" H% D===================================================================================================================================" l7 B7 J2 a+ L/ _) M8 s3 h
111368 CAPTURE CORRUPT_DESIGN Capture - will not produce allegro netlist with 10.0
5 o0 @6 W- [3 E5 F4 i1 ^134439 PD-COMPILE USERDATA caCell terminals should be top-level terminals
8 Z- N3 R) v Q+ g! ? @186074 CIS EXPLORER refresh symbols from lib requires you to close CIS
" E' {5 d, b9 E. D$ Y583221 CAPTURE SCHEMATIC_EDITOR Option to have the Schematic Page Name as a Property in the Titleblock
( U$ d, A) H+ M; c, j; u2 ~591140 CONCEPT_HDL OTHER Scale overall output size in PublishPDF from command line6 s% M- z4 v" P/ [" W
801901 CONCEPT_HDL CORE Concept Menus use the same key "R" for the Wire and RF-PCB menus
6 h# B+ Q5 z, ~+ K* a5 Q+ L0 E. ~- Q813614 APD DRC_CONSTRAINTS With Fillets present the "cline to shape" spacing is wrong.- w& y$ E$ s) k# u1 b
881796 ALLEGRO_EDITOR GRAPHICS Enhancement request for Panning with Middle Mouse Button( }9 s# ]; s% d
887191 CONCEPT_HDL CORE Cannot add/edit the locked property
0 F1 ^" a0 m. A$ `* m# Z8 E: @911292 CONCEPT_HDL CORE Property command on editing symbol attaches property to ORIGIN immediately
; T6 o9 W4 D( ?5 v: }* j987766 APD SHAPE Void all command gets result as no voids being generated on specific env.& k4 J- c. z P$ O& v1 X) G/ I
1001395 SIP_LAYOUT ASSY_RULE_CHECK Shape Minimum void check reports lots of DRCs which are not necessary to check out.
( s7 I" f" W8 A7 }9 O" p: _1030696 ALLEGRO_EDITOR INTERACTIV Enh - Allow another behavior of PAN movement using middle mouse in Allegro- E, w; e' T/ n4 s, j/ S
1043856 ADW TDA Diff between TDO and DE-HDL Hierarchy Viewer is confusing to the user9 M' b' r* R- J% P7 l7 ^
1046440 ADW PCBCACHE ADW: ImportSheet is not caching libraries under flatlib/model_sym when the source design is not an ADW project
& Q: h4 C7 H6 x- @! I1077552 F2B PACKAGERXL Diff Pairs get removed when packing with backannotation turned on' o Y# w1 `1 _7 c5 Y2 w# o- U4 @6 A
1079538 F2B PACKAGERXL Ability to block all 縮ingle noded nets� to the board while packaging.
* ]# v$ W3 I; w1086362 ALLEGRO_EDITOR SHAPE Enhancement request to autovoid a via if shape cannot cover the center of the via.
$ q6 ~; s6 D( I- u* s1087958 PSPICE MODELEDITOR Is there any limitation for pin name definition?
2 r) M2 A" {! K3 \# Y+ A. Q1087967 CIS UPDATE_PART_STAT Update part status window shows incorrect differences
/ a3 @7 z" O. b" e4 A1090693 ADW LRM LRM auto_load_instances does not gray out Load instances Button
! Y1 b0 s: O% F. I1 s* G1097246 CONCEPT_HDL CORE ConceptHDL - assign hotkeys to alpha-numerical keys
& l2 B2 b7 u4 m1099773 CONCEPT_HDL CORE DE HDL goes into recursive loop if a custom text locked at site level is deleted from Tools > Option# Q6 z1 W: C) l2 F5 G0 Q
1100945 SCM SCHGEN SCM generated DE-HDL has $PN placement issue# q- p# C5 Z9 ?% Y- W3 Y
1100951 PSPICE SIMULATOR Increasing the resolution of fourier transform results in out file0 }. `' ~# c2 Z% ^: |7 Z3 G
1103117 RF_PCB FE_IFF_IMPORT Enh- Allow the Allegro_Discrete_Library_to_ADS_Library_Translator to output in its original unit
3 {. R% E6 k+ ]+ M9 ^/ M1105473 PSPICE PROBE Getting error messages while running bias point analysis.! i" c) r0 W, [' P9 u Z. q
1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr.
, Y, a8 [, q7 C; {6 P! E1106298 ALLEGRO_EDITOR INTERACTIV Copy Shape uses last menu pick location as origin and not the Symbol Origin as specified in Options.0 u" `/ Z, j: g* b$ ?( b
1106626 CONCEPT_HDL CORE Concept HDL crashes when saving pages
! U( b. n. ?7 }9 a2 [1107086 ALLEGRO_EDITOR INTERACTIV manual void with arc's goes in wrong direction during arc creation+ K) W& W! y% V5 T+ L
1107172 CONCEPT_HDL OTHER Project Manager Packager does not report errors on missing symbol
& g5 t: V& q, K/ w1108193 CONCEPT_HDL CORE Using the left/right keys do not move the cursor within the text you're editing# t! R2 ]+ m" U# ~# I
1108603 PCB_LIBRARIAN VERIFICATION PDV Tools Verification > View Verification (CheckPlus) leaves <project>.cpm_tmp.cpm1 E1 [+ Y& {) Q5 @6 `" S1 h
1109024 CIS OTHER orcad performance issue from Asus.
$ L _3 ~) @1 ?1109109 CAPTURE NETLIST_ALLEGRO B1: Netlist missing pins when Pack_short property pins connected
0 s% \% z6 O) R1109466 ALLEGRO_EDITOR ARTWORK Artwork create some strange gerber lines for fillet./ g) `, D4 ]* ~! q) q
1109647 SIP_LAYOUT DEGASSING Shape degassing command enhancement - control over what layers are counted in even/odd layer sets.
8 _; h/ |, R% x7 [1109926 CONCEPT_HDL CORE viewing a design disables console window
8 M P1 Z' i9 w; h$ W1110194 SIP_LAYOUT WIREBOND If OpenGL settings for display of dynamic net names is enabled, should be visible while push/shove wirebonds.
$ T9 k7 ?" Y4 F" o$ g1 v' n1112357 SIP_LAYOUT WIREBOND wirebond command crashes the application: v- p$ b' U5 z
1112395 CONCEPT_HDL CORE 縗BASE\G� for global signal is not obeyed after upreving the design to 1650.
- K2 _8 ^8 b, C$ z. q9 Z1112658 CAPTURE PROPERTY_EDITOR Changing Part 縂raphic� value from property Editor Changes Occ refdes values to instance
. }5 |4 ^5 n# \$ x8 e0 w* e- O- U1112662 CAPTURE PROJECT_MANAGER Capture crashes after moving the library file and then doing Edit> Cut
1 g' O: J, J5 a' y! d$ {; ?1113177 PCB_LIBRARIAN CORE Pin Shapes are not getting imported properly
1 Z. w2 T7 T6 {( S2 p1113380 ALLEGRO_EDITOR INTERACTIV Change layer to - option for package type .dra is not available in 16.6 release: g# n6 T6 u [ I) K- r R
1113656 SIP_LAYOUT WIREBOND Enable Change characteristic to work without unfixing its Tack point.# {4 c" Q3 v. W: p5 M2 E5 k
1113838 SIP_LAYOUT DIE_ABSTRACT_IF probe pins defined in XDA die abstract file are added with wrong location; B9 T. S, f& t8 ~# p$ v
1113991 CAPTURE GENERAL Save Project As is not working if destination is a linux machine
6 G5 v1 ]" R; _6 x# d+ B1114073 APD DRC_CONSTRAINTS Shape voiding differently if there are Fillets present in the design.
. A8 e8 h7 y+ P: w+ h1114241 CAPTURE SCHEMATIC_EDITOR Port not retaining assigned color, when moved on the schematic7 Z( {. a2 W: g2 H; z" b* E) [9 v$ H
1114442 PSPICE PROBE Getting Internal error - Overflow Convert with marching waveform on, z! i; [' x$ p2 T+ T
1114630 CONCEPT_HDL ARCHIVER Archcore fails because the project directory on Linux has a space in the name
9 J7 s) `, Z9 W1114689 CONCEPT_HDL CORE Unknown project directive : text_editor# t1 E# }/ |( d' A
1114928 F2B PACKAGERXL 縀rror (SPCODD - 5) while Export Physical even after change pin from A<0> to A; U3 K1 d2 O8 w1 x& U
1116886 CONCEPT_HDL CORE Crefer hyperlinks do not work fine when user use double digits partitions for page Border.
* j8 c* J1 m: p- s, \: j( O1118088 ALLEGRO_EDITOR EDIT_ETCH Should Plan accurate and Optimize be removed in 16.6?6 I! r. \7 j$ v) j: f
1118734 APD EDIT_ETCH Multiline routing with Clines on Null Net cannot route in downward direction
% D# M A) a% l U1 Z- Q- @1118756 ALLEGRO_EDITOR SHAPE Shape clearance parameter oversize values getting applied to Keepouts* S+ T, A$ x7 ]- B
1119606 CONCEPT_HDL MARKERS Filtering two or more words in Filter dialog box
/ f2 T! F) o0 o5 r9 K7 L V5 N% U1119707 CONCEPT_HDL CORE Genview does not use site colors when gen sch from block symbol
! ~- O- S4 _4 Q2 \1119711 F2B DESIGNSYNC Design Differences show Net Differences wrongly
; \3 P0 }) {& ] h1120659 CAPTURE PROJECT_MANAGER "Save project as" does not support some of Nordic characters.1 a- E$ b& q! k3 ?6 O
1120660 CONCEPT_HDL CORE Save hierarchy saves pages for deleted blocks.
( P0 V5 s9 D' i/ y1120817 SIP_LAYOUT SYMB_EDIT_APPMOD Rotate Pads commands not working while in the Symbol Edit App. mode
" w. {2 a9 T/ A0 J4 i- p1120985 PSPICE MODELEDITOR Unable to import attached IBIS model9 l5 c4 E0 u, h* v2 I. D/ L& J
1121171 CONCEPT_HDL CREFER PNN and correct property values not annotated on the Cref flat schematic% D* l4 o i' ~8 O6 m/ g
1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening.
/ C* v; d' \( l8 o1121382 ALLEGRO_EDITOR INTERACTIV Undo command is limited to two for this design
+ V0 `, B Z6 F) e$ I( X1121540 F2B PACKAGERXL pxl.chg keeps deleting and adding changes on subsequent packager runs
4 s$ E; ~& E2 L# Z! j' S1121558 ALLEGRO_EDITOR MODULES Unrouted net and unrouted connection when module is placed of completely routed board file.
W1 p/ [ t) H% x8 A1121585 ALLEGRO_EDITOR OTHER Drill Hole to Shape Same Net Spacing with Dynamic Shapes shows wrong result./ T- K5 ?$ v& x- g+ ?
1121651 CAPTURE SCHEMATIC_EDITOR "PCB editor select" menu option is missing
. W- t& D6 i3 [, ?/ H) d1122136 SIP_LAYOUT PLACEMENT Moving a component results in the components outline going to bottom side of the design.
, P1 O% h. D4 k. t3 }4 R3 ?1122340 CAPTURE NETLIST_ALLEGRO Cross probe of net within a bus makes Capture to hang.
6 n& p; J' Z+ e7 c; G1122489 CONCEPT_HDL OTHER Save _Hierarchy causing baseline to brd files1 d- ?- Z' a5 j% q3 N
1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically
9 E; `0 g! i1 d0 \8 u4 q. r1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one2 U5 C7 c; |7 T8 M
1123150 CONCEPT_HDL CORE property on y axis in symbol view was moved by visibility change to None.2 o; g1 ]* `! ]' q8 ^
1123176 ALLEGRO_EDITOR UI_FORMS Negative values for pop-up location is not retained with multiple monitors (more than 2)
2 [1 U& A3 T; B* Y0 \! n3 w( j( R' O1123815 ALLEGRO_EDITOR GRAPHICS Embedded netname changes to a different netname
% B- P2 ~& `" \% O$ T3 U1 X1124369 ALLEGRO_EDITOR INTERACTIV Sliding a shape using iy coordinate does not work indepedent of grid.
4 V2 X1 D2 h8 H# x. |4 q1124544 CONCEPT_HDL CORE About Search History of find with SPB16.5
5 H9 U- c- S# D1124570 APD IMPORT_DATA When importing Stream adding the option to change the point
P& v, y6 ]8 z& d1125201 CONCEPT_HDL CORE Connectivity edits in NEW block not saved( lost) if block is created using block add9 n. P% p9 X5 c! y2 f1 ?
1125314 ALLEGRO_EDITOR INTERACTIV Enved crash during setting of library paths in user preference
6 L! p/ z. R1 c$ a, Q1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux
- i+ ?7 Z0 N% W" }0 W# Q! A: K1125628 CONCEPT_HDL CORE Crash on doing save hierarchy
9 \( q4 B/ m7 c1 q8 _4 N4 k1130555 APD WIREBOND Wirebond Import should connect to pins of the die specified on the UI.; Q4 x0 h; x3 `( @7 |7 }
1131030 PSPICE ENVIRONMENT Unregistered icon of Simulation setting in taskbar2 o: Y* k0 r. i7 [ a! Q
1131083 ALLEGRO_EDITOR INTERACTIV Bug: 16.6 crash in changing the mode in Find filter window
5 `, t" _3 P7 a1131226 ALLEGRO_EDITOR PLACEMENT When Angle is set in design parameters while placement component is rotated but outline is not.
- q; w" |: [5 _0 z1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction.
; J4 X1 |5 b0 f1131699 PSPICE PROBE Probe window crash on trying to view simulation message
/ b2 {3 C* E; B3 i1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.
' n3 Q$ ?1 O, E: b1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command.7 ?% p! D( v7 L: m+ H; J0 R1 c$ ^* j
1132698 ALLEGRO_EDITOR EDIT_ETCH Slide Via with Segment option with new Slide command
) [% o( T- a. i8 I3 H. L! E1132964 ALLEGRO_EDITOR SHAPE Same net "B&B via to shape" errors created when adding shape
; M9 t) k% I" |& a( s8 x7 e1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top; d& y/ E, o% _" ]) R) F
1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode.
8 {& E) Q) z) O0 t( h; H: M1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property0 L9 F4 Q5 {( Z" i; [8 Q) J
1135118 ALLEGRO_EDITOR INTERACTIV Mirror and other editing commands are missing for testpoint label text in general edit mode.
% ?* w- R: F& D9 w1136420 CAPTURE GENERAL Registration issue when CDSROOT has a space in its path& ^& V c' Q' o
1136808 PSPICE STABILITY Pspice crash marker server has quite unexpectedly
3 y( S1 g' V! T, L% ]9 O1136840 CAPTURE SCHEMATICS Enh: Alignment of text placed on schematic page: n5 s# c' P! A+ l6 p0 ]6 M7 l2 {5 w
1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs
3 d& r! R. ]4 h1 F) F1 k& Y1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness
6 Q, g& F5 J: P- `5 K2 C+ x1140819 APD GRAPHICS Bbvia does not retain temp highlight color on all layers when selected.
8 x4 t3 x, M( m- @0 l7 K1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped: n# l; ?6 j, c0 m1 L |# a# o
1141723 ADW PURGE purge command crashes with an MFC application failure message
* @9 _: J X/ `6 Y7 P& w) m1143448 CAPTURE GENERAL About copy & paste to Powerpoint from CIS% K( c2 l1 ^# H" y) G# b4 {
1143670 SIP_LAYOUT OTHER Cross Probing between SiP and DEHDL not working in 16.6 release
' x: l+ w. ~9 y) K+ ~' z0 R1143902 ALLEGRO_EDITOR DATABASE when the shape is rotated 45 degrees the void is moved. M. O+ @1 q% t2 _# N
1144990 PCB_LIBRARIAN CORE PDV expand & collapse vector pins resizes symbol outline to maximum height
! F/ ?! {' O$ P/ z5 P: z3 p1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed; I! z5 ?% k8 P+ F4 x" I
1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case' p0 O. s% }& F: n$ V
1146386 ALLEGRO_EDITOR INTERACTIV Place Replicate Create add Static shape with Fillet shape3 N( R+ E0 Z* \. h" k/ X
1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail
0 Y: M) j5 D/ U1 j8 m8 C; f9 E! W1146783 ALLEGRO_EDITOR INTERFACES Highlighted component is missing from exported IPF file.
' B9 R" v! N% A: L" t: ^1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block( T- b" i9 D. {" p
1148337 CAPTURE ANNOTATE Checking "refdes control" is not giving the proper annotation result$ ?9 N3 D' G2 s$ m% [
1148633 SIP_LAYOUT INTERACTIVE Add "%" to the optical shrink option in the co-design die and compose symbol placement forms
6 E5 m9 w& v6 }2 M5 w' I( F1 |1149778 CAPTURE SCHEMATICS Rotation of pspice marker before placement is not appropriate
. ^) [: k: V4 U1149987 PCB_LIBRARIAN PTF_EDITOR Save As pushing the part name suffix into vendor_part_number value( p2 ^! x3 H: c% R
1151748 ALLEGRO_EDITOR OTHER If the pad and cline are the same width don't report a missing Dynamic Fillet.
% _3 Y2 {1 F& j8 O' z4 H1152206 CONCEPT_HDL CORE ROOM Property value changes when saving another Page5 @: B2 ?6 O9 h U
1152755 CONCEPT_HDL COPY_PROJECT Copy project hangs if library or design name has an underscore& c9 [- l# T- l8 \% z* ?$ x
1152769 PSPICE ENCRYPTION Unable to simulate Encrypted Models in 16.6
# d; [' ]: {& A3 Z, D! l5 x# G9 f7 O1153308 ALLEGRO_EDITOR DRC_CONSTR Creating Artwork Getting Warning "DRC is out of Date" even when DRC is up to date7 C( N$ U# @; Y
1153893 F2B DESIGNVARI 16.6 Variant Editor not supporting - in name
' r4 D% }9 N0 _( L1154185 SIG_INTEGRITY SIGNOISE Signoise didn't do the Rise edge time adjustment. V, w8 ?! ]( D9 e
1154860 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend7 m" m4 n8 ^) F. m w
1155167 ALLEGRO_EDITOR EDIT_ETCH Via structure placed in Create Fanout has incorrect rotation./ v) \$ k3 y4 X1 ^# q
1155728 CONCEPT_HDL CORE Unable to uprev packaged 16.3 design in 16.5 due to memory0 z( E9 G& P+ X' S& i: J) R
1155855 SCM SCHGEN A newly user-defined net property is not transferred from SCM to DEHDL in Preserved Mode
3 z6 L# p/ K2 R* r: t/ \, w. J1156274 ALLEGRO_EDITOR INTERFACES Exported Step file from Allegro is wrong. }4 r; t h9 P% h! ]/ D3 E4 \
1156316 CONSTRAINT_MGR OTHER Break in functionality while creation of pin-pairs under Xnet in Constraint Manager
7 h- c8 j9 A- [, h8 m, q6 k1156351 CONCEPT_HDL CONSTRAINT_MGR Loose members in Physical Net Class between DEHDL and Allegro
2 k' w( J8 n. Y- F2 R3 e; E. G1156547 ALLEGRO_EDITOR DRC_CONSTR Etch Turn under SMD pin rule check through pin Etch makes confused.
) w4 L, j7 s" n2 S1156779 CONSTRAINT_MGR OTHER Electrical Cset References in CM not working correctly9 \1 n8 r y" l2 F
1157167 ALLEGRO_EDITOR SKILL axlPolyFromDB with ?line2poly is broken) H9 M- V+ Y3 ~
1158042 ALLEGRO_EDITOR DFA DFA_DLG writes the dra file name in uppercase.
+ k6 d5 D, U: N* n) I3 ~+ X1158718 CONCEPT_HDL CHECKPLUS Customer could not get $PN property values on logical rule of CheckPlus16.6.6 t' w, _) I& J" n% g* g
1158970 ALLEGRO_EDITOR SCHEM_FTB Changing LOCATION to $LOCATION in DEHDL does not update the .brd file
4 a5 s2 ^1 R; H; k& h- d" r% }1158989 ALLEGRO_EDITOR INTERFACES pdf_out -l creates a PDF: f i; F* f' D N( T: o
1159285 APD DXF_IF DXF_OUT fails; some figures are not exported
5 F2 R5 Q, s2 k# v9 H$ r5 S1 h1159432 ALLEGRO_EDITOR SHOW_ELEM http:// in the Show Element in 166 do not have HTML link to open the Website
7 T! g3 e# V9 P7 n1159483 PCB_LIBRARIAN SETUP part developer crashing with
/ |! g# _) v4 I1159516 ALLEGRO_EDITOR EDIT_ETCH Unable to slide cline segment with new slide.
: f& f7 Z0 x- @' t2 ]1159959 ALLEGRO_EDITOR GRAPHICS 3D viewer displays clines arcs incorrectly
5 \3 Z1 T% Q* H( R9 S1160004 SCM UI The RMB->Paste does not insert signal names.
* L( c W) i. ]; g# Y. P4 T) B1160410 ALLEGRO_EDITOR DATABASE Lock databse with View Lock option is misleading
/ o( u( j4 N7 B( W8 x& i& i1160529 SCM SCHGEN Schematic generation stopped because the tool was unable to create an appropriate internal symbol structure2 B' M8 v3 x; W" Y% r" o* C
1160537 SPIF OTHER Cannot start PCB Router" _4 T) _ M% l' O3 q1 n0 W
1161363 ALLEGRO_EDITOR SYMBOL Getting error SPMHGE-73 when trying to mirror symbol+ M6 Z2 g% a# X( @0 B6 G
1161781 CONSTRAINT_MGR CONCEPT_HDL SigXp crash when selecting ECset in design* G; ~. L$ L! X- S$ t
1161896 ALLEGRO_EDITOR DRAFTING Tolerance value added for Dimensions is not working correctly (HF11-12)4 m8 D' I5 G& U
1162193 SIP_LAYOUT DIE_ABSTRACT_IF shapes in dia file not linked to the die after edit co-design die
& d+ }- g1 g5 W0 _( V; W/ n2 q1162754 APD VIA_STRUCTURE Replace Via Structure command selecting dummy nets.6 T# O: c7 \' Z- ?- c
O" p% N% ~# P5 c( bDATE: 06-28-2013 HOTFIX VERSION: 012" }! p0 V/ m& t; ^
===================================================================================================================================2 T2 @) p3 D' o" v+ C) c
CCRID PRODUCT PRODUCTLEVEL2 TITLE0 W1 C. Z: A) h7 T6 s0 P) r0 N
===================================================================================================================================
, w- d5 O( H, N) ^914562 ALLEGRO_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD+ q; s1 M9 z5 o$ h% `4 Y
1120397 CONCEPT_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files3 |' x9 ~- i/ C( N: Y
1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display
: D, J% o$ K" s9 ]) Y1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.' l9 A! h6 D5 u1 s& f
1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line- w9 |3 M0 ^% `8 a& m% [4 T# T7 v
1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.
6 h% k+ Y2 }9 N: \; ^8 n) J7 Y1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.
[" D4 `# Y0 X5 i" u/ y& Y1151458 GRE CORE GRE crashes on Plan Spatial
, o+ A- [0 `# e8 ^ j1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy9 x: d1 @9 `9 O3 P; E
1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]6 @8 H2 r& G# b1 z7 v9 S
1152475 PSPICE SIMULATOR RPC server unavailable error while simulating the attached design
- j G7 E* ?+ b$ I4 K1152737 ALLEGRO_EDITOR SKILL dbids are removed because highlighted objects in setting the xprobe trigger! B9 Z1 G9 w V' ^+ Q6 @
1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.+ K; d9 M6 R. o8 A; C) ^
1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places- U1 b7 J1 m1 \1 @3 l" ~
1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail$ ^) Y( M) O3 R- o* p) H0 u
1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.2 |$ n/ G# U" @$ P
1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer" m+ X- u' A6 z& v m
, W& F5 O& N& T- G
DATE: 06-14-2013 HOTFIX VERSION: 011! S1 q2 _: d9 j2 {
===================================================================================================================================$ q6 W f5 S1 }
CCRID PRODUCT PRODUCTLEVEL2 TITLE
2 ]' t6 X0 p7 {6 q===================================================================================================================================
8 T$ e/ c; U4 s. [982306 CONCEPT_HDL OTHER When plotting a PDF publisher output the page coming out half inch bigger in pdf
7 m$ k( Z, b* Y! @' ?1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers- p* M! l4 B# w- u1 d% g& i, x. H: H9 L
1093375 ALLEGRO_EDITOR PLACEMENT Align Module with Zero spacing value space the modules further away the modules should be nearer* Y0 I/ b" {/ h5 |
1103201 RF_PCB FE_IFF_IMPORT Wrong permissions to map file during IFF import" r$ J# _9 N4 ^7 T" t5 o. c) W
1106900 CONCEPT_HDL COMP_BROWSER Component Browser performance utility should honor CPM directives for include and exclude PPT- w! i; q: b4 B8 N3 H% _( ^) _7 c! h
1110178 ALLEGRO_EDITOR EDIT_ETCH Line Width Retention should be controlled via setting# X1 E* \# |7 {# g3 x. i
1110323 APD DXF_IF DXF out is offsetting square discrete pads.
2 o3 I6 x6 |* j. n0 ]1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board
/ v) z" ^9 o% f, E! R1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.9 r+ i1 x9 [7 J+ }, [* m: I) r) Q
1139338 ALLEGRO_EDITOR DRC_CONSTR The total etch length does not seem to work for Xnets after setting the variable "retain_electrical_constraints_on_nets") q) k& b! I6 |1 ^* m
1139361 ALLEGRO_EDITOR DRAFTING Angular dimension tolerance is incorrect when plus minus tolerances are equal.
$ J' P& X7 V8 u. n! v1141882 ALLEGRO_EDITOR EDIT_ETCH Allegro Crashes during diffpair slide/ _5 y, y8 J* l9 o$ V
1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero0 R ^# L& w, A# ?. [$ T
1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP
: S7 C' X. g( {) _1145243 ALLEGRO_EDITOR NC Duplicate drills found in the NC Drill output
- m4 f1 c( t h6 d. c* D1145260 SIP_LAYOUT DIE_EDITOR Enable "Copy" in die editor% w1 {' R/ L+ y: E; D* P1 C
1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL2 V N' p) G3 p, O( G( E5 N' P
1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.
; _4 e V) k. Z0 h, ^9 o% q1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added
+ H8 U; }7 R7 d1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps1 S$ b5 P: ~' s! f
1146865 ALLEGRO_EDITOR DATABASE Allegro crashes when trying to place mechanical symbol
% y# V& u( H. F' P1148513 ALLEGRO_EDITOR OTHER Importing a subdrawing file causes incorrect net name assignment.* X- r( A! z( w' y8 n0 G# e
1148734 CONCEPT_HDL OTHER Logical Symbol Text is turned upside down after extracting PDF by Publish PDF
$ N" Z; I$ W- C1149025 ALLEGRO_EDITOR INTERFACES IPC-2581 imports cross-hatched shapes as solid+ y% O$ ^$ x# W6 U
1149948 APD OTHER Stream_out hangs on this design -- hang processing merge of overlapping shapes using poly_deletecolinear_only()
( o* F. ~5 |5 V" Q) ]* R, C1150274 CONCEPT_HDL CORE Uprev from 16.3 to 16.6 is not preserving RefDes: {* S! U3 I" j8 @! q0 W- x
1151450 SIP_LAYOUT DXF_IF DXF export from CDNSIP missing symbols; {, t- ]+ E2 ^" S
7 Q9 t8 C2 C0 Q% N5 j
DATE: 05-25-2013 HOTFIX VERSION: 010
: p' e- E! c- T& \, N4 O" u===================================================================================================================================9 D; s8 p8 A2 W
CCRID PRODUCT PRODUCTLEVEL2 TITLE5 i& t: H7 i* j, x( A
===================================================================================================================================
# a5 e/ v4 c; c4 g1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer$ D$ M9 e1 Q3 X6 a8 K% g
1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border
6 Q v) R# e8 ?' s* H* P1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files& U* g" B6 @ Q( B' b9 R; W
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
. P/ A. c2 T8 Y# n1124610 PSPICE SIMULATOR Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.6
& r; P' m3 C m! H+ A7 b( ?( h1125330 FSP CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border
* N% Y6 W- |9 T1131775 ADW LRM LRM error with local libs & TDA
& c2 P: p. t0 ]1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP43 a9 u8 ^1 v2 o* h8 V( ]. |
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo
2 c; H- y) {8 ~' B2 v, _" N1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
/ U& Q9 }2 m+ j( b- M+ M2 F1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur% n2 f8 G, O) S; r/ t
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?
. Q* i/ w2 [/ S& g1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.( R/ c' u3 Q9 @! D: Z8 H
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor
& R3 k/ T6 V' C9 u1 E% |% w1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro
2 c# y& R7 q$ T/ L* U1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.
6 k) V1 y) T* w( w% G1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.+ L; F4 @2 F$ F3 j' X! F
1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash+ O! N s; t; J, y& A4 @" H
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
& W! ^% c: Y$ |, ^' Z" n8 |5 Z, w) M1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering$ F# C) V V% }/ _$ R
1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor L/ x# \# O A
9 _3 p* E2 k+ Q& x) {' L# S( K# O
DATE: 05-9-2013 HOTFIX VERSION: 009 t; O3 j% |, n
===================================================================================================================================
: m! g, q( w1 U2 XCCRID PRODUCT PRODUCTLEVEL2 TITLE6 j8 b4 _) _ v5 Y) g) D% }6 c
===================================================================================================================================* i- R0 [7 s( H7 w
961420 ALLEGRO_EDITOR PLACEMENT Regardless of the aspect ratio for room of side The QuickPlace by room command could be placed comp9 R. b$ k( B/ ]8 \
1079862 ALLEGRO_EDITOR SKILL Ability to create IPC2581 layer mapping file by Allegro Skill function
% m. l8 r: J8 Y: s1080734 CONCEPT_HDL CORE Repainting of grid lines during pan or by moving window show as solid white lines instead of gray da
( a' Z' | b5 ~/ o# ]7 w9 @9 G1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB# p! b) Q t: @6 @6 Z+ w
1107547 SCM OTHER v15.5.1 tcl/tk code not recognised in 16.6
- o9 K) l* J" T% T# O" R1110209 CONCEPT_HDL OTHER We can move symbols and wires off grid despite the site.cpm grid lock
( Q/ G* t0 Z6 U# K7 B6 b1117825 CONCEPT_HDL OTHER SHOW_CONSOLE_ON_LAUNCH throws an unrecognized directive warning in the schematic editor1 y+ r: N/ J. F) b
1118874 ALLEGRO_EDITOR INTERFACES Oblong pad shapes are not shown with correct orientation after DXF export from Allegro3 k- f4 @; K- B" { R$ f+ B
1121873 ALLEGRO_EDITOR INTERFACE_DESIGN Importing Bundles from Net Groups does not allow any further editing.
/ b8 E! I& T1 c V0 [0 n1122933 CONCEPT_HDL CORE Newly added Toolbars are getting invisible after re-staring Concepthdl
( U; p4 M* q/ d) m b% h1124587 ALLEGRO_EDITOR INTERACTIV The Shape Expansion/Contraction command should also be available in EE mode.
# N3 W; ~( g; ]- ]1125895 SIP_LAYOUT LEFDEF_IF Tool crash while moving the slider in the Filter options Macro tab form of the co-design die library manager# s9 y! g6 k" ~, D' k
1125962 F2B DESIGNVARI Custom Text in Variant Details dialog box is inconsistent
0 ^- H% @( x9 r0 Q( Z! F1126096 SCM REPORTS Two nets missing in report
. f4 P Z6 C6 q5 {3 K7 u1126134 SIG_INTEGRITY GEOMETRY_EXTRACT Attempting to extract topology hangs APD
2 { d( D; O% _5 v: F* }1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.! I+ a- x% u: ]1 h, j8 ^
1130280 ALLEGRO_EDITOR MANUFACT stream_out command in 16.6 seems hard coded to look for a design called stream_out.brd
( k- p7 A8 y$ g- y: }8 ~4 @; w1130737 F2B PACKAGERXL Error - pxl.exe has stopped working
/ x' |) e/ f4 B8 v7 g( b% Q K }) W; T1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters0 O3 C) O Y3 _! |7 z* X3 T' y
1131764 ALLEGRO_EDITOR EDIT_ETCH Line segment will not slide using the New Slide.
V& p; s# k2 i9 n/ u1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder.
5 U% g- X, c3 b1133311 ALLEGRO_EDITOR SKILL ?origin switch is not working correctly with axlTransformObject while rotating shapes
2 U6 d' w$ C3 L0 }4 v- E1133893 SIP_LAYOUT IMPORT_DATA netlist-In Wizard crashes
: A1 A& ?* V6 K( v9 }7 D+ @ L# {- u- v$ I; R9 X( o
DATE: 04-26-2013 HOTFIX VERSION: 0088 E- B ]& ?6 E% R; L6 }1 f
===================================================================================================================================/ W) X! Q. l4 |) q' F0 R5 E4 ^4 Q
CCRID PRODUCT PRODUCTLEVEL2 TITLE
1 X: |6 s$ a9 q& C7 [/ F8 J& f1 U) D- o===================================================================================================================================
6 G O- ^/ t) R2 p876711 ALLEGRO_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit% S" \% D4 ?' r" C0 W5 v- R6 S2 P
1080386 CONCEPT_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation
$ A% c8 c( o2 P M1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device, K7 C! R& x4 _. [8 S9 X
1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.
/ `" l# a8 E t: w- r+ {" b1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section2 X+ C. K1 q1 c! P; W5 g5 s) ?
1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running
. J) P4 d+ p1 O* e1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color.
0 r# b3 J9 B2 p/ J1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence
! L" }9 v; z5 s3 {1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred.7 E8 b6 H4 x8 @ j+ t$ `" m" c+ d
1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason: T4 I4 R J; H; \, Y. T1 W! o
1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations.
2 Y# J r0 ]3 `, E* G- M+ Y/ j2 G1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered?( x7 c+ L( ]7 X* _& c' O+ j
1120414 ADW LRM TDO Cache design issue2 S( i+ |; w0 W0 L* i1 U$ A
1121044 SIP_LAYOUT SKILL axlDBAssignNet returns t even when no net name is assigned to via. M6 M: S6 y6 b( e/ T" r \! r6 {. E
1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups7 B; y1 h1 f( r
1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it# p2 i X; X' P. G/ k( ~" y' q {
1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.
! U! U0 H5 x$ Z# R7 H- N; N1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced. ^* c1 E& e; ^
1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file. _) o) k" b' ?5 a0 A& |! P; I
1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable8 A/ D7 l7 \' d$ z- x G# }
1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file
( S7 b! A+ t5 i0 a1 \! `, `1123816 CAPTURE PART_EDITOR Movement of pin in part editor
. ~ l' s; B+ k- ]+ x1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 50
5 K9 _/ k8 w' i2 I& }! K
x3 E$ r& R' i3 q B, P: c7 ?6 pDATE: 04-13-2013 HOTFIX VERSION: 007
+ L) j) o/ W" A8 _# C===================================================================================================================================0 g( c; p& l R7 T# t8 I
CCRID PRODUCT PRODUCTLEVEL2 TITLE3 A: \) g0 v: X' Z& G0 S
===================================================================================================================================* P: K/ A: L5 G1 i1 Q' O+ L( {
1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die% W6 D [' W M5 Y$ Z5 R6 @2 r
1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.68 h0 L. `! g m4 S1 q& y
1112295 APD DXF_IF Padstacks� offset Y cannot be caught by DXF.
5 ?( \" |9 i F# @, Q% P( @1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components
! Q3 N- K8 \2 j& v$ Q, K+ Z: y4 D1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly
6 u/ S+ M/ |: }6 s2 A' P1115491 ALLEGRO_EDITOR SKILL telskill freezes command window
H) |3 i. |3 S1 f1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.
1 x6 {' ?' ]- ^5 u1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer.$ W! S, o8 V% g+ J
1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear8 }+ `; a0 a7 X+ `+ Y. V
1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks6 o9 f% o( F+ C
1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?1 a- a9 S9 [; d' @
1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh$ X, b ~2 l0 R8 y: D
1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh
$ _" e4 V! }. \9 u$ x+ i$ q% m1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors
+ k0 E0 a% k9 t& @- K/ P4 g+ w1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.6
* y0 N @* a1 | T0 `7 m) d1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently
( F' K9 P* w, l9 D& J4 i4 w1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps2 ?3 F5 c3 w# x# b: ]
1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks% T* b% r S `( m
1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment.
6 d B6 {1 b. M6 w+ c& j# A- }9 J |( e; U g& B' A
DATE: 03-29-2013 HOTFIX VERSION: 006
, \! d) \8 j/ {; J/ E" ~& y===================================================================================================================================
/ ^( @- \+ t! o) z/ x* k# pCCRID PRODUCT PRODUCTLEVEL2 TITLE
; r& [) M+ z. [=================================================================================================================================== n' y: A/ ?) d. }
625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.2 u$ u/ n: g! M F o3 [3 o/ L
642837 PSPICE SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep
7 o) p6 W. x( E( a650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".
2 k5 U+ v" D- b- ^653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend- h, k o9 |5 e9 H5 X: R( a
687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect) E# \$ t9 x3 k% \- B# _6 o
787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics
0 z1 o0 }- y. @. I0 q t: s% B825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other
6 I. H% _* Y# ]1 s: Y @834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming
) |% M6 s& t" R8 U3 U835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.
1 K8 R, J. G7 l2 A868981 SCM SETUP SCM responds slow when trying to browse signal integrity& \" K/ v/ w# `4 v* e
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide, h! F. w, y! P; B: _
873917 CONCEPT_HDL CORE Markers dialog is not refreshed
! b4 g" ~9 w4 ?( Y h887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License
+ s$ `2 d: s2 F, ]5 O9 @' x5 T8 z888290 APD DIE_GENERATOR Die Generation Improvement4 n$ k- q4 j4 V( g$ }7 t* I
892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator6 d$ t. q, x% L2 E O& U
902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice
3 ^8 f; }1 k) D) @5 ~$ f7 l( j# p908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM
- K* {& m& s1 G6 H) W. k, ~922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols
! {0 q5 O: `5 m) g; N- g923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences
0 b* y2 V; [6 N S5 P935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC! N9 i& {/ s, e# R; A$ S( y* q
945393 FSP OTHER group contigous pin support enhancement
' D2 \" y7 _3 n& @6 u969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database/ r @. X7 \# |- T6 J
1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes* \! U4 B2 w3 e6 X+ T& B' I
1005812 F2B BOM bomhdl fails on bigger SCM Projects
2 c) k- A8 k4 f# y1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture5 {' R. @& @2 G" C+ t7 H9 P4 W
1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names' N9 g g# j% @ \6 Q
1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net
+ h( _1 F8 l0 R# r0 ]0 K1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical, X4 A' j- y5 \% W
1032387 FSP OTHER Pointer to set Mapping file for project based library.
6 E' W0 f9 ?: Y6 u' O6 Z' r1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with 縋LL PLL_3 does not exist in device instance�7 v2 Q/ c' B, @. m, _' Z
1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart
& J0 l6 \8 U7 V! Q. |1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding
1 i" I1 | v) |" {1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.& n$ ~4 Y! G7 Y0 I( l* @6 S
1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type
( r( Y( }. F9 n) E1 R1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll1 Y2 P( |+ Z$ Q6 Z) a
1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation- {: i% ~" c& `+ z/ ]+ n
1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects
5 M' \3 P8 }* u1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus
$ M, H% \7 a1 `% a" j6 `1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts
+ J8 A6 s% [6 L/ B1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs( Y$ z- V$ O6 v
1065636 CONCEPT_HDL OTHER Text not visible in published pdf
1 j# J2 ]3 x. ~) D1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings3 i! c9 f& e+ {: s- C0 H! g* b
1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary
" f/ m X$ B# ^6 K" T1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts
: k: E h! a2 q, [ ?: M1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic
c- P, }+ W: i1 t1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down
2 `3 O, u; b X8 D3 ?1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45* ?. g2 T! v' r) \7 `
1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal9 l& P, w; n* J) ^% ?6 a/ d
1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check
1 H& s" s4 k, g- s1 b$ ~8 O1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.# F( s/ X) {6 E7 D; q( X9 n
1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)
: P4 \1 M( u) W# {1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die- G0 h/ @4 e( H& V/ F" ]5 p( B
1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic
. J0 V8 b2 Z( g& x2 O5 _1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut- R/ B8 I4 H: j1 h+ r) J Y* F% n
1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects
! r: F* P, O( T: j1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format
$ D) h( O b: H% w/ o1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net1 n R) k* A$ B/ I$ ?" P
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic+ w* F: C6 M5 o/ O
1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible
7 z6 `0 F' t1 W/ W6 X. F8 v& c: i: m1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.& L* E E2 [! g) l
1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.( s( P |2 P4 Y& K
1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors1 `9 s7 ]: _! N" P9 K
1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.
0 K! S8 x& g+ E# H1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition g0 P* x# L1 g' x+ g/ x
1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor" m* c+ m0 `5 q! }2 @
1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options
- ]; r; U! {) m1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5
. }+ C5 R$ |9 n* m: Q2 e- {1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.
6 H! P4 Y7 B8 f. @$ x/ {1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate2 a& ?% ~1 P5 q4 ]! e3 x
1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3, s, O! M" [' t! W4 }, B$ ?0 `
1078270 SCM UI Physical net is not unique or not valid$ m' T9 b* L/ O- _" x
1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted3 d; z/ O! l* e8 b1 @9 A- E
1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle* @5 d3 T; p8 C w# L
1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs
* q! X, k8 I2 u8 T k1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage"7 w8 f) c0 Z: T! P- Q) p* y8 {
1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters3 J! }% h" P' v- i* I! C. \! x( ?
1080336 CONCEPT_HDL CORE Backannotation error message ehnancement
2 ^% M7 {8 @5 }$ w9 x1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using OrCAD license1 p! H& ?2 ^6 M% W/ W, y! C; Q1 G. q
1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd
, q4 B6 @) \% n8 B) L1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error8 O- n* K0 N* ?' w) {
1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.
5 i* ]0 V/ R- ?" D& u# y1081760 FSP CONFIG_SETTINGS Content of 縁PGA Input/Output Onchip termination� columns resets after update csv command' a: }7 H% P5 E" W
1082220 FLOWS OTHER Error SPCOCV-353
! c, M z8 G1 w. ?! a* `0 w+ d1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.9 j: i: K, d9 V: {8 M
1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command" g, L5 F) J5 z5 Y2 i* p
1082737 CAPTURE GENERAL The 緼rea select� icon shows wrong icon in Capture canvas.: ]# @8 H. P" E. r- x/ H( _
1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name
6 j1 `5 J7 J1 `( {) ^3 E1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way/ f1 R, P) @) \9 p- V! D p
1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher+ O! C: m e2 u4 J0 v
1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI
- F5 ^7 b( R! A/ S; k2 w+ s, u1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file
' m* u: ^7 U$ K5 g9 n7 ~1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.: o0 _( ]3 d4 j" W a
1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates: L, E5 p, l3 B7 y. H
1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters
9 n s; f$ f: V5 W# Z; Y! o1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.
/ B0 Q) a' x0 f# O# R1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results
2 ]( e+ O% m4 u* B+ j1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.
6 P8 q! L9 o! r6 \3 ?1085891 ALLEGRO_EDITOR INTERACTIV about DRC update, ?4 L6 J x, |- L, I! H
1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO8 W- M: }1 T; ]3 k; [( g
1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working
! A7 J4 Q$ m8 _1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.
) E6 x( o1 m2 v' b1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design
3 N5 a/ Q: Y7 ~, G8 a' H1086749 ALLEGRO_EDITOR MENTOR mbs2brd: DEFAULT_NET_TYPE rule is not translated, C4 T$ W! w+ l. v/ q4 c' b
1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins+ E7 [9 M, l; E& `
1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity! |( n# i8 ~* t' G
1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.. H5 X+ o3 h3 t* K. S. n) ? j
1087221 CONCEPT_HDL OTHER Part manager could not update any parts.& b4 ?9 p7 n' ]2 O2 j8 f n
1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space5 L( X$ Q& t- g/ _6 N; v" p7 T
1087295 SIP_LAYOUT EXPORT_DATA Enable "Package Overlay File for IC" for concurrent co-design dies too$ Y* W4 R: n2 r* b/ G
1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice
) O8 [7 P, x7 a5 e1088231 F2B PACKAGERXL Design fails to package in 16.5
4 v& t7 e+ p0 w* j$ O1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.
0 Q9 l* }% n m, m o, V1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor+ f* v) u3 @8 K6 f& c6 f* {/ x
1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager
0 _3 v# n, u) e; M; {( H1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?
. h7 C6 l2 @+ b) t! V" M! x1089259 SCM IMPORTS Cannot import block into ASA design
/ J" Q8 q0 |: m' h2 h1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form; _. m& p1 v+ D4 g8 ]) d3 E
1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project1 r8 W8 O9 l4 }/ N# Z* a
1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory
( Z7 [1 r5 C7 p5 D* g" N- j% R# }! ?1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.. ]. i3 k1 G" a* w
1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165
8 ]' n, ]# [2 N3 r7 I! V1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.( v, J! s# l& }5 l5 ?
1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-22
2 \# j9 u# t1 K1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.+ B$ d" E! o. |& C
1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.# w6 e. `7 _5 A; {
1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled# n$ a- K9 ~/ e9 K- `$ ^1 ~
1091359 CAPTURE GENERAL Toolbar Customization missing description
0 b* d7 D. o Q0 u7 l: T1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive
5 S" `) D. j; y1 z2 X9 M. d* R Q1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time# d X9 o- R8 m6 J6 `8 P5 ^
1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5
2 [; g; G) p1 S1 m+ N1 X* A1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design1 L* Z2 K: S% D9 n8 \
1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled" \8 t2 {$ D, ?, Y- N& k: w
1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters
X+ G# p! I, t5 g" i/ n1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error" H1 }( o+ b, \" B/ G6 V y
1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder
{0 t- N9 i% Z1093327 CONCEPT_HDL OTHER Getting error SPCODD � 369 Unable to load physical part in variant editor
' I' ^4 v6 G# P# }6 m; A( \4 Z& l1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.9 k" S# g. O. B' U/ z# V. s$ t
1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time
$ p- e/ f" c# |2 A) j1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.% o& U0 A+ _8 m3 {
1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?( \& i) m. D9 @- r* J' C$ {
1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic1 T0 N/ b5 S3 u) \% U- e0 h+ j
1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5
1 q' F: t4 ], S* a1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet
4 Y7 F& e# P) Q; u8 }' ^! U8 h1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die( u0 w# \6 K7 H7 c
1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block
; s* _ Y6 S' t, n/ t1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3' Q! I1 _! ?- `+ o" M( O; x+ u
1095861 F2B BOM Using Upper-case Input produces incorrect BOM results$ R* ]9 c) O+ X! `4 q4 m" }2 c
1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import
6 B) F: t& ?" D- u! }. T, L$ q0 O1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically
8 [0 j5 _4 i0 R( V7 X0 b s, Y1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias
. m* f5 `9 z: T" H1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate
8 N) y. v+ C% M1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors
/ t+ O& E# C7 r4 E/ h1 a1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL+ `! ^, {: l! o
1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.
' y: d( f/ {9 j5 o, ~5 W1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side
, S" ]# [) c: o8 T T; o, _+ S1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command: O5 }, L9 ~1 K$ s6 u4 E% |) h
1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.
% F4 W( Z' Q5 i) r; K) g0 F v1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives6 V' N! p" r, _2 q
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork2 ^( e6 B% N m5 _* t5 s' N
1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts: D! I1 m _6 x: A# R" D# ^
1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy& v3 s# J6 J9 W6 N& Q- G* H4 p
1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.
l4 ~+ V v$ Z6 f% p1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties
1 }( Z, t) J# W# o1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6
" H. |0 z1 e* ~, t" T+ R4 _6 X1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad4 k9 C9 E: B. E& B E) l
1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P38 V4 L4 f; O* g& w8 z8 R6 M
1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad
D+ t7 |4 T2 b- J1103703 F2B DESIGNSYNC Toolcrash with Design Differences
J; W d+ U u" C6 c v1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view
6 i8 o; h: Y% j1 {1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.62 I2 q0 l( T# p& R1 @
1104121 PSPICE AA_OPT 縋arameter Selection� window not showing all the components : on WinXP! X: l& B9 t. [0 R$ b- B. R
1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly
& [ Y$ Q% E% {3 i9 P) T3 G4 h1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM
" _, u$ f9 u3 h6 U; l3 z1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule." ?, Z/ C/ r3 N& y& ^7 e* t
1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.3 V4 F% a; h$ V
1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form! V L( v) P' I& i
1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part
: j& m5 `" x# r0 G. s2 U1 T1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked
4 [' Y% r4 G% Q% T1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax
" E, O1 {4 w2 c. n, B1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.61 C0 \ @0 j# l7 p& P) V
1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only
3 ]1 k* A, o0 `7 p. |0 M5 ~: q d1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid7 g- M x* i/ B( \2 E! G) a
1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.
' k0 p/ @- s8 H2 u: R# f2 {1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param
% o% O+ Q1 T4 A& I) t) I/ g1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish: m/ [, |9 d/ ^* \- u( ?& z, _* w
1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).7 k1 G7 _; x5 a' K) A$ i* Q
1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke
% e/ T" g9 F1 }( W1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.
9 h- u8 {( I, L7 h4 e1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode
! S9 c) i% x+ }8 `3 K, R2 v7 U6 O1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs* k! M. H/ f' C, }7 \& p
1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6" M& w! ?" Z. r5 X* [3 {7 `
1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.
: c- Q4 Q, u) R1 B1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
: ~# g+ g/ P& H1 D$ i/ j0 b1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6
: E' i5 O+ a: i; t A8 M1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset
6 _: m) c, P$ Y' K1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters* D X+ W, V+ _# S l5 _5 s8 H
1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend/ ^& L2 Y i: X4 v2 Q/ j
1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP
0 r4 D6 T* ~$ F& X \+ C4 w1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint7 E( t" O8 Q4 W9 w
1112774 GRE CORE Allegro GRE not able to commit plan after topological plan& g) a5 a0 K7 X6 [8 l& d- w- J5 }
1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.) k, C+ l( p5 m* k4 w6 `
1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file$ V1 z1 q; d* ^1 F
1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6" ~" O- R2 @$ R' F l& F
5 C* S3 z; _# z( L7 b0 A( g: i* \DATE: 03-7-2013 HOTFIX VERSION: 005; B& l: ]% o7 X& x
===================================================================================================================================
( K2 r7 }. `7 K* z( tCCRID PRODUCT PRODUCTLEVEL2 TITLE; X b1 Y7 Y. H3 }; P7 R
===================================================================================================================================" z! t2 X; C- L8 r) `
1067770 IXCOM-COMPILE COVERAGE Assertion failed: file ../covToggleCoverageXform.cpp, line 11029 P( Y! ^! N% D6 i- m, E
1100442 ALLEGRO_EDITOR PLACEMENT Placement queue shows components whichs are already placed( Y0 m l* ^* l2 B
1101555 ALLEGRO_EDITOR DATABASE Allegro Crash frequently
' u0 @$ s. n! t' D1104011 ALLEGRO_EDITOR DATABASE Place replicate move group of a modules leaves traces behind( | N7 f0 t% V( d
1104065 SCM NETLISTER SCM 16.6 has problem generating Verilog with existing sym_1 view
y/ d8 g6 r" `% A1104605 F2B PACKAGERXL Pins of function swapped part in block not displayed
]7 b) u5 E& Y7 }- s2 v" T& i# Q1104790 SCM IMPORTS Corrupt data once SiP file is imported into SCM
% ?! G& ?1 x4 L5 Q% m2 x5 j1105066 APD IMPORT_DATA Import NA2 worked in 16.5 "035" but fails in 037 and 16.6
# f, \& S& z5 N" y' I1106323 ALLEGRO_EDITOR PLACEMENT Unable to locate specific placed symbol on this board as it becomes invisible after placement.
9 H) v2 K. T& t1 d) N1108032 CONCEPT_HDL CORE 'Find' option does not list all Components in the Design0 r' f6 O# S+ c4 U! n4 T
1109080 ALLEGRO_EDITOR OTHER Window DRC is not working in OrCAD PCB Editor Professional
* b9 y9 Y! f5 [% _, D
- V D. J0 Z5 }8 M7 @% }DATE: 02-22-2013 HOTFIX VERSION: 004
_. ^3 X& ?9 E5 _8 c f* B$ r; G===================================================================================================================================3 I/ p! R+ }" r' X# r
CCRID PRODUCT PRODUCTLEVEL2 TITLE2 @0 u3 }/ h/ i7 L7 L$ R
===================================================================================================================================2 ^: q6 a6 l8 H4 a9 Q& R
1081026 ALLEGRO_EDITOR GRAPHICS 3D Viewer do not show the height for the embedded component correctly
% q" k1 d' j+ `3 d1 r1095225 ALLEGRO_EDITOR EDIT_ETCH The Constraint option does not work from right mouse click>Options>Line Width > constraint during interactive routing% b. F9 P1 z* r7 [7 ?: h5 Z0 {+ h. p
1096356 ALLEGRO_EDITOR DATABASE Cannot Analyze a Matched Group in CM
! I3 `3 Z/ Q' k7 r" F1097481 ALLEGRO_EDITOR INTERACTIV Allow replace padstack command in design partition
! q: p ]( ` x( C/ o! u1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend1 M1 ], ~/ o5 ?% x0 g( O& o% q" Y
1099958 ALLEGRO_EDITOR PAD_EDITOR Library Drill Report producing an empty report% n4 |8 R Q# U
1100401 ALLEGRO_EDITOR OTHER Invalid switch message for "m" for a2dxf command& {& ^, V& P- O. ^# n" u3 ^2 s
1101026 ALLEGRO_EDITOR OTHER utl_perftune hanging in fpoly_RemoveVerySmallSegments(), causing shape degassing never to exit.
: d9 R- u9 l( m/ j1101064 SIP_LAYOUT SHAPE 'Shape force update creates a rat" ^+ U! C$ q: K/ }3 N n& t7 A
1102798 SIP_LAYOUT OTHER Stream out puts offset pad in wrong position if pad is mirrored but not rotated.
8 g5 g7 V" X! \- u8 m2 f
* ?2 x" v# p- O9 |1 B! UDATE: 02-8-2013 HOTFIX VERSION: 003
8 |" B7 O$ \5 \0 h" J===================================================================================================================================1 C Y( [' @$ M
CCRID PRODUCT PRODUCTLEVEL2 TITLE
6 O% {+ Z6 K' s1 r( f c4 t' D8 Q===================================================================================================================================: ]' N- U/ _: Z' G7 M3 G
1077728 APD EXTRACT Extracta.exe generate the incorrect result
$ i* t3 Q+ W- ?* I- ?* _1084711 APD DXF_IF Padstacks with offsets cause violations in Export > DXF% P- g3 H9 R! s: o5 I& @1 i1 S
1090369 SIG_INTEGRITY LICENSING Impedance value not updating in OrCAD PCB Designer3 v; b1 o& [* g: r
1093050 ALLEGRO_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing.
8 Z! [ |# H% T8 b6 o1093563 SPECCTRA ROUTE PCB Router crashes with reduce_padstack set to on
9 `9 T$ X9 |! K; W/ M1093717 APD DATABASE Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent, Q6 m7 c. f( _6 j) z2 O6 H6 `, U
1094788 SIP_LAYOUT WIREBOND Wirebond edit move command, g/ N8 E6 f9 A& H- h" d
1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor2 I$ L7 i2 K" F0 H4 T$ \
1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn縯 show up after 縎uppress unconnected pads� option.
' W; p- m2 e3 v9 z% V; d/ J$ F0 d1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff3 M% d* A5 a: u0 t9 g" i
1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible1 l+ Q$ z9 r' X$ s# J; k' L$ C
1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35
# O( A: c0 B( b. E R8 j1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.
( Q( ]# r; t. T2 x/ S+ _9 ?$ M" f1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes. s9 N2 i) u& _
1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.
( K4 b& B s. B- x# u5 i( C/ c4 L% O8 i6 Z: \/ {3 G7 w
DATE: 1-25-2013 HOTFIX VERSION: 002( a& Q% S& q; y5 J4 X7 g
===================================================================================================================================
5 z! c" D4 l' b1 K ^CCRID PRODUCT PRODUCTLEVEL2 TITLE9 P9 T1 X: o7 o* A* ]# J9 t7 c" {
===================================================================================================================================
/ P: F8 E1 U- x* @ M1 v7 |491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute' Y8 e: y Q! N+ \ s8 n0 w+ d
863928 ALLEGRO_EDITOR INTERACTIV Segment over void higlights false "nets with arc"
6 m6 f# \$ ]9 D8 [* j1067272 PCB_LIBRARIAN CORE Unable to retain the symbol outline changes4 ~8 ]5 h$ \. B+ q: M* f) I4 |! b
1074820 ALLEGRO_EDITOR GRAPHICS losing infinite cursor tracking after selecting the add text command with opengl enable; X" j+ Q/ }. J5 P
1075622 CONCEPT_HDL CORE PDV Edit Symbol in DE-HDL all editing functions disabled since Hotfix 33
6 X5 l& q" Y8 Z' d: a% g1076986 APD WIREBOND Wirebond Adjust Min DRC does not maintain the finger position in the same sequence
8 ]- N0 X* D1 o! g) j( _( D1078031 SIG_INTEGRITY REPORTS Requesting improvement to progress indicator for report generator$ ^. M$ S* M. E. r% H. X
1080213 SIP_LAYOUT WIREBOND Wrong behavior of Redistribute Fingers Command. i9 }; B' c D, B5 J
1080667 ALLEGRO_EDITOR GRAPHICS Allegro lines with fonts not displayed correctly in 16.64 {# O' m* L8 h1 u1 g* v3 p* S
1080982 CONCEPT_HDL CORE Crash of Allegro Design Entry during a copy of a note.
* \3 g1 ]0 T0 `3 ^: I6 r" M. K$ q1081200 CONSTRAINT_MGR OTHER In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete.
& B u% z1 q/ Q: R- K8 K! x4 [1081553 CONCEPT_HDL OTHER Model Assignment can not translate M (Milli-ohm) property value of DE HDL.% q: f1 _& F( ~/ w1 P" K6 }) ~8 n
1081696 ALLEGRO_EDITOR INTERACTIV Compose shape not working when radius is set to 1.0
9 m' D2 G, d: H4 _, x: o4 _1082595 ALLEGRO_EDITOR COLOR Infinite cursor remains white even we change background to white9 W+ }; D# |2 H7 F# x8 D
1082704 ALLEGRO_EDITOR GRAPHICS infinite cursor disappears when using Display>Measure
$ y( }: a! h7 f- U2 t1082715 SIG_EXPLORER INTERACTIV Single line impedance for BOTTOM Layer is not calculated in cross section upon changing the thickness of dielectic layer
2 \ u& L0 ]' m' ~! H- d8 ^1082774 ALLEGRO_EDITOR TECHFILE Import techfile command terminates abnormally when importing a generic techfile.
+ K/ T; I. E6 w1 G0 L+ v4 u' e1082820 CONSTRAINT_MGR UI_FORMS The configure generic cross-section pull downs do not work.
6 W3 s* D0 ~: l- k. g$ F5 Q1083133 SIP_LAYOUT INTERACTIVE SiP will crash when using the beta Pad Rename command to change a BGA pads name.6 v4 r5 f, U9 w, P3 C) v/ }9 l
1083158 ALLEGRO_EDITOR GRAPHICS The cursor chage to Arrow head for Shape Select is more sensitive to location in SPB 16.6/ e9 Y0 k1 H: B
1083533 CONCEPT_HDL CONSTRAINT_MGR Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout2 P' O$ \, Q+ Y8 O& D. E' f
1083637 PCB_LIBRARIAN CORE Save As is not renaming the NAME in the symbol.css file: c* C1 W# P* u+ J* t
1083934 ALLEGRO_EDITOR PAD_EDITOR Error(SPMHUT-41): File selected is not of type Drawing.: y& G. S0 f d- J
1084148 CONCEPT_HDL CHECKPLUS The CheckPlus hasProperty predicate fails in the Physical environment.
' `$ b1 R- G) o% [) Y; g1084166 SIP_LAYOUT DIE_ABSTRACT_IF Updating sip layout with new die abstract doesn't properly update IC_DESIGN_CELL* properties# E6 z( L3 L: K# q2 U
1084285 CONCEPT_HDL INFRA Corrupted dcf was never fixed and caused PXL error
6 @3 r0 u3 O3 b) ?& y+ I: w1084441 CONCEPT_HDL CORE Assigned net property value changes to numeric* @7 }& I; S/ D* W C
1084542 ALLEGRO_EDITOR DRAFTING Dimensions associated with frect doesn't rotate with the symbol.! Y" h0 p8 q4 `4 e: p/ f
1084736 APD IMPORT_DATA Import SPD2 file from UPD-L shape Pad and text issue% G- }7 ^+ |2 h# S
1085008 ALLEGRO_EDITOR INTERACTIV Relative (from last pick) option in the Pick dialog not working for pick command
4 }' e' R; x6 n) N5 L1085139 ALLEGRO_EDITOR GRAPHICS Infinite Cursor disappear during Add Connect if Infinite_cursor_bug_nt is enabled9 u9 [0 l/ n2 f: h% r4 S8 N: s2 _
1085187 SIP_LAYOUT INTERFACE_PLANNE netrev with overwrite constraints fatal error; P. M) s$ X% c% h I; r* S
1086402 ALLEGRO_EDITOR GRAPHICS Infinite cursor dissapear when using command like add connect or Place manually with opengl enabled.
& c2 S7 t1 h D; t$ @% f1 z1086905 PSPICE SIMULATOR PSpice crash while simulating circuit file with BREAK function
/ v% \0 d: |$ D" q5 [3 W6 j1 V1087770 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes on a pick with the slide command.
) C7 ]. s" d6 u; _# r4 P, c3 C1088412 SCM CONCEPT_IMPORT why reimport block adds _1 to the netnames?, w. u% K, J6 {1 u9 S% _4 [
1088958 CONSTRAINT_MGR INTERACTIV annot create Differential Pairs out of nets that belongs to a Net Group0 P2 \: N. z# B0 E' p+ H4 B8 Q; g
1089336 ALLEGRO_EDITOR GRAPHICS infinite cursor and pcb_cursor_angle3 V$ _* ]- |" o9 t* q2 h
1090689 ADW LRM LRM: Unable to select any Row regardless of Status1 x+ D U' l: N# u7 n& v+ W
1090955 ALLEGRO_EDITOR OTHER Cancel command crashes PCB Editor when add rectangle
3 a+ l0 m) a6 p& {8 W1 q! Z1091047 ALLEGRO_EDITOR REPORTS The "Dangling Lines Via and Antenna� report seems to be missing vias that are antennas.
, L4 n2 Q/ z; y9 |5 C) F, d1091218 ADW LRM LRM is not worked for the block design of included project
: [8 O1 G5 j! u5 J& g2 L+ W1091443 ALLEGRO_EDITOR OTHER Crash when toggling suppress pads4 N' E$ k' a j' a
1091706 ALLEGRO_EDITOR EDIT_ETCH Allegro crash while routing after setting variable acon_no_impedance_width' ^. {! S7 X& c! Z {
1092916 CAPTURE OTHER Capture crash
2 y) x a* }: {1093573 ALLEGRO_EDITOR DATABASE team design opening workflow manager crashes allegro. possibly corrupt database
/ W" I6 ? [& a, Y# E' @, V# }. m4 H
5 ? H+ ^. f( g: v7 @$ LDATE: 12-18-2012 HOTFIX VERSION: 001$ v$ L& b" }1 l. W* \
===================================================================================================================================
, a& N1 f6 G5 r! s0 m0 A3 ]. oCCRID PRODUCT PRODUCTLEVEL2 TITLE3 [: }. u9 f$ w3 F* F
===================================================================================================================================
- F& g" j! Y; ?! s# B% {" m501079 ALLEGRO_EDITOR MODULES Enhancement for Module swap function similar to component swap. s! c+ d: r- c* o; \4 m3 \0 J
745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched
9 j" h( ~! d* b9 M( ^+ m' o- A825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted
* d. z& M2 i0 J3 t; T2 e871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash
, e" H- T }8 j8 ]2 C$ `5 E7 Q891439 ALLEGRO_EDITOR INTERACTIV moving cline segments2 ]6 C: Y( ~7 M5 `0 A% A
898029 CAPTURE PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore
3 z$ V, n; v# a) j9 P, ^923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties* |: Z+ P, G' B2 u; k
938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic D! A' b9 y J5 {0 H
947451 ALLEGRO_EDITOR INTERACTIV Allow the tool to select multiple shapes when assigning a net to more than one shape.9 g5 ?* s; n# o1 J5 l7 R
968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
8 B; \2 K3 ~$ {! B976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor6 S, X# n6 I9 V
981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected. z7 P7 G2 {+ Z' O$ J
982273 SCM OTHER Package radio button is grayed out
p3 C8 g/ m! \+ c988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command
1 v9 v. P, ^- L) s8 H' u9 ?989471 ALLEGRO_EDITOR INTERACTIV Functionality to zoom to the selected object in Pre Select Mode, B; V4 t' {/ k
993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).) \6 K% T0 S" f* ~+ N3 \
996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections
3 S" ]3 d# n* F7 u0 ^8 r8 l& M997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?
( I& X9 z& r4 j3 O* a/ L1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model o' }% K! H. W9 n% q! M0 e
1010124 PSPICE SIMULATOR Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs# D. _' M6 |1 ]5 c0 O1 C
1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg" j( l# [' D. C! Y2 m: U
1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.1 S! O, A, q( H7 p) e( _
1016859 SCM REPORTS dsreportgen exits with %errorlevel%% l6 }9 o" N7 I1 _- O
1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin
@! X2 p2 _' J2 B# _& }8 Y1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs
4 E+ `4 R$ G9 p" G$ r1020798 SIP_LAYOUT SHAPE Shape not voiding on layer 2 causing shorts
- J5 i) ^* Z$ N6 K& g1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
7 x( @; e4 B3 i; N. v4 L1023774 APD WIREBOND After "xml wire profile data" is imported it isn't reflected to actual wire.
2 @& G0 y& u S1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button
$ F; C, F$ H' C9 E+ B1024239 ALLEGRO_EDITOR INTERFACES DXF pin location is moved when I execute DXF out* K [$ }; r. h# V: @/ u
1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist3 p" v1 e- c5 Y7 T, [
1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed) M+ e; u* ?& a* S2 l/ h u! Y
1035624 CONCEPT_HDL CORE Options pre-selected when launching base product
z* ~% @" t1 t8 ^' R1035896 SIP_LAYOUT ASSY_RULE_CHECK Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly% h$ j: X' ]' [- j2 r
1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it. y0 }" {+ b5 U; R7 U* Z6 f
1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file): O1 T: B0 }6 R# E
1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol
. o' v8 a7 f: s9 v3 u+ p; p9 e1038285 SCM UI Restore the option to launch DE-HDL after schgen.2 r- ?8 {& c8 U7 o
1038371 ALLEGRO_EDITOR INTERFACES Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."
& E& t1 Q5 V, D ]1 Q1038577 ALLEGRO_EDITOR DATABASE Modifying Void crashes Allegro
) T6 E5 l C2 G; U4 f, g6 K& ~8 H1039112 ALLEGRO_EDITOR ARTWORK Antietch and Boundary layers deleted when Match Display selected/ V. S1 b, J$ K' K# {& t' X
1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing
! q) G* S& }" i4 z- x1040653 ALLEGRO_EDITOR DATABASE Cannot update netlist data, ERROR(SPMHDB-121): Attribute definition not found.
) Q# y w/ c" O1 }1 i9 Q+ B( d ^1041368 APD DEGASSING The Degas_No_Void properties assigned to Cline does not work.% [2 ` L+ O( }* `" ?. Q( A H, h
1041864 ALLEGRO_EDITOR MANUFACT Allegro crashes when opening the Backdrill setup menu: Z4 G2 C1 }0 {' ~# s) w
1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab.
( ^8 i" U7 K, H% g9 A: a, n1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow: U+ z& v2 }3 [
1043861 SIG_INTEGRITY REPORTS Derating values are NA in bus simulation report when derating table is not in working directory
( ~' e, `3 X. ]+ i* o& k1043903 GRE GLOBAL This design crashes during planning phases in GRE.3 F! x' r/ O7 D% W
1044029 PSPICE ENCRYPTION Encrypted lib not working for attached
' \. ?3 n/ n7 O1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory
9 y$ @4 S) G3 d1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.+ y% r4 A2 n" E q- g, t( T9 i! m
1044577 GRE CORE Plan > Topological either crashes or hangs GRE9 g; f3 j' Y7 x5 j9 U$ c
1044687 TDA CORE tda does not get launched if java is not installed) f% K; [/ N1 f$ E; `: s- ?
1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die3 @& m# u m8 K: M& C' n; H+ M
1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form.
9 g+ v* g5 }/ j0 |+ Q1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board?
$ U" {7 J/ K: ?9 q7 ^1045863 CONCEPT_HDL INFRA Customer had the crash several times when they run script with SPB16.51./ R7 b4 o5 t! a* u
1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.8 t* @6 {% f# e" k' m! z6 r
1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow
% @+ I: T) p! |& A p- d1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.
4 z' l1 J; M- r% `# U* R1048403 ALLEGRO_EDITOR SKILL Allegro crashes opening more than 16 files with skill
( q8 V. Y: [$ `3 D; H% ?- C$ Z1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond." i* [3 H) v5 \( \) ~) Y
1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5% N4 ~9 Z+ k; n8 @. k/ @
1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.5
- R7 _. _1 q# S' @ z G1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value
# K" e) ]" ]6 D; P7 D' D6 C2 p; d& z+ X1049956 ALLEGRO_EDITOR DATABASE BUG:dbdoctor deletes fillets as design is migrated from old version
! X, b' ~- c0 l% ?1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesn縯.# D3 k( w7 u9 G" ^1 N/ `2 \
1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.
2 T/ f' |$ Y1 ~1050918 ALLEGRO_EDITOR MANUFACT Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.
+ i1 W J9 W H% V1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes% }. M- @5 e$ ?1 G" S
1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.- v# Y1 k, I5 a$ n
1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3
6 R+ U* Q7 {' y' N; q* F/ H1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file
7 Z7 ?( }8 X6 C" B1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors
3 `9 a/ y0 t* l+ e0 c1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.
8 i" F5 i# P* Y/ s1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.% U( T1 K( P. C( }
1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design1 M* S+ e, {: F8 K; o: u
1054351 ALLEGRO_EDITOR SHAPE Shape voiding fails for board having diffpairs with arcs
' e( ^- j. j* e# X1 O2 Q+ h1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label& |: Z# T2 [& }
1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction.9 a* W/ k4 P5 ]; ?2 H5 q
1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy
7 C+ q8 ]0 e6 V) d7 S* A1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down/ N# v7 I$ C" @+ v$ d! h5 Z- _' D g
1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection
% J1 s* D; W4 P# r0 H* A1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.$ e- q( j7 R5 r8 A0 ?& |
1056579 CAPTURE OTHER Ability to define custom variables for titleblocks that update for specific variant views
# z. ^' v# P/ {9 \1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline
2 P0 V/ o- A& a9 ~8 ?1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.# {0 h! E l# q
1058002 SIG_INTEGRITY SIMULATION Incorrect Xtalk sim netlist was created.
1 [& R) x# X! g1 ~ O* V1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move" N5 L2 z; e- M9 f1 G1 t3 |" _+ s" {
1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value
* `& b) K- P! h3 f$ ]' g' V1059037 CIS PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer6 |* S9 g+ n4 }% o
1059389 ALLEGRO_EDITOR MANUFACT about back drill analisys report% b8 G) ]( }4 ?8 d
1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.& u( P# n F# a
1060428 ADW DESIGN_INIT ADW Flow Manager Copy Project fails to complete) S1 u, M+ g& Q
1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.3 D; y: F" @2 [: T& H2 I
1060977 F2B DESIGNSYNC back annotate in 16.5 does not bring in already placed nets as global nets
: t* o2 k1 j# u0 z! |$ V, J2 X6 L& X" t1061223 CONCEPT_HDL CHECKPLUS What determines a passthru pin?+ y7 O4 {( B. p" q
1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values.& z% t$ R/ E3 v
1061572 ALLEGRO_EDITOR INTERACTIV Shortcut keys wont work after "Edit Text" command is finished.
0 O- N/ C0 X% X1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 00( ]. m1 Q- T: h; D/ G
1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation1 \8 h- }7 m0 ]+ O: u+ z- }
1062982 ALLEGRO_EDITOR MODULES Module containg partitions has been imported to the main design and cant be refreshed.5 v" |# Z# _4 T8 e' e# u! x
1063284 PCB_LIBRARIAN OTHER PDV Save As is broken- o% W) ^3 W& x( n4 w
1063658 ALLEGRO_EDITOR SCHEM_FTB Allegro Import Logic does not remove library defined diffpairs
8 G* T% c& \/ b$ A* j6 S1063778 CONCEPT_HDL CHECKPLUS The hasSynonyms CheckPlus predicate is not returning true for all global signals.
: r9 L2 `- t( k" Y3 O1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager.
* b- s; {% _ ]* V' s- \; A2 F# N1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design
; Z' c8 X+ f4 M( T4 I1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV3 v6 D' F) d2 L& j
1065618 CONSTRAINT_MGR ANALYSIS DRCs on board but Constraint Manager shows the columns as green.; M, f! `" Y5 p% q \3 F4 `$ ^3 B0 d
1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X1 m$ N' m6 ^1 L: {8 |8 b; Q; z- ^
1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application
) _! h* _' I/ j! S7 V6 E n5 I9 k1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report+ K) O! y: B* E( B4 {$ `
1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC* G. D2 U- _1 {( j* o
1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic6 b! m. d4 [* o0 U# \4 C
1067339 CONSTRAINT_MGR ANALYSIS Relative Propagation Delay analysis in the Partition file seems very inconsitent.' r- l1 H' [ M( Y* x" V" p
1067984 SIP_LAYOUT OTHER layer compare batch fails with write protected file
5 b' q- p" b3 @1 `) F. }, m! k1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 縞hange properties� command
/ C. ^+ ^) Z h+ X& C1068547 ALLEGRO_EDITOR EDIT_ETCH Outward Fanout is not fanning out this 4 sided part as intended
8 T6 M2 r4 e" c6 H o x( |0 G1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067
3 \- H$ }9 h: {+ d" d: [/ n( P+ O/ x1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design
3 t" Y% q0 B# N6 ^; }# F5 q1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify9 v# y- {# x" U9 ~& \- W) C8 E# `
1069915 ALLEGRO_EDITOR EDIT_ETCH Allegro hangs with when doing spread between voids
6 [: C/ W% f3 }) d1070007 ALLEGRO_EDITOR PLOTTING Export IPF omits drill figure characters for backdrill holes
1 M! I! I% g/ A* }9 _: L. V1071722 SIP_RF DIEEXPORT Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow
2 W }$ k: D @3 r7 j4 _( _1 G U1072067 APD EXTRACT When expoting using Extracta oblong pads with anyangle are abnormal; G& k" J, b5 R+ p9 p- P4 R
1072791 ALLEGRO_EDITOR DATABASE Database check cannot fix error and keep report the same issues cause artwork cannot export.
" J! a) \$ |+ \! R1072806 CIS EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6" ]; z8 c# Z- |- `
1072843 ALLEGRO_EDITOR PLACEMENT The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5' e, H. _8 D) v. n1 B
1072904 SIP_FLOW SIP_LAYOUT Probe pins not being mirrored in Die Editor correctly in Chip Down mode.' C0 M$ j d$ U7 D3 K6 ?
1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.
2 g* k# Z! L3 Y' x: d9 T1073445 ALLEGRO_EDITOR GRAPHICS 'infinite cursor graphics fail -ghost copies as you move cursor
, G$ w G) o6 |9 h/ |/ \1073464 SCM SCHGEN Schgen never completes.
, a4 n8 F5 w+ U1073587 SIP_LAYOUT OTHER axlSpreadsheetSetWorksheet command clears the cells in memory
1 W3 I/ `4 X% ?1 B2 L/ _1 o1073745 CONCEPT_HDL CORE Import design fails1 T) o2 \% M2 p1 L3 e7 m6 a! l
1073852 ALLEGRO_EDITOR INTERACTIV While doing a Copy Via use the last 'Copy Origin'
: M, x, P. Y3 r: W1074279 ADW DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE
2 v! N! e+ W4 v- ?* g7 \$ O1074791 CONCEPT_HDL HDLDIRECT User gets port exists in schematic but not on symbol message even though the port does not exist
; C) u1 E2 i' d' v) T; X( U4 G1075135 ALLEGRO_EDITOR DRAFTING Ability to edit dimension text block in Instance Parameter
+ a4 S5 R6 C6 ?0 y1075151 ALLEGRO_EDITOR SHAPE Cannot change global shape parameter back to thermal width oversize after having used fixed thermal9 X' e1 J; Q5 g% G1 o
1075256 ALLEGRO_EDITOR OTHER Import > IPF in 16.5 is dropping data.) [" Q! D: e9 a. ?1 G
1075853 ALLEGRO_EDITOR REPORTS please add "PART_NAME" at Extract UI
1 o# v' J7 M9 P j0 i1075934 ALLEGRO_EDITOR DRAFTING Able to Changing Dimension Text Block
: l# Y, K" ]0 t- c) B9 I1075955 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 using key "I" on keyboard in not centered on mouse pointer2 @9 e! G# S: _; T
1075964 ALLEGRO_EDITOR SHAPE Shape voiding is not consistent in conjunction with odd angle and arc traces" c6 I* Y2 j- o6 M& H
1076086 SIP_LAYOUT IMPORT_DATA missing wirebond after import SPD2; `! @. d( e; ~, L
1076202 ALLEGRO_EDITOR EDIT_ETCH Allegro add connect causing crash after Hotfix# o: K3 Z* s5 e0 _0 h2 w
1076205 CAPTURE PRINT/PLOT/OUTPU : Printing of User Assigned RefDes
* z. _4 m, A+ O8 V0 C1076536 ALLEGRO_EDITOR DRC_CONSTR Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top+ @, t" [+ d/ u' E6 z
1076538 CONCEPT_HDL CORE Property visibility changes in attribute form not updated in schematic canvas.
# t" Y! R, a% S9 u, d1076655 APD DXF_IF Dxf does not get offset value if die symbol padstack has offset value
. M2 `0 E. s' S( m) O7 d o. }1076846 ALLEGRO_EDITOR EDIT_ETCH Grid snapping broken after slide in 16.6; b/ }1 ~9 u- D) U# T0 Z
1076891 ALLEGRO_EDITOR INTERACTIV Symbol rotation not displayed correctly when defined as a funckey
" t- c) D0 P, a/ Q1076909 ALLEGRO_EDITOR DRC_CONSTR Allegro crashes while placing modules from database! E" Z- w0 E1 q, ~/ G5 }' L+ r
1077084 CAPTURE NETGROUPS Crash on selecting bus when Enable Global ITC is unset
+ E' S# F* c" d1 c0 P* a* R1077169 APD SHAPE Shape > Check is producing bogus results.
( H/ q" P1 G2 s) @1077572 ALLEGRO_EDITOR DATABASE Mechanical symbol created with 16.6 cannot be placed on board.
5 d- N: i v$ O1077879 ALLEGRO_EDITOR SKILL Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim8 v, P1 |0 j2 i3 W: I% u! S& F! Z
1078380 SCM OTHER Custom template works in Windows but not Linux3 Z! @% |/ |; w4 }$ k' n4 u& W9 e
1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly.
1 H) [6 \0 a3 S+ k' H) N- h1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide
& ^/ U+ U$ ^7 z! f7 N$ L8 q1079082 ALLEGRO_EDITOR PLACEMENT Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping0 ?% r. B* z" t' i7 i& T! _' T
1079533 ALLEGRO_EDITOR PLACEMENT Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"
/ b' J/ E) @4 ?! O* e1079937 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text
! Z+ I3 x( V' t( @2 ?" [1082582 ALLEGRO_EDITOR GRAPHICS Allegro hangs on a given testcase using the MMB zoom control
0 P" r* x! |7 U1082981 ALLEGRO_EDITOR SKILL Allegro crash while change the new symbol type as mechanical., e7 {# k- n( C. J
1083230 SIP_LAYOUT SHAPE Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.
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发表于 2014-7-31 09:06
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