关于 signoise errors 的问题

mjchen

set  ads_autosaverevs = 0
, A( }8 f- h' C( [0 c1 o8 P+ P% oset  ads_boardrevs = 1
- |) W" z8 L8 o" hset  ads_dbext    = brd
& f* ?' R$ p2 z7 ?, y# i) i5 Iset  ads_logrevs  = 4
  O: B5 L6 r: e* y* Tset  ads_materialname = materials
set  ads_msgname  = allegro
* e; M. i$ z5 }% t0 [& u1 ^" eset  ads_norevs   = 1
( I1 N7 _/ A2 F  S" F) zset  ads_textrevs = 2
set  adsboardpath = E:/working/tr5 .
" M/ `+ V/ `" G- }  ]set  aDSPath      = . C:/cadence/SPB_16.6/share/pcb/text
set  alibpath     = C:/Cadence/SPB_16.6/share/pcb/pcb_lib
, x' [0 ^/ I  [5 B3 b5 u% ?6 Mset  allegro_brd2odb = C:\mentorGraphics\Allegro Export ODB++
8 \: Y( `/ f4 m, ~% e3 ]set  allegro_dynam_timing_fixedpos =
; |7 j7 l, {6 m  o! X  B; M9 L1 Uset  allegro_install_dir = C:/Cadence/SPB_16.6/share/pcb
+ w& A2 S4 k) [* Tset  allegro_install_dll = C:/Cadence/SPB_16.6/tools/pcb/bin
set  allegro_install_root = C:/Cadence/SPB_16.6
set  allegro_install_tools = C:/Cadence/SPB_16.6/tools/pcb
set  allegro_site = C:/Cadence/SPB_16.6/share/local/pcb
set  allegro_type = pcb
set  allusersprofile = C:\ProgramData
set  ansifont     = ansifont
4 p$ a* C& j) G4 n$ oset  appdata      = C:\Users\chenmaojie\AppData\Roaming
set  aptpath      = . ..
set  artpath      = . ..
set  artwork_no_unit_warn =
4 ^' k. H. r% w; g/ qset  autosave     =
set  autosave_time = 10
6 H/ B/ ^; Z& g9 p# P, J6 Tset  base         = E:/working/tr5
/ p0 b! H8 Z& ~. f: W  i" Tset  batchhelppath = . C:/Cadence/SPB_16.6/share/pcb/batchhelp
0 F) x, D& y( J, z: F; a0 D+ B/ Gset  bmppath      = . C:/Cadence/SPB_16.6/share/local/pcb/icons C:/Cadence/SPB_16.6/share/pcb/text/icons
' P: O9 O- m- r1 \set  brd_dbext    = brd
set  brd_mcm_tech = EXT=brd:EXTALT=mcm;tech:MSG=BRD/MCM/TECH:TITLE=Select a BRD/MCM/TECH file:
set  caetbin      = C:\adiva\bin
& K# u6 G* L+ t$ Y. b4 y( y: W" r- Fset  caetdata     = C:\adiva\data
) T" @3 m9 x& b9 I( M& r0 Yset  caethelp     = C:\adiva\manual
- W( a: a1 q) S- c% g9 u/ Oset  cds_lic_file = 5280@chmj
5 v& c3 e7 j6 Z$ S8 Aset  cds_lic_only = 1
, f: k/ ?$ P* F) qset  cds_sis_msglog_key = SISMsgLog
9 I% x. j1 r, l, @, vset  cds_site     = C:/Cadence/SPB_16.6/share/local
3 ~+ o6 n% E$ T4 E; ?. w( I3 u& ~5 Sset  cdsdoc       = algcmdref
set  cdsplat      = wint
. ?' O4 b; r8 t' w: r0 J; y* u% eset  cdsroot      = C:\Cadence\SPB_16.6
set  cdsversion   = 16.6
- A) C1 t- j6 E) J& _( m! O3 x2 u  h$ kset  chdl_lib_inst_dir = C:\Cadence\SPB_16.6
4 i4 _1 R) L; J$ Y1 g& m+ Sset  cio_dbext    = cio
" D6 F/ k4 `, E1 T4 T- l1 _set  class        = BOARD GEOMETRY
& g" J7 |' E0 F1 K9 d2 {8 }set  clippath     = .
set  commonprogramfiles = C:\Program Files (x86)\Common Files
" t# g  t& O; d3 yset  commonprogramfiles(x86) = C:\Program Files (x86)\Common Files
0 C9 k9 x' s: g, F+ H% F- \7 @3 P( pset  commonprogramw6432 = C:\Program Files\Common Files
; I& r- Y+ y1 Hset  compalib     = C:/Cadence/SPB_16.6/share/pcb/pcb_lib/symbols C:/Cadence/SPB_16.6/share/pcb/allegrolib/symbols
& D# B5 _& z' a2 X; [7 \( Y( k/ @5 Nset  complibpath  = C:/Cadence/SPB_16.6/share/pcb/allegrolib
- M- `6 A/ B: u2 g- L* b# Iset  computername = CHMJ
set  comspec      = C:\Windows\system32\cmd.exe
set  concept_inst_dir = C:\Cadence\SPB_16.6
8 B% |1 A- [$ Lset  cwd          = E:/working/tr5
& z# H1 M5 L4 K9 _; W; [5 [3 L, H7 z  sset  dclpath      = . .. C:/Cadence/SPB_16.6/share/pcb/pcb_lib C:/Cadence/SPB_16.6/share/pcb/allegrolib
, l8 v8 t. B! ~2 Uset  devpath      = D:\Allegro_LIB\Allegro_LIB\
set  dfaauditpath = . C:/Cadence/SPB_16.6/share/local/pcb/assembly C:/Cadence/SPB_16.6/share/pcb/assembly
: X# N2 @$ C, I9 B! x, w8 e! Oset  dfacnspath   = . dfa .. ../dfa C:/Cadence/SPB_16.6/share/local/pcb/dfa
( C4 w- f7 h* u1 C/ W* w2 oset  display_backingstore = on
set  display_nohilitefont =
set  display_norepair = rats
set  display_shapefill = 4
set  display_shapefill_analysis = 2
set  dpm_dbext    = dpm
( Q/ S$ T, _1 J7 x; Lset  dps_dbext    = dps
8 c, b1 @: t5 Y% f+ p; aset  drawing_4mils =
& G% I" e2 G$ {. O0 cset  drc_diff_pair_overide = 0
# |( X) b  @6 l( {1 a8 Q" iset  envpath      = C:/Users/chenmaojie/AppData/Roaming/SPB_Data/pcbenv C:/Cadence/SPB_16.6/share/pcb/text
set  ext_artwork  = art
4 \' [5 G1 Z' K* `) hset  ext_drill    = drl
set  film_nosort  =
set  formpath     = . C:/Cadence/SPB_16.6/share/local/pcb/forms C:/Cadence/SPB_16.6/share/pcb/text/forms
2 X( X* g( [! T/ h: k3 Rset  fp_no_host_check = NO
set  global       = C:/Cadence/SPB_16.6/share/pcb/text
, k5 A. r1 m- Q4 C& H' I# L& zset  globalpath   = . C:/Cadence/SPB_16.6/share/pcb/text
3 ^7 X; q1 y# qset  helppath     = . C:/Cadence/SPB_16.6/share/pcb/help C:/Cadence/SPB_16.6/share/pcb/text/help
set  home         = C:/Users/chenmaojie/AppData/Roaming/SPB_Data
set  homedrive    = C:
set  homepath     = \Users\chenmaojie
' a1 \3 [: J0 _) T# k! D2 \3 P& oset  ignore_popup_action =
6 V. t% m1 j9 X0 M' `set  imagepath    = . C:/Cadence/SPB_16.6/share/pcb/examples/image
set  kanjifont1   = kanjifont1
& E* W7 L% Y, R$ P0 Dset  kanjifont2   = kanjifont2
6 X6 L, H, D! y8 o/ rset  kanjifontpath = . C:/Cadence/SPB_16.6/share/pcb/text/fonts/kanji
set  ldfpath      = .
9 }6 l9 Z) N' d1 m! o" Nset  localappdata = C:\Users\chenmaojie\AppData\Local
set  localenv     = C:/Users/chenmaojie/AppData/Roaming/SPB_Data/pcbenv
* k; `) o- l2 B, x; k9 n' J. iset  localpath    = . C:/Users/chenmaojie/AppData/Roaming/SPB_Data/pcbenv C:/Cadence/SPB_16.6/share/local/pcb . C:/Cadence/SPB_16.6/share/pcb/text
0 ~. X/ w) X) D/ V# G0 Yset  logonserver  = \\CHMJ
7 B& r. ?* {. s, B( ^' i+ e4 bset  materialpath = . C:/Users/chenmaojie/AppData/Roaming/SPB_Data/pcbenv C:/Cadence/SPB_16.6/share/local/pcb C:/Cadence/SPB_16.6/share/pcb/text
8 [4 ~/ H$ G* h8 e: p& b4 p  vset  mcm_dbext    = mcm
set  menuload     = allegro
set  menupath     = . C:/Cadence/SPB_16.6/share/local/pcb/menus C:/Cadence/SPB_16.6/share/pcb/text/cuimenus
set  module       = TR5_A0.brd
6 P% n, t, H' @: F0 v/ mset  modulepath   = . C:/Cadence/SPB_16.6/share/local/pcb/modules
5 h" b6 W: `$ F: j8 Qset  ncdpath      = . .. C:/Cadence/SPB_16.6/share/local/pcb/nclegend C:/Cadence/SPB_16.6/share/pcb/text/nclegend
set  noshow_current_selections =
( ]* M; L8 U- hset  number_of_processors = 4
set  oa_plugin_path = C:\Cadence\SPB_16.6\Share\oaPlugIns
set  os           = Windows_NT
6 J$ L0 S( _7 U# q4 t* o& Hset  padpath      = E:\layout working\SPO2 WITH MFI\SPO2 LIB\ D:\ALLEGRO\ E:\LAYOUT WORKING\PACKAGE\1394\ E:\LAYOUT WORKING\PACKAGE\11.10\
) B. t0 v2 l9 gset  path         = C:\MentorGraphics\Allegro Export ODB++\nv\bin C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common C:\Windows\system32 C:\Windows C:\Windows\System32\Wbem C:\Windows\System32\WindowsPowerShell\v1.0\ C:\Program Files (x86)\WinMerge C:\Program Files\TortoiseSVN\bin C:\Program Files (x86)\Skype\Phone\ C:\Cadence\SPB_16.6\openaccess\bin\win32\opt C:\Cadence\SPB_16.6\tools\capture C:\Cadence\SPB_16.6\tools\Pspice C:\Cadence\SPB_16.6\tools\specctra\bin C:\Cadence\SPB_16.6\tools\fet\bin C:\Cadence\SPB_16.6\tools\libutil\bin C:\Cadence\SPB_16.6\tools\bin C:\Cadence\SPB_16.6\tools\pcb\bin
set  pathext      = .COM .EXE .BAT .CMD .VBS .VBE .JS .JSE .WSF .WSH .MSC
set  pcb_cursor   = cross
; E& h1 Z; Y# Sset  pcell_lib_path = C:/Cadence/SPB_16.6/share/local/pcb/../../RFsip/sip_pcells . sip_pcells .. ../sip_pcells
; Q( b. I* k8 ~' F/ N& o- dset  pdfpath      = . C:/Cadence/SPB_16.6/share/pcb/help/pdf
) o, z" l* \4 ]6 M& ^# T! g) cset  pm_cmdmap    = allegro
set  prfeditpath  = . configure/prfedit C:/Users/chenmaojie/AppData/Roaming/SPB_Data/pcbenv/configure/prfedit C:/Cadence/SPB_16.6/share/pcb/configure/prfedit
' `4 H2 B$ u: V, x( H4 I: `set  processor_architecture = x86
2 s% d* `: D0 Dset  processor_architew6432 = AMD64
set  processor_identifier = Intel64 Family 6 Model 37 Stepping 5, GenuineIntel
! a1 H5 ^7 q$ Kset  processor_level = 6
set  processor_revision = 2505
set  programdata  = C:\ProgramData
set  programfiles = C:\Program Files (x86)
  v! C( d# y* Q( b. W' a( c" fset  programfiles(x86) = C:\Program Files (x86)
set  programw6432 = C:\Program Files
set  psmodulepath = C:\Windows\system32\WindowsPowerShell\v1.0\Modules\
: @- q, v  L4 e5 Iset  psmpath      = E:\layout working\SPO2 WITH MFI\SPO2 LIB\ D:\ALLEGRO\ E:\LAYOUT WORKING\PACKAGE\1394\ E:\layout working\package\11.10\
set  public       = C:\Users\Public
set  roaminc      = 96
set  scfpath      = . scfs .. ../scfs
4 {, K3 N( \4 g# L  Zset  scriptpath   = . C:/Cadence/SPB_16.6/share/local/pcb/scripts C:/Cadence/SPB_16.6/share/pcb/text/script
set  sessionname  = Console
set  si_model_path = .
set  signal_install_dir = C:/Cadence/SPB_16.6/share/pcb/signal
' Y; B) j# G; e2 H( Y7 j: ]set  signal_optlib_dir = C:/Cadence/SPB_16.6/share/pcb/signal/optlib
0 V9 A: c5 Y& U9 h5 cset  signoisepath = . C:/Users/chenmaojie/AppData/Roaming/SPB_Data/pcbenv C:/Cadence/SPB_16.6/share/local/pcb/signal C:/Cadence/SPB_16.6/share/pcb/signal C:/Cadence/SPB_16.6/share/pcb/signal/optlib C:/Cadence/SPB_16.6/share/pcb/text
set  sip_dbext    = sip
set  slide_arcs   =
set  sproutepath  = C:/Cadence/SPB_16.6/share/pcb/configure/sproute
7 _9 B" b0 Q4 M) Q: i" e1 kset  subclass     = OUTLINE
4 k1 i/ P! F/ j7 k! i7 Mset  systemdrive  = C:
set  systemroot   = C:\Windows
( V1 e) Q5 T" P) C7 A. Nset  techpath     = . C:/Cadence/SPB_16.6/share/local/pcb/tech C:/Cadence/SPB_16.6/share/pcb/text/tech
set  telenv       = C:/Cadence/SPB_16.6/share/pcb/text/env
8 g4 B8 T$ B( y9 `  Z5 O  aset  temp         = C:\Users\CHENMA~1\AppData\Local\Temp
3 G. X0 H) k' t% v) k* o( v& R( dset  textpath     = . C:/Cadence/SPB_16.6/share/local/pcb/extracta C:/Cadence/SPB_16.6/share/pcb/text/views
set  tilepath     = . C:/Cadence/SPB_16.6/share/local/pcb/modules
set  tmp          = C:\Users\CHENMA~1\AppData\Local\Temp
set  topfilelib   = C:/Cadence/SPB_16.6/share/pcb/pcb_lib/templates C:/Cadence/SPB_16.6/share/pcb/allegrolib/templates
- ^$ `" u' m) P8 x& X4 R; X( Eset  topology_template_path = . templates .. ../templates C:/Cadence/SPB_16.6/share/local/pcb/topology C:/Cadence/SPB_16.6/share/pcb/pcb_lib/templates C:/Cadence/SPB_16.6/share/pcb/allegrolib/templates
set  units        = C:/Cadence/SPB_16.6/share/pcb/text/units.dat
; `, ?! j- s0 L- l, iset  userdomain   = chmj
) ~* G; a" h' u0 ^5 fset  username     = chenmaojie
7 v* u( j( F: \, ^% |( m3 {set  userprofile  = C:\Users\chenmaojie
set  vectorfontpath = . C:/Cadence/SPB_16.6/share/pcb/text
/ p* g* h( F6 x/ q9 f" a- `$ Wset  viewlog      = E:/working/tr5/signoise.log
$ ^7 R4 q% A% D$ V" dset  viewpath     = . C:/Cadence/SPB_16.6/share/local/pcb/views
1 G: s' _0 J2 _. X$ Dset  wbpath       = . C:/Cadence/SPB_16.6/share/local/pcb/wbtiers
set  windir       = C:\Windows
set  windows_tracing_flags = 3
set  windows_tracing_logfile = C:\BVTBin\Tests\installpackage\csilogfile.log
. ~$ b4 y; b5 b( o9 pset  wint         =
/ g1 A! ]$ A4 |9 Z' q3 @set  wirebond_hud_update_frequency = 25
! c- z, y  v7 |! g+ u$ Dset  wirebond_suppress_bondwire_drcs =
set  wizard_template_path = . .. C:/Cadence/SPB_16.6/share/pcb/pcb_lib/symbols/template
! A/ D8 @; w  m* ?, b! ]0 l/ lset  xtalk_table_path = . xtalk_tables .. ../xtalk_tables C:/Cadence/SPB_16.6/share/local/pcb/xtalk C:/Cadence/SPB_16.6/share/pcb/pcb_lib/xtalk_tables
  B. k+ }/ e9 mset __compat_layer = DisableThemes
set _allegro_adv_optimize =
$ C' x4 n6 n1 Q/ P% \! @' P, q# _set _allegro_aibt_built_in =
set _allegro_cns_regions_ok = 1
set _allegro_cstm_nclegend_ok = 1
4 B$ D; y/ S' c  Mset _allegro_diffpair_ok = 1
set _allegro_diffpair_static_ok = 1
set _allegro_ecsetflatten = 1
set _allegro_elec_cns_ok = 1
set _allegro_electrical_checks = 1
set _allegro_gre_all = 1
" Y) f/ D7 _& I- B7 m: Fset _allegro_gre_ifd = 1
set _allegro_gre_view = 1
set _allegro_group_route = 1
* U2 e( ?2 h& ^9 \  |  D  bset _allegro_ibd_all = 1
9 |! r) ^9 Q7 P% T! _# b; ?5 @set _allegro_ibd_view = 1
set _allegro_mini_ok = 1
set _allegro_pcb_gxl =
set _allegro_ratt_ok = 1
set _module = TR5_A0.brd
set _module_base = TR5_A0
set _program = allegro
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# N! L8 N! d! j3 \) R$ E

# M( d, \$ y# D8 {4 i; a这个是我allegro   的设置
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% x/ ^) r5 m7 E  k

mjchen

SigNoise Errors/Warnings
0 h/ x# \+ @3 E: P" u5 K5 IStarted by xrwright on 1 Dec 2013 10:05 AM. Topic has 1 replies and 548 views.
Last post on 2 Dec 2013 5:06 AM by Dennis Nagle.
# s& H# C* C$ Z% O; L" m- y' a7 D  sHi,

0 S. {' G' @& K( O+ b' {6 `All of the sudden whenever I open Cross-section and try to change Coupling Type or go to do a diff route on this particular board, an error dialog box named "SigNoise Errors/Warnings" pops up which shows this  list:

WARNINGS:
Iml model STL_2S_1R_TRACE6 is duplicated 2 times in libraries
         interconn.iml ..\..\..\..\Cadence\SPB_16.6\share\pcb\signal\cds_interconn.iml.
( {% ?. p3 m9 a. Z4 zIml model STL_2S_1R_TRACE48 is duplicated 2 times in libraries
. |( d0 f; Z$ u/ \( J) M         interconn.iml ..\..\..\..\Cadence\SPB_16.6\share\pcb\signal\cds_interconn.iml.
Iml model STL_2S_1R_TRACE36 is duplicated 2 times in libraries
9 ?1 D; A6 k4 Q0 z         interconn.iml ..\..\..\..\Cadence\SPB_16.6\share\pcb\signal\cds_interconn.iml.
; D/ _# F; e5 {Iml model STL_2S_1R_TRACE24 is duplicated 2 times in libraries
+ V: x2 a; E3 z7 S, E2 R         interconn.iml ..\..\..\..\Cadence\SPB_16.6\share\pcb\signal\cds_interconn.iml.
Iml model STL_2S_1R_TRACE16 is duplicated 2 times in libraries
         interconn.iml ..\..\..\..\Cadence\SPB_16.6\share\pcb\signal\cds_interconn.iml.
Iml model STL_2S_1R_CPW76 is duplicated 2 times in libraries
         interconn.iml ..\..\..\..\Cadence\SPB_16.6\share\pcb\signal\cds

" M- ?3 n7 F& q. C6 [5 G$ I......

% D9 j; c. i% C" H( J  x! I......
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: n9 u- E) u! _( T6 P+ i+ [It continues for a lot more lines showing different models. These errors are also replicated in the dialog area at the bottom of the screen.
8 w4 X; O2 ]! V0 ?% N
( |3 y) n  i% B3 ]) l# aIt's only happening for this board and no others.

Anyone know how I can correct this? Thanks!
3 V8 Q5 H  Y+ a$ M5 R0 R& l
Robert  
/ o7 W+ B  _, Z: o
xrwright xrwright
5 E$ f! M/ d6 c0 L- i1 Dec 2013 10:05 AM Reply
% D2 ~  ~8 L5 D8 o1 Reply
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Dennis Nagle Dennis Nagle
2 Dec 2013 5:06 AM
2 J0 j1 `! |- ~& g4 H/ eRobert,
5 q, q! J" ^  Y) y  ^1 E$ N1 R
The easy solution is to delete your local copy of interconn.iml - this file should be located in your working directory where the .brd is. This file is just a local cache of field solver output. Each of those "STL_2S_1R ...." entries is a coupled trace model which contains the differential impedance.
0 T2 p, O5 E0 {2 N: \/ A5 o
The bigger questions are what your desires are at this stage of the design (and/or whether someone else like the SI engineer is using the same directory). If you don't need or want to see differential impedance calculated in the Layout Cross Section dialog, then diable the checkbox in the lower right hand corner of the dialog for "Show Diff Impedance". This is what is forcing the field solver to be called. You also may or may not want to disable the imedance DRC if you are also seeing these messages generated when routing a diff pair.
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) U" u9 _+ d5 @* x* d- f5 B* R1 QThe messages also indicate that algorithmic models are enabled and that you are using the full wave solver. If you don't understand what these are and want to fully understand the implications, feel free to contact me offline.
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4 U# v( S  u7 u! i Regards,
6 ]! F" t2 Q  M# r3 h7 z-Dennis Nagle
Cadence
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9 U+ l% J/ F1 J/ H- m3 p' XReply
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dzkcool

一点一点来排查吧。
建议不要把路径设置到有空格的目录，例如padpath的路径。
看情形，你的Home路径好像也没设置，用的是系统默认的，建议改一下。
si_model_path的路径只有一个点？我的是这样的：
set  si_model_path = . D:/Cadence/SPB_16.6/share/local/pcb/signal D:/Cadence/SPB_16.6/share/pcb/signal

4 R# |' K7 @/ X你的板子叠层设置界面也截个图出来看下吧。

dzkcool

mjchen 发表于 2015-6-25 11:36
SigNoise Errors/Warnings
Started by xrwright on 1 Dec 2013 10:05 AM. Topic has 1 replies and 548 vi ...

5 D/ p/ v/ u! e# G; U看看是不是有等长参考模型，如果有，再全部重新提取生成一遍。
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武紫旭

看下你环境变量里temp及tmp路径在哪里，你把temp及tmp文件清空一下就好了，以前遇到过。

mjchen

还是不行啊   

mjchen

我从来都没有设置过home路径    不知道怎么设置

mjchen

求救

dzkcool

mjchen 发表于 2015-6-25 10:57
7 ?" r8 \2 V" G1 a我从来都没有设置过home路径    不知道怎么设置

xp系统的设置方法，供参考

mjchen

哎   

mjchen

我好蛋疼   

kinglangji

确实蛋疼...我感觉是文件的问题....去别人机器试试,如果都有上个文件呗.

mjchen

最后重新装系统，就好了

taotaonuli

我也碰到一模一样的问题了，只要是设置模型就会这样，重装了两次软件都这样，咋办

勒凹特

你的pcbenv文件是否在\Cadence\SPB_Data路劲下，我之前是因为将pcbenv文件夹放到了其他路劲下出现了这个问题。