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本帖最后由 zgyzgy 于 2015-9-1 14:13 编辑
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0 [' w: G6 }% N, x# U, |* @: tDATE: 08-28-2015 HOTFIX VERSION: 056
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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9 b* g, Y+ }6 \. @7 [1134412 allegro_EDITOR PLACEMENT Place replicate creates redundant vias and shapes- option required to prevent that1 o2 l3 {& `2 E/ T
1431136 ALLEGRO_EDITOR OTHER Cannot z-copy board outline with Contract: m; h3 j; U4 h$ }
1432392 ORBITIO INTERFACES SiP db import is 鈥渃rashing鈥� if no xda inside8 {- s2 A, R7 o4 Y, u* u
1444820 CONSTRAINT_MGR concept_HDL Exporting TCF file from Constraint Manager does not output physical and spacing constraints. K9 N9 X R2 E3 a7 {
1447986 F2B DESIGNVARI All the DNI parts not available after saving the variant file
2 O# @+ \( C4 @/ A3 g) r8 y8 G+ X1455901 CONCEPT_HDL CORE Need the ability for the front end tool license to have the High Speed option selected by default
8 c$ Q2 s3 s5 N/ o1456280 ALLEGRO_EDITOR DRC_CONSTR DRC not shown even when the constraint is violated
+ |+ [4 n% z+ J- R+ H9 ^, p& Y+ [. x1458272 SIP_LAYOUT ASSY_RULE_CHECK File size increases by factor 4 after ADRC check on a specific customer design; Z9 L2 U% g) q; V
1458960 CONCEPT_HDL OTHER Getting packaging error when SEC_TYPE and PACK_TYPE properties go out of sync due to a manual name change in chips.prt7 c9 _! I) s0 M1 m4 @
1459961 CONCEPT_HDL PDF Publish PDF command issues: Logo (.gif file) not rotated, font changed in the published file ~: c! n4 H* v' u+ \
1460178 ALLEGRO_EDITOR INTERFACE_DESIGN PCB Editor crashes on deleting vias or nets5 L2 p' A: Z! c8 ], r
1460204 SIP_LAYOUT IMPORT_DATA BGA Text In wizard ignores the primary pad layer set in text file
! [2 C d; \6 {1460246 APD OTHER axlDeleteObject() command is not removing the die from the design) L+ L1 ^0 B" v% u& V
1461387 SIP_LAYOUT skill axlDBRefreshID(nil) removes ID from assigned variable
7 o; E# v/ R6 c* o7 X! N+ x1461625 SIP_LAYOUT ASSY_RULE_CHECK Core polygon routines are not creating proper polygons; ADRCs reported: "acute angle", "exposed metal to exposed metal"
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发表于 2015-8-31 18:20
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