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本帖最后由 zgyzgy 于 2015-9-1 14:13 编辑
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DATE: 08-28-2015 HOTFIX VERSION: 056
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( k r5 Q5 l! B- w1134412 allegro_EDITOR PLACEMENT Place replicate creates redundant vias and shapes- option required to prevent that
. O! m- q, i! b6 @# C5 |1431136 ALLEGRO_EDITOR OTHER Cannot z-copy board outline with Contract! E' C% s* U7 n7 U! @
1432392 ORBITIO INTERFACES SiP db import is 鈥渃rashing鈥� if no xda inside4 ?& i$ _) h: | q! s6 v5 T
1444820 CONSTRAINT_MGR concept_HDL Exporting TCF file from Constraint Manager does not output physical and spacing constraints# q9 H1 p2 w9 N2 I4 |" K8 A) r3 P5 G
1447986 F2B DESIGNVARI All the DNI parts not available after saving the variant file; O7 J/ s+ U5 |% `
1455901 CONCEPT_HDL CORE Need the ability for the front end tool license to have the High Speed option selected by default/ ]) @0 }; G5 [9 V0 j: r* Q: ^% Y- K! Q
1456280 ALLEGRO_EDITOR DRC_CONSTR DRC not shown even when the constraint is violated. k7 \9 h. e4 c6 Q* H3 C( h6 s, o6 K
1458272 SIP_LAYOUT ASSY_RULE_CHECK File size increases by factor 4 after ADRC check on a specific customer design$ z6 C8 y/ \0 e& ]
1458960 CONCEPT_HDL OTHER Getting packaging error when SEC_TYPE and PACK_TYPE properties go out of sync due to a manual name change in chips.prt
: Y5 D% J' ~' H% C7 J1459961 CONCEPT_HDL PDF Publish PDF command issues: Logo (.gif file) not rotated, font changed in the published file
: F) `8 d6 Q4 a/ J4 m% w- d8 z1460178 ALLEGRO_EDITOR INTERFACE_DESIGN PCB Editor crashes on deleting vias or nets
- R2 N! p$ t0 j4 `1460204 SIP_LAYOUT IMPORT_DATA BGA Text In wizard ignores the primary pad layer set in text file
% T: z% C# a$ J1460246 APD OTHER axlDeleteObject() command is not removing the die from the design" {% W L* z2 c5 ~7 G# O
1461387 SIP_LAYOUT skill axlDBRefreshID(nil) removes ID from assigned variable
2 H2 d3 |6 l. x$ F8 t# a1461625 SIP_LAYOUT ASSY_RULE_CHECK Core polygon routines are not creating proper polygons; ADRCs reported: "acute angle", "exposed metal to exposed metal"
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, q0 x" S( \% m3 ~; ?6 |正在上传文件中,分享链接稍后。。。。。。
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