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General5 q) A( {$ S6 w, v7 J: Q8 k3 e
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Tablet, two mcu subsystems architecture
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Supports eMMC/uFS boot2 N R: p. k* m* G- [( m
1 Y8 [) a4 U" W$ T- Q
' h' g6 Q3 k- X( F9 N+ b Supports LPDDR3 C7 k$ R4 o. J8 ?: F/ F* F6 k0 T8 r
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; a+ \6 W" {: Q$ t+ z, t Supports LPDDR4X
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AP MCU subsystem
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9 x, Z* a0 ]% z Quad-core ARM® 2.0GHz Cortex-A73 MPCoreTM with 64KB L1 I-cache, 64KB L1 D-cache and 1MB unified L2 cache. a' [7 Y6 \2 a, q3 f* A
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Quad-core ARM® 2.0GHz Cortex-A53 MPCoreTM with 32KB L1 I-cache, 32KB L1 D-cache and 1MB unified L2 cache
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NEON multimedia processing engine with SIMDv2/VFPv4 ISA support
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7 C4 [0 p& b2 M$ m: Z DVFS technology with adaptive operating voltage from 0.6V to 1.12V
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/ q9 _. c: t; ]. Q: r8 `3 S! O+ qMD MCU subsystem( V# D+ }% y) \* K- Y
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Imagination MIPS32® InterAptive processor with max. 864MHz operation frequency2 w+ ~2 a' c0 C1 P/ V
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High-peRFormance multi-core and multithread processor architecture (two cores and two threads)
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T7 p4 R* k/ M7 t2 x. w% Y 32KB L1 I-cache and 32KB L1 D-cache per core
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384KB SPRAM (Scratchpad memory, Two-Core’s ISPRAM and DSPRAM)1 D' e4 `3 M6 J W
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' e" {1 G5 v" A2 t& r. l 256KB L2 Cache (share L2 cache for two cores)1 T L- J' h; ]- k3 h; n! P" U
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. b3 q3 x) M6 X' w @( {/ H5 ? High-performance AXI bus Interfaces
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Power management for clock gating control
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FD216 DSP for running GSM modem with max. 312MHz operation frequency
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MD external interfaces
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Dual SIM/USIM interface
7 Q/ z% ]+ p8 E2 c Interface pins with RF and radio-related peripherals (antenna tuner, PA, etc.)0 {% x: d+ X1 j) z
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Security1 R/ F( S5 G9 `3 {& B
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5 `% L4 }, U; o ARM® TrustZone® Security3 z7 M( ^" k0 j9 m
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3 P( [7 ]& I2 B8 Q1 t% J) \External memory interface
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LPDDR3 up to 4GB (single channel with 32-bit data bus width)
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LPDDR4X up to 8GB (dual channels with 16-bit data bus width)
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& U- J Z( d2 m0 b. h Memory clock up to LPDDR3-1866 or LPDDR4X-3600- I, A ^1 t* ~" ^6 x u, T, Y
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Self-refresh/partial self-refresh mode" G* U* P4 T! S
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Low-power operation
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; H$ l0 P) ]! v* L6 U0 \4 ? Programmable slew rate for memory controller’s IO pads
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0 i; k3 F. g0 {$ @3 Q; ^- f3 l
5 P1 I4 M; Y( V) _- W' {. e& G Dual rank memory device; {! H# d) s- N* Z
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Advanced bandwidth arbitration control$ z# i" P# X1 C, S
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$ f6 _, x0 N& F% A' [( `Peripherals0 k: b5 a. k: @$ u; g. q, v% F
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USB one port with USB3.0 device mode or USB2.0 OTG mode
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& S" L: U9 K) \8 ? eMMC5.1
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uFS 2.1
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6 Q6 t0 S8 l3 E$ @ 3 UART for debugging and applications7 _7 L' F" j, t( d9 Q
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6 SPI masters for external devices
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' M8 o0 k4 [& F2 w/ G 6 I2C/3 I3C to control peripheral devices, e.g. CMOS image sensor, LCM or FM receiver module
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- G) X( c; `" a+ G( x Max. 3 PWM channels (depending on system configuration/IO usage)) T* r& _+ ? ^2 v
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: \. I) J A6 ~ I2S for connection with optional external hi-end audio codec
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( F9 M. N; q$ F( a GPIOs
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# ~9 E I* J8 M* H3 _( ?0 R$ w" f 2 sets of memory card controllers supporting SD/SDHC/MS/MSPRO/MMC and SDIO2.0/3.0 protocols
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Operating conditions
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Core voltage: 0.7V/0.8V
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I/O voltage: 1.8V/2.8V/3.3V " y E% u% {9 M$ o$ b0 M. n8 L0 l
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3 `4 U7 E" ^) Y8 f! |5 G& G Memory: 1.1V/0.6V
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H9 W3 t& d# M; A' t LCM interface: 1.8V
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7 S8 ~# Q8 q# T7 l% ^% Z# _ Clock source: 26MHz, 32.768kHz
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Package& }$ N# ?* d! q. |- ?: M
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5 }7 y9 t3 P1 t+ u# A1 E% O Type: VFBGA
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11.8mm*11.0mm
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3 C( ~+ F# C: W: Q! ~ Height: Max. 0.9mm% x% r+ M; x. ?! V3 |/ M
% V/ J( {& o2 c1 T ]5 L- [) x& K5 P9 T! |: N/ l+ B+ B8 `
Ball count: 599 balls
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Ball pitch: 0.4mm
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% ~2 N5 _+ y8 A+ P/ NLTE% }4 C% _* \! ]# z! l8 x8 Y: x* W
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3 E* r! Q1 k( [4 Q+ } FDD/TDD Up to 300Mbps downlink, 150Mbps uplink6 ]# g6 q" H- I" H; @
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Downlink carrier aggregation (CA) ability; 1.4 to 20MHz RF bandwidth per component carrier (CC) and up to 2 CCs
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8*2 downlink SU-MIMO per component carrier
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0 Q, n' s# d. X8 _! v2 r; v Downlink MU-MIMO per component carrier! k2 N5 d, K7 H- X
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Supports feICIC$ G1 \' G, E( q# C+ |
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( {+ j$ p2 S( X& s+ y2 j4 T+ \( W1 T Supports MBMS0 l) {$ j8 r7 q# ~9 Y
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, M3 z$ c, e- v8 M Uplink CoMP ability& e' }, {5 `4 Z$ n1 H0 Q; i) I6 `& q9 E
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4 x$ Z( L9 \) W# n) p" m8 z Advanced Interference Cancellation
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Transmit Atenna Selection( O% t4 h; k: b" a/ d! ^
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" L& T$ Q0 _7 Q3G UMTS FDD supported features
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+ L( b1 A4 k+ z9 I3 u/ V 3G modem supports most main features in 3GPP Release 7 and Release 8! i( Z' C, y& C2 g1 B& J
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. b1 F, ?' Q$ W) z CPC (DTX in CELL_DCH, UL DRX DL DRX), HS-SCCH-less, HS-DSCH
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Dual cell operation" ~5 p. T: r0 \' U# Q- }! K6 O: m
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1 \2 E- o/ E* C8 }" a0 ? MAC-ehs
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h3 X0 }1 y' R1 b! c$ i' L. \ 2 DRX (receiver diversity) schemes in URA_PCH and CELL_PCH5 v( g9 V" l+ \7 ]( _
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$ l! [# T4 j4 f1 h: w3 z+ F Uplink Cat. 7 (16QAM), throughput up to 11.5Mbps& p2 ]4 @6 _* \" K
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Downlink Cat. 24 (64QAM, dual-cell HSDPA), throughput up to 42.2Mbps9 C- ^( {+ U% L
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. P7 u$ ]$ N0 c* F1 n Fast dormancy% Z9 w( ~6 g# z0 C/ L
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: J: R* t7 [3 Q d ETWS
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Network selection enhancements4 a4 V! D! E, p: _/ H' w
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3 s4 j6 n- t# B& k6 c Transmit Atenna Selection ]+ R; h0 [4 T
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0 m* c& i7 C3 T! C2 lTD-SCDMA5 P% D3 w! i' F3 l* e2 I7 y
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: w6 `4 L. ~# U2 h% Z CDMA/HSDPA/HSUPA baseband
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c3 r! N/ d7 g2 V N$ L o TD-SCDMA Bands 34, 39 & 40 and Quad band GSM/EDGE
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Circuit-switched voice and data; packet switched data 7 S* @" D9 ]: t- R* d, x
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384/384Kbps class in UL/DL for TD SCDMA. D/ L) ~1 n. e- O6 }
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! Q. r8 I) m1 x0 x- w0 D- M9 F7 | e TD-HSDPA: 2.8Mbps DL (Cat.14)
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TD-HSUPA: 2.2Mbps UL (Cat.6)
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F8/F9 ciphering/integrity protection
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/ g5 p! }. J4 B4 E- w I Transmit Atenna Selection
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Radio interface and baseband front end" C7 i' `, T! P$ m9 U
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High dynamic range delta-sigma ADC converts the downlink analog I and Q signals to digital baseband.
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10-bit D/A converter for Automatic Power Control (APC)
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: A% X4 C( R% T0 j" U. ~7 S Programmable radio Rx filter with adaptive gain control
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Dedicated Rx filter for FB acquisition
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) O _: D L9 @2 X: { Baseband Parallel Interface (BPI) with programmable driving strength0 c6 w0 n( B+ h+ j4 {' J0 V
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Supports multi-band9 p8 O! I6 b/ m
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GSM modem and voice CODEC- m: s+ @, ^9 B, V) `1 r2 S
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# V) g- V* `# ^/ ^( R Dial tone generation( d$ \0 T# \7 X4 }) Y, a* ]
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. j0 l! ]: `: ?* |& B; [5 t2 v Noise reduction
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Echo suppression
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Advanced side-tone oscillation reduction
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) r/ ]5 G3 r/ R. r* m/ a! ?$ X- J Digital side-tone generator with programmable gain
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2 programmable acoustic compensation filters. R! B. H) i y7 v+ b
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GSM quad vocoders for adaptive multi rate (AMR), enhanced full rate (EFR), full rate (FR) and half rate (HR)3 L( n. b' r- y, n4 w, X
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E! ^+ E' I; j% ^7 o GSM channel coding, equalization and A5/1, A5/2 and A5/3 ciphering
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; N' a4 B. V, u, g; M1 g GPRS GEA1, GEA2 and GEA3 ciphering
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Programmable GSM/GPRS/EDGE modem
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Packet switched data with CS1/CS2/CS3/CS4 coding schemes' O4 v7 F7 {3 o' s. i
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( s9 p4 ]) [! o6 v. m: K5 X$ G GSM circuit switch data4 S9 b/ F9 Z5 o. E5 b# R
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) ?7 m, c5 ]# I3 P+ X GPRS/EDGE Class 12
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- ] D/ E. M0 _CDMA2000 modem interfaces
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Supports CDMA2000 1xRTT (releases 0) and CDMA2000 HRPD/1xEV-DO Revision 0 and A; `4 q8 T. F- _4 n/ l
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Supports maximum 1x data rates of 153.6kbps for forward and reverse links and DO data rates of 3.1Mbps for forward link and 1.8Mbps for reverse link
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Hybrid operation between 1x and HRPD/ v! S: i# {; n9 i- C+ F
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Simultaneous Hybrid Dual Receiver (SHDR) support
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2 b4 M+ ^9 h+ ~) B3 K; K+ V m. [( a Supports 1x Diversity
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Supports SRLTE
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# I. F5 j7 L$ `更多芯片参数特点，可参考MT8788规格书资料
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发表于 2019-11-27 15:28
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淘帖
支持！
反对！