PCB Designer’s si guide

snowwolfe

PCB Designer's SI GUIDETable of Content
& d7 {9 n+ ?* Z$ q  p8 I3 r; U* aBasics of SI___________________________________________________________________5
& d) J6 d) m# o/ H' n; k3 j1.1 When Speed is important? _____________________________________________5
/ ^5 c' z+ K8 V1.1.1 Acceptable Voltage and timing values ________________________________5
1.2 Signal Integrity ______________________________________________________5
1 B8 y- ^. I, {2 L& S  a' X1.2.1 Waveform Voltage Accuracy _______________________________________5
6 p7 k& h8 k$ r9 [( T1.2.2 Timing_________________________________________________________5
$ t9 p5 @0 N# x. R1.3 Speed of currently used logic families ____________________________________5
* H" f5 @* c" J" ?. }2 b2 O* \1.3.1 Transition Electrical Length (TEL) __________________________________6
1.3.2 Critical length ___________________________________________________6
: k+ R+ T- r' C1 m1 U1.3.3 What is Transmission Line? ________________________________________6
1.3.4 What is moving in a Transmission line?_______________________________6
) ?+ H+ H7 A! X% Y+ E& o6 G1.3.5 Power Plane Definition____________________________________________6
1.3.6 The concept of Ground ____________________________________________7
1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
1.5 RLC Transmission Line Model _________________________________________8
: G4 I( u) M7 |. M7 o# `9 ?/ p+ M  ?1.5.1 What is Impedance? ______________________________________________8
  `  F9 K  Q) W9 D* ?3 g% U) Y1.5.2 A Practical impedance equation for microstrip _________________________8
1.5.3 What is relative dielectric constant Er? _______________________________9

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2 Interconnections for High Speed Digital Circuits _______________________________10

! n; L8 l, q/ v, n+ w3 q/ z+ B# c+ `2.1.1 Summary______________________________________________________10
2.2 Examples of dynamic inteRFacing problems _______________________________10
2.3 IC Technology and Signal Integrity _____________________________________12
6 n# `( a! T! ^) }* k+ e; U" W2.4 Speed and distance __________________________________________________14
- J$ f( N8 `$ `4 M6 M2.5 Digital signals: Static interfacing _______________________________________15
2.6 Digital signals: Dynamic interfacing ____________________________________16
* {; i: Y1 t0 X  L+ G2.7 Review questions ___________________________________________________18

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3 Interconnection Models____________________________________________________20

3.1 Summary__________________________________________________________20
3.2 Reference model for interconnection analysis _____________________________20
2 F6 w% ]& w  Y  w+ i# y3.3 Receiver model_____________________________________________________21
3.4 RC interconnection model ____________________________________________23
2 x4 e, R& @7 _* t  }$ K: |! ^+ j% Y$ a3.5 Parameters of the interconnection ______________________________________25
3.6 Refined models _____________________________________________________26
3.7 Review question ____________________________________________________28


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4 Transmission Line Models _________________________________________________31

7 j8 H& y2 f5 X6 s* ^( @; A+ |7 b4.1 Summary__________________________________________________________31
4.2 Transmission line models _____________________________________________31
" Q$ S6 l! p! G# Y9 `8 G4.3 Loss-less transmission lines ___________________________________________32
4.4 Critical Length _____________________________________________________34
4.5 Reference transmission line model______________________________________35
4.6 Line driving _______________________________________________________36
- q1 Y, y$ r# G4.7 Propagation and reflected waves _______________________________________37
4.8 A sample system____________________________________________________39
4.9 Review questions ___________________________________________________42
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PCB Designer’s SI Guide Page 2 Venkata

5 Analysis techniques _______________________________________________________45

5.1 Summary__________________________________________________________45
* }1 K$ U4 T( J8 s6 N- r2 ?/ K, [5.2 Transmission time and skew___________________________________________45
5.3 Effects of termination resistance _______________________________________46
$ d2 p0 }: m7 M2 ?8 K- \" z5.4 Lattice diagram _____________________________________________________48
6 J  D9 A+ N7 h/ K0 w5.5 Examples of Real Lines ______________________________________________49
. B5 l7 Y5 [" o" f9 c: n5.6 Simulation code ____________________________________________________51
2 D! N, m) u. u* Y5 p! O5.7 Examples of results__________________________________________________54
6 f( i1 J6 T* f, X, y" Q. U5.8 Review questions ___________________________________________________55
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6 Design guide for interconnection ____________________________________________57

6.1 Summary__________________________________________________________57
+ `2 V! p% b; Q6.2 Incident wave switching ______________________________________________57
6.3 Effects of capacitive loading __________________________________________58
6 X  \, B; {/ p# r: ]6.4 Termination circuits _________________________________________________59
: p5 Y0 f: u0 E; Z" t6.4.1 Passive termination______________________________________________60
% b( q! M% L3 @* O$ I6.4.2 Low power termination___________________________________________61
6.4.3 Active low power termination circuit. _______________________________61
6.5 Driving point-to-point lines ___________________________________________62
9 @# i2 W* |$ g- K- i7 R6.6 Driving bused lines __________________________________________________64
9 O1 X, Y& N) p, c& |8 C6.7 Design guidelines ___________________________________________________67
6.8 Review questions ___________________________________________________67

snowwolfe

Signal Integrity in Digital Circuits ___________________________________________70
# G2 ?9 p3 s+ U/ }8 C7 U7.1 Crosstalk __________________________________________________________70
& x0 b3 o& t7 r8 H7.1.1 Summary______________________________________________________70
7.2 Examples of signal integrity problems ___________________________________70
7.3 Simplified Model for Crosstalk Analysis _________________________________71
5 P1 N" y) n) ?- L. I( s4 z7.4 Forward and backward crosstalk _______________________________________74
7.5 Examples__________________________________________________________76
7.6 Near-end and Far-end crosstalk ________________________________________80
7.7 Review questions ___________________________________________________81
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8 Design Guide to Handle Crosstalk ___________________________________________85

8.1 Summary__________________________________________________________85
8.2 Effects of Crosstalk __________________________________________________85
8.3 Passive countermeasures _____________________________________________86
8.4 Active Control of Crosstalk ___________________________________________92
8.5 Review questions ___________________________________________________94
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9 Ground Bounce and Switching Noise_________________________________________97

9.1 Summary__________________________________________________________97
9.2 The totem pole Current Spike__________________________________________97
9.3 Current flow in the output capacitance __________________________________100
  `! v" d! ^: a1 ?. x/ m9.4 Total Ground Bounce _______________________________________________100
0 X9 @; ^# w) @; E) Z9.5 Review questions __________________________________________________105
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10 Design Guide for Ground & Power Distribution _____________________________107

" n& S/ l9 ^# Q10.1 Summary_________________________________________________________107

PCB Designer’s SI Guide Page 3 Venkata

10.2 Decoupling Capacitors ______________________________________________107
% J  U* Z6 o2 K* N6 p4 A10.3 Placement of bypass Capacitors _______________________________________113
10.4 Ground and power distribution________________________________________114
10.5 Clock distribution __________________________________________________115
10.6 Review Questions __________________________________________________118
11 Laboratory Experience _________________________________________________120
11.1 Summary_________________________________________________________120
11.2 Aim of the experience_______________________________________________120
11.3 Generator Parameters _______________________________________________122
  n1 C5 c( l* B0 r3 L# ]11.4 Cable Parameters __________________________________________________123
11.5 Mismatch at driver and at termination __________________________________124
11.6 Capacitive Load ___________________________________________________125
  A4 |+ _8 S+ H  _11.7 7. Time-domain reflectometer ________________________________________127
1 J$ T& h, J+ P0 F& }% H9 u11.8 Driving the line with logic devices _____________________________________128
12 SI Analysis Strategy____________________________________________________133
5 j" F; }7 K/ Q+ @$ q0 v9 V9 E* d4 W12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133
12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133
12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
! A5 v( a# n3 j, B# f7 W7 n12.3 SOLUTION SPACE ANALYSIS _____________________________________135
$ ~- @% z% y& D8 l9 T1 l12.3.1
STEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
+ T- ]# g! E# t7 j5 k4 u: q12.3.3
$ @, o# t/ d$ D1 s- d( a) |STEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
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) @# j; A/ M/ G2 P% J2 `STEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136
12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136
12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137
. w- L) J+ @9 o& e: K/ T12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137
/ S: b) N( @  c4 s5 K9 Q12.3.8
STEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137
12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138
2 b3 S; I6 T4 g( v12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139
, S- u8 Z* p) W12.4 CONCLUSION____________________________________________________139
13 Glossary _____________________________________________________________141

PCB Designer’s SI Guide Page 4Venkata

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