PCB Designer’s si guide

snowwolfe

PCB Designer's SI GUIDETable of Content
* T1 C% ~7 w1 L' J+ n/ T& mBasics of SI___________________________________________________________________5
1.1 When Speed is important? _____________________________________________5
1.1.1 Acceptable Voltage and timing values ________________________________5
: c2 w$ r+ E0 z9 ~+ V1.2 Signal Integrity ______________________________________________________5
. O7 d7 |2 m8 C& a; Z9 b1.2.1 Waveform Voltage Accuracy _______________________________________5
1.2.2 Timing_________________________________________________________5
1.3 Speed of currently used logic families ____________________________________5
1.3.1 Transition Electrical Length (TEL) __________________________________6
1.3.2 Critical length ___________________________________________________6
1.3.3 What is Transmission Line? ________________________________________6
& Y' h' w. _$ U. [# A+ W/ l+ k$ y1.3.4 What is moving in a Transmission line?_______________________________6
+ v% V" P6 s% e2 y1.3.5 Power Plane Definition____________________________________________6
2 J$ R' P+ Y1 q' g1.3.6 The concept of Ground ____________________________________________7
! z6 j' r  @$ N1 j$ O1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
1.5 RLC Transmission Line Model _________________________________________8
1.5.1 What is Impedance? ______________________________________________8
1.5.2 A Practical impedance equation for microstrip _________________________8
, [! ]5 W. P3 D3 E7 D$ @, V6 a1.5.3 What is relative dielectric constant Er? _______________________________9
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2 Interconnections for High Speed Digital Circuits _______________________________10

2.1.1 Summary______________________________________________________10
- j0 x4 W+ X, A% A# J2.2 Examples of dynamic inteRFacing problems _______________________________10
2.3 IC Technology and Signal Integrity _____________________________________12
2.4 Speed and distance __________________________________________________14
2.5 Digital signals: Static interfacing _______________________________________15
2.6 Digital signals: Dynamic interfacing ____________________________________16
% V$ }7 q7 O# i- p9 D: _) ]$ G2 @2.7 Review questions ___________________________________________________18
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3 Interconnection Models____________________________________________________20

3.1 Summary__________________________________________________________20
$ n1 E/ c5 C, s3.2 Reference model for interconnection analysis _____________________________20
% X& _& A" A& E2 A/ ~  \4 ^5 D, Y% T3.3 Receiver model_____________________________________________________21
3.4 RC interconnection model ____________________________________________23
3.5 Parameters of the interconnection ______________________________________25
3.6 Refined models _____________________________________________________26
: F. h9 V0 {0 Q% v' x3.7 Review question ____________________________________________________28
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4 Transmission Line Models _________________________________________________31

9 Z; ], R* ~# b. |2 N( L4.1 Summary__________________________________________________________31
" w7 t4 X$ H; V( W4.2 Transmission line models _____________________________________________31
4.3 Loss-less transmission lines ___________________________________________32
- ~, R- s/ u+ i/ `: u4.4 Critical Length _____________________________________________________34
  B) G$ h7 c+ v7 `: S1 r4.5 Reference transmission line model______________________________________35
4.6 Line driving _______________________________________________________36
: J+ ^) S. d3 z, a* a4.7 Propagation and reflected waves _______________________________________37
4.8 A sample system____________________________________________________39
4.9 Review questions ___________________________________________________42
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PCB Designer’s SI Guide Page 2 Venkata

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5 Analysis techniques _______________________________________________________45

# u, o9 z: Q. J* C- j( A2 N" ~5.1 Summary__________________________________________________________45
5.2 Transmission time and skew___________________________________________45
4 P3 k" n; K0 v2 M8 w4 q5 V' N5.3 Effects of termination resistance _______________________________________46
5.4 Lattice diagram _____________________________________________________48
5.5 Examples of Real Lines ______________________________________________49
5.6 Simulation code ____________________________________________________51
% ?( Q3 i3 x4 A5.7 Examples of results__________________________________________________54
5.8 Review questions ___________________________________________________55

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6 Design guide for interconnection ____________________________________________57

1 x3 I9 V- d! v; E. E' N+ u8 M/ s6.1 Summary__________________________________________________________57
6.2 Incident wave switching ______________________________________________57
& _) O& E& s6 d) W6.3 Effects of capacitive loading __________________________________________58
6.4 Termination circuits _________________________________________________59
8 K3 D+ l% Z. F+ a: @6.4.1 Passive termination______________________________________________60
# n+ u1 l) P7 b, O  Y6.4.2 Low power termination___________________________________________61
6.4.3 Active low power termination circuit. _______________________________61
6.5 Driving point-to-point lines ___________________________________________62
% V7 t1 @7 @6 U' a6.6 Driving bused lines __________________________________________________64
6.7 Design guidelines ___________________________________________________67
6.8 Review questions ___________________________________________________67

snowwolfe

Signal Integrity in Digital Circuits ___________________________________________70
! j2 j! B) V' R8 ]( ~( B. I; a7.1 Crosstalk __________________________________________________________70
7.1.1 Summary______________________________________________________70
. v  L- I9 A) c, b, N* q7 C/ U7.2 Examples of signal integrity problems ___________________________________70
7.3 Simplified Model for Crosstalk Analysis _________________________________71
4 t6 S9 T3 |* n: T7.4 Forward and backward crosstalk _______________________________________74
7.5 Examples__________________________________________________________76
6 r8 K& e4 p( \9 s- J# L5 y: M$ G$ X7.6 Near-end and Far-end crosstalk ________________________________________80
7.7 Review questions ___________________________________________________81
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8 Design Guide to Handle Crosstalk ___________________________________________85

( g: t! `$ A: a9 s( M7 n# D' e8.1 Summary__________________________________________________________85
8.2 Effects of Crosstalk __________________________________________________85
0 G& N+ f1 _% B7 A2 G( k8.3 Passive countermeasures _____________________________________________86
8.4 Active Control of Crosstalk ___________________________________________92
4 w- ~4 K0 n" U/ G8.5 Review questions ___________________________________________________94
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9 Ground Bounce and Switching Noise_________________________________________97

9.1 Summary__________________________________________________________97
9.2 The totem pole Current Spike__________________________________________97
9.3 Current flow in the output capacitance __________________________________100
9.4 Total Ground Bounce _______________________________________________100
7 r, q) @. [8 q& c; x4 ?  P# y, U9.5 Review questions __________________________________________________105
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10 Design Guide for Ground & Power Distribution _____________________________107

10.1 Summary_________________________________________________________107

PCB Designer’s SI Guide Page 3 Venkata

, Q1 B1 P: L* _8 S0 y6 u0 U; t10.2 Decoupling Capacitors ______________________________________________107
4 s+ V/ e5 T, K8 K! E10.3 Placement of bypass Capacitors _______________________________________113
10.4 Ground and power distribution________________________________________114
, R5 E! s5 _' D' v10.5 Clock distribution __________________________________________________115
3 x, N9 x9 k2 ]% E0 o* {7 f4 r+ x5 Z10.6 Review Questions __________________________________________________118
11 Laboratory Experience _________________________________________________120
11.1 Summary_________________________________________________________120
11.2 Aim of the experience_______________________________________________120
11.3 Generator Parameters _______________________________________________122
11.4 Cable Parameters __________________________________________________123
; {* ~; |& l1 L8 K* W) J7 }11.5 Mismatch at driver and at termination __________________________________124
) x/ x7 K* @; U  h) h11.6 Capacitive Load ___________________________________________________125
11.7 7. Time-domain reflectometer ________________________________________127
8 ?5 @( P1 g( Y0 l# v5 s4 N8 G11.8 Driving the line with logic devices _____________________________________128
12 SI Analysis Strategy____________________________________________________133
12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133
. o/ T3 w! r9 D( {  X6 {12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133
7 {# |8 I0 s, M0 Z. C' S12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
12.3 SOLUTION SPACE ANALYSIS _____________________________________135
" A& H! M+ o1 p6 S7 j- s12.3.1
7 O. S8 L( w1 o9 S9 O* {9 w* NSTEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
4 V3 U, H; ~/ v( l- d* P0 o12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
  x! f5 o7 F/ A' C12.3.3
STEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
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; R9 y: Z0 v- Z! I5 tSTEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136
12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136
& s& P' _4 {5 O4 q: L/ Z12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137
, x" V: \+ \/ Y% R" g9 D$ T12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137
12.3.8
STEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137
$ d0 E$ P& p& k" {" _12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138
% w) T5 M$ C& T9 [1 @% \6 {12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139
* d% C1 o, Y5 s' h* u  x7 w( D12.4 CONCLUSION____________________________________________________139
13 Glossary _____________________________________________________________141

PCB Designer’s SI Guide Page 4Venkata

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