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各位大神,小弟新使用MSP430F6726A做开发,遇到晶振不起振问题,头疼不已,还请各位大神指点迷津。
: O2 G' _7 O" W主要问题:使用32.768kHz晶振接mcu24,25管脚(XIN,XOUT),根据规格书使用12pF的匹配电容,晶振不起振,更换3pF,6pF,9pF,15pF,22pF,30pF,47pF匹配电容还是不起振,询问ti技术人员也没给出具体解决办法,基本上也是从PCB布线,电容匹配方面给分析的,但都已试过,没起作用,由于此款MCU自带晶振,外部晶振不起振会转到内部晶振起振,以下是源码部分从TI官网上弄得:
! e/ V# o, g* K! K6 x9 pvoid Systerm_Clock_init(void). y4 Q% y+ B/ k$ m, a- [
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volatile unsigned int i;
# M; [4 p' r* K3 U8 N# C; W' H PJDIR |= BIT0 | BIT1 | BIT3; //ACLK, MCLK, SMCLK set out to pins: ?5 s0 H4 ^+ j% \
PJSEL |= BIT0 | BIT1 | BIT3; //PJ.0,1,3 for debugging purposes.
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// Setup UCS * q; W" g$ W; k' H. d" D
// Loop until XT1 fault flag is cleared% {% N4 @2 e' A3 b
do
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UCSCTL7 &= ~XT1LFOFFG; //Clear XT1 fault flags- P* E+ C/ `1 i2 }$ {, C, E" n
} while (UCSCTL7 & XT1LFOFFG); //Test XT1 fault flag" o& ~! Z6 |# U; @9 r5 o9 t' [6 `
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UCSCTL6 &= ~(XT1OFF); //XT1 On, C( M, n5 d0 L* Y5 t
UCSCTL6 |= XCAP_3; //Internal load cap F, ^5 J' ]2 I' u0 @" v' Y
__bic_SR_register(SCG0); // Enable the FLL control loop
/ ^1 s1 g, D, ~6 b9 |7 R$ C UCSCTL0 = 0x0000; //Set lowest possible DCOx, MODx
: Z( k' J& [' p; e; D UCSCTL1 = DCORSEL_5; //Select DCO range 16MHz operation
) W& B' z# A7 |1 G5 q2 O! I: ^ UCSCTL2 = FLLD_0 + 511; //(N + 1) * FLLRef = Fdco=(487 + 1) * 32768 =15990784Hz= 16MHz 1 V' b0 H3 C" w! v y
__bic_SR_register(SCG0); //Enable the FLL control loop3 N, Z2 q, X* q# z- _- j* ]
__delay_cycles(600000); //32 x 32 x 16 MHz / 32,768 Hz = 500000 = MCLK cycles for DCO to settle
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UCSCTL4 |= SELA_0+SELS_3+SELM_3; //Set ACLK = XT1,SCLK=MCLK=DCOCLK=16M/ H6 Z% A/ I" D; z
UCSCTL6 &= ~(XT1DRIVE_3); //XT1 stable, reduce drive strength*/
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实在不清楚到底哪出问题了,还望使用过此芯片的大神给指导一二。0 Y* C9 g# h0 }$ D% _: d
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